JPH02113295A - Video converting device - Google Patents

Abstract

PURPOSE:To increase the number of picture elements of a large-sized display device and also make a multilevel display by one device by storing video signals of respective divided image planes in corresponding memory circuits, reading them by plural devices at a time according to display order and performing conversion by a picture element converting circuit and displaying images on corresponding binary display displays. CONSTITUTION:A graphic memory 10 is divided into blocks A-D, which are displayed on the binary displays 12-15. Then a video converting device read data out of the blocks A-D in order and reads respective blocks at the same time, they are transferred to the binary displays 12-15, and at this time, one picture element 11 of a graphic memory 10 is converted into binary display data of a picture element matrix 16 according to its multilevel. Consequently, an image to be displayed on a large-sized display device can be easily generated by one device, the number of display picture elements is handled flexibly, and the multilevel display is made.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a video conversion device that converts a video signal created by a computer or the like into a video signal necessary for displaying on a large color display device or the like. It is something.

[Conventional technology]

Large color display devices with meter-sized diagonals have been put to practical use in a variety of fields, including advertising, environmental displays, and information display for large numbers of people. There are two typical methods for realizing large color display devices: projection type and direct viewing type. The projection type optically enlarges and projects the image onto the screen, making it easy to obtain a large display device, but since the screen also reflects ambient light, it cannot be used in bright lighting environments. Since the image is directly monitored by lining up with
Less affected by ambient lighting conditions. An example of a large direct-view display device is a display device in which a display module consisting of a liquid crystal display unit and a light source is arranged in a tiled manner, or an L
There are display devices with arrays of light emitting elements such as EDs, CRTs, and fluorescent display tubes (Reference: "Large screen display" Journal of the Society of Television Engineers, Vol. 38. No. 1.1984)
and “Large Screen Display-1, Overview”, Information Processing, Vol. 27° No. 7.1986). However, since a large number of light emitting elements are used, there is a problem in that power consumption is extremely large.

On the other hand, a transmissive liquid crystal display (transmissive LCD)
) and optical fibers (for example, Japanese Patent Application Laid-Open No. 1983-1999)
(See Publication No. 11594 "Color Display Device").

This type of display device is a device in which one end of an optical fiber is arranged in close contact with the glass of an LCD to optically couple it to a transmissive LCD, and the other end of the optical fiber is arranged and used as a display surface. . The light from the back of the transmissive LCD is blocked or transmitted by the electro-optic light shutter function of the liquid crystal, so the displayed image on the liquid crystal is displayed on the other end of the optical fiber.
Since the pixels are arranged at a pitch of 10 to 20 mm, a large meter-sized display device can be easily obtained. A feature of the display device is that the number of pixels can be easily expanded by simply increasing the number of transmissive LCDs and optical fibers. Also, L.C.
Since D can be used as an information display for electronic computers, it has the feature of easily displaying characters and figures.

If the display speed of the LCD is fast, moving images can also be displayed.

Colorization of this type of device includes a method using a color LCD and a method using a monochrome LCD.

A color LCD generally has a configuration in which red, blue, and green micro color filters are arranged for each pixel on opposite glass, and color display is obtained by additive color mixture. However, black and white LC
It requires a pixel density three times that of D, which is expensive, and
Since the light transmittance is extremely low, the display pixels become dark. On the other hand, the method of using a monochrome LCD is to provide three LCD sides, irradiate red, blue, and green light respectively, and bundle the three optical fibers of red, blue, and peripheral optical fibers into one on the display surface. Can express 8 colors. Since a black and white LCD has several times the light transmittance compared to a color LCD, a bright display screen can be obtained. Furthermore, in order to improve the expressive ability of a display device, it is necessary to be able to handle gradation display.

[Problem to be solved by the invention]

A video conversion device that controls such a large display device that combines a transmissive LCD and an optical fiber needs to be able to support one-gradation display with an expanded number of display pixels. Furthermore, since the method of arranging the optical fibers on the LCD varies depending on the diameter of the optical fiber, the manufacturing precision of the diameter, the number of pixels per display, etc., it is necessary to have a configuration that can flexibly accommodate the arrangement method.

An object of the present invention is to provide a large display device that combines a binary display and an optical fiber to display information on a CR7 screen of an electronic computer, etc. in meter size. An object of the present invention is to provide a video conversion device that can be easily expanded.

Another object of the present invention is to provide a video conversion device that allows the large-sized display device to display gradation using a simple method.

(Means for Solving the Problems) A video conversion device according to the present invention includes a plurality of first memory circuits that store video signals, and a pixel matrix that displays the video signal of one pixel in binary according to the brightness level. a plurality of pixel conversion circuits that convert the display screen into a plurality of screens, and convert the video signal of each divided screen into the corresponding first pixel conversion circuit.
The data is stored in a memory circuit of the first memory circuit, and has a control circuit that simultaneously reads data from the first memory circuit in a plurality of devices according to the display order, converts the data in the pixel conversion circuit, and displays the data on the corresponding binary display. be.

The device also includes a second memory circuit that stores display position information for displaying the video signal on the binary display, and when the read data of the second memory circuit is in the first state, the first
The read data of the first memory circuit is transferred to the pixel conversion circuit, and the address of the first memory circuit is updated.
When the read data of the first memory circuit is in the second state, data that makes the pixel matrix completely white or completely black is transferred to the pixel conversion circuit, and address updating of the first memory circuit is stopped, and the first memory circuit is read out. The second memory circuit controls the display position of the video signal on the binary display.

[Function] In this invention, the display screen is divided into a plurality of screens, and the video signal of each divided screen is stored in the corresponding first memory circuit, and the data of the first memory circuit is read out simultaneously in the display order of multiple devices. The pixel is converted by a pixel conversion circuit and displayed on a corresponding binary display.

Furthermore, in the case of a device having a second memory circuit, the display is displayed at a predetermined position on the binary display according to display position information consisting of the first state and the second state.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a conceptual diagram showing the basic processing contents of the present invention. 10 is a graphic memory built into an electronic computer or the like. Here, it is assumed that the memory is a graphic memory capable of gradation display. Data in the graphic memory 10 is sequentially read out along the scanning line direction as indicated by dotted arrows and displayed on a CRT or the like. It is assumed that the graphic memory 10 is divided into blocks of 160 pixels horizontally and 100 pixels vertically, and blocks A, B, C, and D are displayed on binary displays 12, 13, 14, and 15 of 640×400 dots, respectively. Here, the video conversion device is blocks A, B,
Data C and D are read out sequentially along the scanning direction of the solid arrow, and four blocks are read out simultaneously and transferred to the binary displays 12.13 and 14.15. At this time,
One pixel 11 of the graphic memory 10 is converted into binary display data like a 4×4 pixel matrix 16 according to its gradation level.

FIG. 2 is a diagram showing optical fibers arranged on a binary display. In the figure, 16 is a 484 pixel matrix on a binary display.

17 is an optical fiber, and the figure is a cross section thereof. It is assumed that the diameter of the optical fiber 17 is approximately equal to the width of 4 bits. The light transmitted through the pixel matrix 16 is incident on one optical fiber 17. Gradation can be expressed by varying the number of black pixels in the pixel matrix 16.

FIG. 3 is a block diagram showing a configuration example of the present invention based on the conceptual diagram of FIG. 1. The input video signal is an analog signal with 16 levels of gradation.

30 is an A/D converter which converts an analog video signal into a 4-bit digital signal. 310°311, 3
20. 321. 330. 331. 340.34
1 is a memory (V
RAM) and block A.

Two surfaces α and β are provided for each of B, C, and D. One VR
When the AM is in write mode, the other VRAM operates in read mode. For example, when the switching signal 350 is “Lo”
At w level, VRAM 310, 320, 3 on α side
30.340 is write mi mode, β side VRAM311
, 321, 331. 341 operates in read mode;
When the switching signal 350 is at "High" level, the operation is reversed. Furthermore, in the write mode, blocks A, B, C, and D are selected in this order according to the screen scanning direction, and video signals are stored. In the read mode, blocks A, B, C, and D are simultaneously selected and held data is read out. 312, 322, 332, 342 are selection circuits which select data in the VRAMs 311.321, 331.341 on the β plane when the switching signal 350 is at the “Low” level, and select data in the VRAM 31 on the α plane when the switching signal 350 is at the “High” level.
Data of 0.320 and 330.340 are selected and output to pixel conversion circuits 313, 323, 333, and 343.

Pixel conversion circuits 313, 323, 333, and 343 are read-only memories (ROM) 314, 324, and 33, respectively.
4,344 and selection circuit 315, 325, 335.345
It consists of ROM314, 324, 334.34
4 stores a 4×4 pixel matrix corresponding to the gradation level, and selects circuits 312, 322 and 332, respectively.
．． The pixel matrix is read out using the output data of 342 (that is, the digitized video signal) as an address. The selection circuits 315, 325, 335, and 345 are controlled by the control circuit 351 to sequentially select pixel matrices from the top along the scanning line direction of the binary display and transfer them to the binary display.

360 is the VRAM 310, 311, 320.321
, 330, 331, 340.341 are commonly controlled.
This is an address circuit for reading RAM, and reads VRAM consisting of four blocks at the same time. The horizontal address of the VRAM is generated by an address counter 362 that is updated with a clock whose period is four times that of a dot clock (Dot CLK) that transfers one pixel of a digitized video signal by a 1/4 frequency divider circuit 361. Further, the address is updated in synchronization with a blanking (BL) signal indicating that the video signal is valid. The vertical address of the VRAM is updated by an address counter 364 using a clock whose period is four times the period of the horizontal synchronization signal Hs by a 1/4 frequency divider circuit 363.
is generated.

Further, the address is updated in synchronization with a vertical blanking (BL Vs) signal indicating that the video signal is valid.

370 is a VRAM write address circuit common to the VRAMs of each block. Address counter 371 updates VRAM horizontal address with Dot CLK
is generated. Further, by clearing the address counter 371 with the BL number, the address counter 371 is updated only during the period when the video signal is valid, similar to the read address circuit. 372 is a chip select circuit, 373 is an address counter 371
This is a carry signal output from the address counter 371 when the address counter 371 counts 640 pixels in the horizontal direction. 374 is an address counter that generates a VRAM vertical address, and updates the address when a carry signal 373 is output. Furthermore, when the number of vertical scanning lines is counted to 100, a carry signal 375 is output.

CSI to CS4 are chip select signals that sequentially select the write state of VRAM in each block, and when the carry signal 375 from the address counter 374 is output, 1! to all VRAMs until the next vertical synchronization signal arrives.
Control is performed to prohibit F loading. Note that ■■ of the VRAM read address circuit 360 and ■■ of the VRAM write address circuit 370 are both VRAM 310
, 311.320, 321, 330, 331, 340.
341.

The operation of the video conversion apparatus of the present invention having the above-described configuration will be explained using timing charts.

FIG. 4 is a timing chart when writing to VRAM. Switching signal 350 is “Low” level) Lt (7)
M, a-side VRAM310, 320, 330.340
enters the write mode, and sequentially stores the output data of the A/D converter 30, which is a digitized video signal.

The first 160 pixels in the horizontal scanning period are stored in the VRAM 310 with the chip select signal CSI set to "LOW." Thereafter, the 160 pixels are sequentially stored in the VRAM 320, 330° 340. When all 640 pixels are stored, the address Since the counter 371 outputs a carry signal 373, the VRAM vertical address is updated and the pixels of the next horizontal scanning line are stored in sequence.The same operation is repeated until the 100th 0 scanning line.Address counter 3
74 is a carry signal 3 when counting 100 scanning lines.
75, so the chip select signals C51 to CS
4 are all set to "High" level, and all VRAMs are in a write-inhibited state until the next vertical signal arrives. In this way, the video signal is written to the VRAM, but as a result, the blocks A and B of the graphic memory 1o in FIG.
, , C, D images are stored in VRAMs 310, 320, respectively.
330, 340.

On the other hand, β-plane (7) VRAM311, 321, 331.3
41 operates in the read mode since the switching signal 350 is at "Low level". A timing chart of the read mode is shown in FIG.

The addresses of the address counters 362 and 364 are cleared by the vertical synchronization signal Vs. The horizontal address is updated at a cycle four times that of Dot CLK during the period when the video signal is valid, and
, 341. The address is updated during the horizontal scanning period, but the address is cleared again by the next horizontal synchronization signal Hs. However, since the vertical address is updated at a cycle four times that of the horizontal synchronization signal Hs, the contents of the same vertical address are read during four horizontal scanning periods.

The data read from the VRAMs 311, 321, 331.341 are sent to pixel conversion circuits 313, 323.341, respectively. ．．
333,343 ROM 314.324,334.3
A 4×4 pixel matrix predetermined corresponding to the brightness level of the video signal is input to the address 44 and output to the selection circuits 315, 325, 335, and 345. Further, as described above, since the same vertical address is output within the four horizontal scanning periods, the same pixel matrix is read out during the four horizontal scanning periods. Control circuit 35
1 outputs a control signal for sequentially selecting rows of the pixel matrix in synchronization with a horizontal synchronizing signal, as shown in the timing chart of FIG. That is, the selection circuits 315, 325,
325 and 345 select the top 4 bits of the row corresponding to this scanning line in the first horizontal scanning period, select the 4 bits in the second row in the next horizontal scanning period, and then switch sequentially. Four bits of the pixel matrix are selected and transferred to a binary display.

As mentioned above, 1 with the gradation level shown in Fig.
Blocks A and B of 60x100 pixels.

Data to be displayed on 12 to 154 binary display screens of 640 x 400 dots C and D is generated.

FIG. 6 is a block diagram showing another embodiment of the invention. The embodiment shown in Fig. 3 is a video conversion device necessary for an optical fiber display in which optical fibers are closely arranged on a binary display as shown in Fig. 2, and the video signal is displayed on the entire surface of the binary display. This is an example of a configuration in which On the other hand, the embodiment shown in FIG. 6 is an example of a configuration in which a video signal is displayed at a predetermined position on a binary display. For example, as shown in FIG. 7, this is the case of an optical fiber display in which 4x2 optical fibers are brought into close contact with each other to form blocks, and the blocks are arranged with one gap left, right, left, and right.

In the arrangement shown in FIG. 7, the video signals of blocks A, B, C, and D are displayed on an 800×600 dot binary display.

In FIG. 6, 70 is a mask button ROM that stores information specifying the display position of the pixel matrix;
Represents the position where the optical fiber is placed. When the optical fibers 17 are arranged as shown in FIG. 7, the capacity of the ROM is 200 bits horizontally and 150 bits vertically, taking into account the gaps between blocks. When this ROM output is "1", a pixel matrix is displayed, and when it is "0", all white or all black, which is unrelated to the video signal, is displayed. Reference numeral 71 designates an address circuit for the mask button ROM 70, which has the same configuration as the VRAM read address circuit 360 in FIG. 3. Therefore, the mask button ROM 70 performs D during the period when the video signal is valid.

It is read out at a cycle four times as long as t CLK, and the same pattern is read out during four horizontal scanning periods. 72 is the VRAM
310,311,320,321,330.311,3
This is a VRAM read address circuit that commonly controls 40 and 341. The configuration is almost the same as the VRAM read address circuit 360 shown in FIG.
When #, the address is updated; when it is "0", the address is held without updating. 720 and 721 are AND gates. In addition, selection circuits 312, 322, 332, 34
The output data of No. 2 is ANDed with the output of the mask pattern ROM 70 and sent to the ROM 314 and ROM 314 of the pixel conversion circuit, respectively.
It is input to addresses 324, 334°344. In this example, the output of the mask button ROM 70 is "0", that is, white is displayed where there is no optical fiber. In addition, VR
Since the other configurations such as the AM write address circuit 370 are the same as those in FIG. 3, illustration of the configuration and explanation of the operation will be omitted.

The operation of the embodiment shown in FIG. 6 having the above configuration will be explained below.

For example, as shown in Figure 8, a video signal with a gradation level of 15.8.3.10 along the horizontal scanning direction is stored in a VRAM.
311, and at this time, the mask button ROM7
For example, the output of 0 is “1” for the first state, and “0” for the second state.
Assume that 110011'' are sequentially read out to indicate the state of .The first two pixels are displayed on the binary display as a 4×4 pixel matrix according to the gradation level by the pixel conversion circuit 313.Next For the two pixels, the output of the mask button ROM 70 is "0", so all "0" is input to the pixel conversion circuit 314 and a pixel matrix of all white display is output, and at the same time, the output of the VRAM read address circuit 72 is The addresses of address counters 362 and 364 are held without being updated.Mask button RO
Since the next output of M70 is "1", the next video signal is read out and a pixel matrix corresponding to the gradation level is displayed on the binary display. By repeating the above operations, a video signal is displayed at the locations where the optical fibers 17 are installed, and completely white is displayed at the locations where the optical fibers 17 are not present. In this embodiment, white is displayed where there is no optical fiber 17, but the selection circuits 312, 322, 33
By changing the logic between 2, 342 and the mask button ROM 70, black display can be easily achieved.

Note that in FIG. 'iA8, only the mask pattern in the horizontal scanning direction is shown, and the mask pattern in the vertical direction is omitted.

In addition, when handling color video signals, red, blue,
The video conversion device described in FIG. 3 or FIG. 6 may be provided for the green video signal, respectively, and the same processing may be performed.

In this case, mask baton ROM70. Control circuit 351.
Mask button ROM address circuit 71. VRAM read address circuit 360. The VRAM read address circuit 72 and the VRAM write address circuit 370 may be common to video conversion devices for each color.

〔Effect of the invention〕

As is clear from the above description, the present invention includes a plurality of first memory circuits that store video signals, and a plurality of first memory circuits that convert the video signal of one pixel into a binary display pixel matrix according to the brightness level. The display screen is divided into multiple screens, the video signal of each divided screen is stored in a corresponding first memory circuit, and the data of the first memory circuit is simultaneously read out from multiple devices according to the display order. Since it has a control circuit that converts the image signal using a pixel conversion circuit and displays it on the corresponding binary display display, it is possible to provide memory (VRAM) for storing video signals corresponding to the number of binary display displays. A single video conversion device can control multiple binary displays. Therefore, there is an advantage that a video conversion device can be provided at a low cost, and that a video to be displayed on a large display device can be easily generated using a single computer or the like. In addition, the number of display pixels on large display devices is also
Since it is only necessary to add AMs, there is an advantage that the number of display pixels can be handled extremely flexibly.

Furthermore, since it is equipped with a pixel conversion circuit that generates a binary pixel matrix corresponding to the brightness level of the video signal,
Even if a value display is used, there is an advantage that gradation can be displayed simply by changing the number of black pixels in the pixel matrix.

Furthermore, if a device is provided with a second memory circuit that stores position information for displaying a pixel matrix on a binary display, this second memory circuit can be used even if the arrangement of optical fibers installed in the binary display is diverse. Since it is only necessary to change the contents of the circuit, it has the advantage of being able to flexibly adapt to the screen configuration of a large display device.

[Brief explanation of the drawing]

FIG. 1 is a conceptual diagram showing the basic processing contents of this invention, FIG. 2 is a diagram showing an example of the arrangement of optical fibers in this invention,
FIG. 3 is a block diagram showing the configuration of an embodiment of the present invention;
4 is a timing chart for writing to VRAM in the embodiment shown in FIG. 3, FIG. 5 is a timing chart for reading the same (VRAM), and FIG. 6 is a block diagram showing the configuration of another embodiment of the present invention. 7 is a diagram showing the arrangement of optical fibers in the present invention, and FIG. 8 is a diagram showing a processing example in the embodiment of FIG. 6. In the figure, 10 is a graphic memory, 11 is a pixel, 12 ，
13, 14, 15 are binary display displays, 16 is a pixel matrix, 17 is an optical fiber, 30 is an A/D converter,
310,311,320.321,330,331,3
40, 341 is a main f-1, 1 (VRAM), 350 is a switching signal, 312, 322, 332, 342 is a selection circuit, 313, 323, 333, 343 is a pixel conversion circuit, 3
14.324, 334.344 are read-only memories (
ROM), 315, 325, 335° 345 is a selection circuit, 351 is a control circuit, 360 is a VRAM read address circuit, 361.363 is a 1/4 frequency divider circuit, 362.
364 is an address counter, 370 is a VRAM write address circuit, 371 and 374 are address counters,
372 is a chip select circuit, 373 and 375 are carry signals, 70 is a mask button ROM, 71 is an address circuit for the mask button ROM, and 72 is a VRAM read address circuit. Figure 1 Figure 2 Figure 7 Horizontal power Figure Figure Figure Horizontal scanning direction Horizontal scanning direction Video signal after pixel conversion

Claims (2)

[Claims] (1) In a video conversion device for displaying video with gradation information on multiple binary display displays, a plurality of first memory circuits that store video signals and a video signal of one pixel are converted to a brightness level. and a plurality of pixel conversion circuits that convert into a binary display pixel matrix according to the pixel matrix, the display screen is divided into a plurality of screens, and the video signal of each divided screen is stored in the corresponding first memory circuit. A video conversion device comprising: a control circuit that simultaneously reads data from the first memory circuit in a plurality of devices according to the display order, converts the data in the pixel conversion circuit, and displays the converted data on a corresponding binary display. (2) The first part that displays the video signal on a binary display
a second memory circuit that stores display position information consisting of a state and a second state, and when the read data of the second memory circuit is in the first state, the read data of the first memory circuit is transferred to the pixel conversion circuit and the address of the first memory circuit is updated so that when the read data of the second memory circuit is in the second state, the pixel matrix becomes all white or all black. a control circuit that transfers data to the pixel conversion circuit, stops updating the address of the first memory circuit, and controls the display position of the video signal on the binary display in the second memory circuit; The video conversion device according to claim 1, characterized in that: