JPH02110397A - Stepping-motor driving circuit of hand type electronic clock - Google Patents

Abstract

PURPOSE:To alleviate the current consumption of a step motor by obtaining the effective value of the minimum pulse by which the step motor can be rotated, and avoiding the driving with a small pulse which does not reach said effective value. CONSTITUTION:A pulse signal phi1 is inverted with an inverter 16. The signal is imparted to the gate of a switching transistor 15. The transistor is made to be an ON state for a specified time period (pulse width of the pulse signal phi1). The signal is directly inputted into an input line I1 of a decoder part 19. All gate elements on the input line I1 are turned ON for above described specified time period. Since all gate elements on input lines I3, I5 and I7 have been already made ON, an opening/closing control signal Y1 is outputted. A driving transistor Tr1 is made to be an ON state for above described specified time period. The pulse whose pulse height is the smallest is applied to a driving coil (not shown).

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a step motor drive circuit for a pointer type electronic timepiece that changes the drive pulse of the step motor according to the load.

[Prior art and its problems] The conventional method of controlling the driving pulse of the step motor of a pointer-type electronic watch is, for example, pulse width control. By providing several stages of pulse widths up to a certain small pulse width that is effective in reducing When non-rotation is detected, a correction pulse with the maximum pulse width is used to compensate for the non-rotation, and thereafter, the width of the drive pulse every second is set to one step larger than that when non-rotation occurred. If the step motor is driven for a certain period of time (for example, 1 minute), and no non-rotation is detected during that 1 minute, the pulse width is returned to one step smaller, that is, the drive pulse used when non-rotation occurred, to reduce the current consumption of the step motor. It was something that was overwhelming.

Therefore, due to variations in characteristics among individual step motors, some step motors may not rotate with the above minimum pulse width, and in such cases, the pulse width must be lowered one step at a time until the minimum pulse width is reached. It stops rotating every time it reaches the maximum pulse width for correction. Therefore, the drive pulse continues to fluctuate between the maximum pulse width and the minimum pulse width at -regular intervals, and is of no use in reducing current consumption.

[Object of the Invention] The present invention has been made in view of the above-mentioned circumstances, and provides a step motor drive circuit for a pointer-type electronic timepiece that can constantly supply the step motor with pulses effective for reducing the current consumption of the step motor. [Summary of the Invention] In order to achieve the above object, the present invention determines the effective value of the minimum pulse that allows the step motor to rotate, and drives the step motor with small pulses that do not reach this effective value. The main points are the things that should not be done.

[Example] The present invention will be specifically described below based on an example shown in the drawings. In this embodiment, the effective value of the drive pulse is adjusted by the pulse height (voltage).

1 is a diagram showing the circuit configuration of this embodiment. An oscillation circuit 1 is a circuit that constantly sends out a basic clock signal of a predetermined frequency, for example, 32 KHz.

The frequency dividing circuit 2 is a circuit that divides the basic clock signal from the oscillation circuit 1 to a constant frequency and sends it to the pulse generating circuit 3. The pulse generation circuit 3 is the frequency dividing circuit 2
Pulse signals φ1' and ≠2' as shown in FIGS. 5(a) and 5(b) are created from constant frequency signals from This is a circuit that gives or gate 4
is a circuit that inputs the pulse signal φ1' and the pulse signal φl'' from the CPU10 and supplies them as the pulse signal φ1 to the drive circuit 6.The OR gate 5 is
This circuit inputs the pulse signal φ'2 and the pulse signal φ2'' from the inverter 16 and supplies them as the pulse signal φ2 to the drive circuit 6. Signal CI from 9
, C2, and C3, and applies a drive pulse of a predetermined pulse height to the drive coil 7 based on these. A drive current is passed through the drive coil 7 by the applied drive pulse, and a corresponding magnetic flux is generated, which applies torque to the rotor (not shown) of the step motor to generate a 180
The zero-rotation detection circuit 8, which rotates the rotor by ', takes in the induced electromotive force generated in the drive coil 7 at the rotation timing of the rotor via the drive circuit 6, and detects rotation or non-rotation of the rotor from the induced electromotive force, This is a circuit that sends a detection signal Z to the CPU10 when the rotation is non-rotating. The switch SW receives 8 types of predetermined pulses with different pulse heights (each pulse is sequentially given a pulse number 〇, 1.2...7, starting with the pulse with the lowest pulse height). This switch is operated to set the minimum pulse height (hereinafter referred to as the "minimum pulse") that allows the rotor to rotate, from among the pulses (hereinafter referred to as "minimum pulse").This operation causes a predetermined switch input signal to be sent to the CPU10. . The latch 9 is a circuit that temporarily stores and holds the above-mentioned pulse number sent from the CPU 10 as 3-bit information, and sends signals C1 to C3 corresponding to the above-mentioned 3 bits to the drive circuit 6. Note that the signal C1 corresponds to the digit of 2 to the 0th power, the signal C2 corresponds to the digit of 2 to the 1st power, and the signal C3 corresponds to the digit of 2 to the 2nd power. For example, when pulse number 3 is set in latch 9, Signals CI, C2, and C3 are each 1. l, θ level. The CPU 10 is a circuit that controls each circuit section, and receives the pulse signals φl, φ2' and the detection signal Z.
, further inputs the signal sent when the switch SW is operated, and inputs the pulse signal φ1φ2″ and 3 to the latch 9.
RAMI 1 sends a set signal and a reset signal to RS flip-flop 12, and exchanges data with RAM 11. RAMI 1 has registers A, B, and N, and is under the control of CPU 10. ,CPUl
This is a circuit that stores data sent from 0 and reads out the stored data and provides it to CPU10.

Note that register A is a register in which the pulse number of the minimum pulse is set, and register B is a register in which the pulse number of the minimum pulse is set, and register B is a register in which the pulse number of the minimum pulse is set.
This is a register in which the pulse number of the pulse being applied to the drive coil 7 is set, and the register N is a register used to time when driving is continued for one minute with the same pulse. RS flip-flop 12 is CPU1
It is a flip-flop that is set or reset by the above-mentioned signal from 0, and when in the set state, the output Q is given as a reset signal to the frequency dividing circuit 2 and the pulse generating circuit 3 described above.

FIG. 2 shows the configuration of the drive circuit 6 in detail in relation to the drive coil 7 and latch 9.

The drains of N-channel drive transistors T'1' to Tr8' are connected to one end 7a of the drive coil 7, to which the voltage VDD is applied when the P-channel switching transistor 15 is on. Then, the drive transistor T r + ~T "8'
are opening/closing control signals x1~ from the decoder section 19, respectively.
x8, and the voltage VSS is applied to each source.

The drains of the N-channel drive transistors Tr1 to Tr8 are connected to one end 7h of the drive coil 7, to which the voltage VD+1 is applied when the P-channel switching transistor 17 is in the on state. And drive transistors T r I to T r 8
are the opening/closing control signals Yl- from the decoder section 19, respectively.
ys, and a voltage VSS is applied to each source.

Further, the drive transistor T r I” T r s
' and the saturation value of the drain current IO of the drive transistors T r l to T r 8 are the drain current I in FIG.
As can be seen from the O-drain-source voltage characteristic curve, drive transistors Tr8' and Tr8 are equal and largest, drive transistors Tr1' and Tr7 are equal and second largest, and so on. The drive transistors Tr+' and Tr+ are equal and the smallest, and in FIG.
S, and the drive current is passed through the switching transistor 15, the drive coil 7, and then any of the drive transistors T r l to T r 8, and the switching transistor 17, the drive coil 7, and then the drive transistor T r l' The load straight line when the drive current is passed through either of the paths .about.T and 8' is also shown. As can be seen from the figure, the voltage applied between both ends of the drive coil 7, that is, the drive The pulse heights of the pulses used gradually increase, and in this embodiment, by selecting the drive transistor, 8 pulses with different pulse heights can be generated as described above.
It is possible to select one of the various pulses and apply it to the drive coil 7, and each pulse is sequentially applied with pulse numbers 〇, 1, .
2...7 is given.

P-channel switching transistors 15 and 1
7 are opened and closed by signals obtained by inverting pulse signals φ1 and φ2 by inverters 16 and 18, respectively, and apply voltage MOD to one ends 7a and 7b of drive coil 7, respectively.

Note that one end 7° and 7b of the drive coil 7 are respectively
The electromotive force induced in the drive coil 7 by the rotation of the rotor is connected to the rotation detection circuit 8.
given to.

The decoder section 19 sends three signals 01 to C3 according to the storage contents of the latch 9 and the inverter 20, respectively.
.about.22, and the pulse signal φ1. φ2, and open/close control signals X+"Xa, Y
This circuit sends out any one of + to Y8 as a level of 1.

In the decoder section 19 in FIG. 2, gate elements are indicated by circles at the intersections of the input lines 11 to I8 indicated by vertical lines and the output lines indicated by horizontal lines. The element is such that the input signal applied to the input line passing through the intersection (hereinafter referred to as the input signal applied to the gate element) is 1.
Activate at the level of . Therefore, the opening/closing control signal x1
~x8, Y1~Y8 are sent out when all the input signals applied to all the gate elements on the output lines related to them are in the level (that is, the decoder section 19 has an AND configuration).

Next, the operation of this embodiment configured as described above will be explained with reference to the flowchart of FIG. 4 and the time chart of FIG. 5.

First, the operation for setting the minimum pulse, which is performed after replacing the battery, will be explained.

In this case, the switch SW is operated, but when this operation is detected in step Sl in FIG. Send it to circuit 2 and pulse generation circuit 3 and reset them (
Step S2), as a result, the sending of the pulse signals φ1 ′φ2 ′ from the pulse generation circuit 3 is stopped at -
Next, in step S3, 0 is set in register A of RAM II to designate a pulse with pulse number 0. Further, the 0 set in register A is set in latch 9. As a result, all of the signals 01 to C3 from the latch 9 become 0 level.

input! ! All the gate elements on lI3, Is, and I7 are opened (see FIG. 2).Next, in step S5, a pulse signal φ1'' is sent to the drive circuit 6 via the OR gate 4. (see FIG. 1), and this pulse signal φI is inverted by an inverter 16 and then sent to a switching transistor 15.
is applied to the gate of the pulse signal φ
1 pulse width), and is directly input to the input line II of the decoder unit 19 to open all the gate elements on this input line Il for the above-mentioned fixed time (see FIG. 2). ), input line I3. I5. I7
Since all the gate elements on the input line Il have already been opened, the opening/closing control signal Yl is generated by opening all the gate elements on the input line Il.
The gate elements on the output line of are all open for the predetermined time, the opening/closing control signal Yl is output, and the drive transistor T r I is turned on for the predetermined time. The power source of voltage vDD, the switching transistor 15, the drive coil 7, and the drive transistor T r
1 and the power source of voltage VSS is formed for a certain period of time, and the pulse with pulse number 0, that is, the pulse with the smallest pulse height, is applied to the drive coil 7.

Next, in step S6, it is determined whether the rotor has rotated due to the application of the pulses, based on the presence or absence of the detection signal Z from the rotation detection circuit 8, and if the rotor has rotated, the RS flip-flop 12 is reset (step 5ll). , output Q
The pulse signal φ from the pulse generation circuit 3 is stopped.
1, the transmission of φ2 is restarted, initial setting is made to set register N to 60, and the operation at the time of minimum pulse setting is completed.

On the other hand, when it is determined in step S6 that the rotor has not rotated, a pulse signal φ2# is sent out (step S7). (see figure), is inverted by an inverter 18 and applied to the gate of the switching transistor 17, which is opened for a certain period of time and then applied to the input line X8 of the decoder section 19. Pulse signal φ
? is given to input line 8, this input line 8
The upper gate element is opened for a certain period of time (see FIG. 2), but the input line I3. I5. The gate on I7 is open as mentioned above.

All gates on the output line of the opening/closing control signal x1 are opened,
The opening/closing control signal x1 is sent out for a certain period of time.

Therefore, the drive transistor T r I' is in an ON state for a certain period of time, and a path is created through the power switching transistor 17 of the voltage VDD, the drive coil 7, and the power supply of the drive transistor T r I' voltage VSS, and the drive coil 7 is connected to the power supply of the pulse number O. A driving pulse is applied in the opposite direction to that in step S5. Then, it is determined whether the rotor has rotated due to the application of this driving pulse (step S8). If the rotor has rotated (in this case, it has not rotated in step S5). This is not because the pulse height of the drive pulse was insufficient;
(due to an inappropriate correlation between the polarity of the rotor and the polarity of the field generated by the drive coil 7), described in step 511.
, 512 are performed, and the operation at the time of setting the minimum pulse is completed.

Further, when it is determined in step S8 that the rotor has not rotated (that is, when the pulse height of the drive pulse is insufficient), the pulse still specified by register A is the drive pulse number 7. While confirming that the pulse (the one with the highest pulse height among the pulses that can be applied to the drive coil 7 in this embodiment) has not been reached (step S9), change the pulse number in register A by 1 each time. Make it bigger (Step 5lO),
We consider whether the rotor will rotate with that pulse (steps S4, S5, S6, 57, and S8). In this way, we search for the pulse with the smallest pulse height that can rotate the rotor, and When a suitable driving pulse is found, the process proceeds to steps 88, 311, and 512, and this minimum pulse setting operation is completed.

When the minimum pulse setting operation is completed, the pulse number of the pulse with the smallest pulse height among the pulses capable of rotating the rotor is set in the register A and latch 9.

In the normal part, for example, pulse number 3 is set as the minimum pulse by the minimum pulse setting process described above (that is, pulse number 3 is set in register A and latch 9), and register B is set as the minimum pulse. The explanation will be made assuming that pulse number 3 is set in register A as well.

In this case, since the pulse number 3 is set in the latch 9 as shown in C&) in FIGS. The pulse signal φ1' and the pulse signal φ2' from the pulse generating circuit 3 are sent out alternately at 1-second intervals, so that the pulse signals φ1 and φ2 are also sent out alternately at 1-second intervals. Ru. The rotor rotates by 180° in response to the pulse signals φ1 and φ2.

At this time, each time the pulse signal φl' or φ2' is sent out, the process changes from the standby state (step Sl) to step S1.
Proceeding to step 3, the rotation of the rotor is confirmed, and the value of register N is decreased by 1 to remember that there was one normal rotation, that is, one second has passed (step 314). .

As a result, if the value of register N is not yet 0, the process returns directly to the standby state (step 31), but if the value of register N is 0, the values are set in registers A and B. After confirming that both pulse numbers are 3, the process returns to the standby state (step 51).

(8) Operation when the rotor is rotating If, for some reason, the rotor is overloaded and does not rotate during normal driving as described above, A detection signal Z as shown in (b) of FIG. In order to perform the above-mentioned non-rotational rotation using the pulse with the pulse number 7 having the highest height, set the pulse number 7 in the latch 9. As a result, as shown in (b) of FIGS. , the signals C+, C2, and C3 are all levels, and the input lines I2 .
I4. The gate element on I6 opens (see Figure 2)0
Next, whether the current rotation timing, which was non-rotating, is the timing of the pulse signal φ1' or the timing of the pulse signal φ2'
(step 521), and in the case of the former, the pulse signal φ! Step 322 to send ``
), in the latter case, the pulse signal φ2'' is sent out (step 323), and as shown in (&) in FIG. , the pulse signal φ2 is sent out as shown in (b) of FIG. The gate element on the transistor 17 and the input wire 8 is opened.The gate element on the input llIa is opened, so that (input t&lz, I4
, since the gate elements on I6 are already open), all the gate elements on the output line of the opening/closing control signal x8 are opened,
An opening/closing control signal x8 is sent out (see FIG. 2), so that the power supply of voltage VDD, the switching transistor 17,
Drive coil 7, drive transistor Tr8, voltage VS
A power supply path S is created, and a drive pulse with pulse number 7, that is, the pulse with the highest pulse height, is applied to the drive coil 7, and the rotor rotates.

Note that, contrary to the above case, if the rotation is not performed at the timing of the pulse signal φ1', the pulse signal φ1
'' is sent out, and a pulse signal φ1 is given to the drive circuit 6 (see FIG. 1), which connects the power supply of voltage VDD, the switching transistor 15, the drive coil 7, and the drive transistor Tr.
8. A path for the voltage VSS power supply is created, and the drive coil 7
In this case, as in the above case, a pulse with pulse number 7 is applied in the opposite direction to that in the above case, and the rotor rotates.

As described above, after rotating the rotor with the pulse with the highest pulse height and correcting the non-rotation, check that the pulse number in register B has not yet reached 7 (step 324), then step In S25, the pulse number in register B is set to be 1 larger, that is, 4 in this case, in order to perform subsequent driving with a pulse height that is one step higher than the pulse when non-rotation occurs. Then, pulse number 4 of this register B is also set to latch 9 (step 526), and then, with the pulse of pulse number 4 set to this latch 9,
The register N is set to 60 to continue driving for 60 seconds (step 527), and the process returns to step 31.

In addition, for the next 1 minute, the pulse signal φl' or φ2
′ is sent, that is, every second, step S
1, proceed to step S13, check the rotation of the rotor,
Step 314) to remember the elapse of one second, step 315) to confirm that one minute has not elapsed, and return to step Sl. And when one minute has passed,
This is detected in step S15, and it is determined that the pulse number in register B and the pulse number in register A do not match. Pulse (i.e. drive pulse with pulse number 3)
(step 516), and then set the pulse number of register B to one smaller by 1, that is, 3 in this case (step 517).

The pulse number of register B is also set in latch 9 so that subsequent driving will be performed with pulse number 3 (step 31B), and furthermore, driving with that pulse will be performed with pulse number 1.
Set the register N to 60 to continue for 5 minutes (step 519), and return to step Sl.

Then, for the next 1 minute, pulse number 3 is applied to latch 9.
is set, and signals CI, C2, and C3 are at l, 1, and O levels, respectively (Fig. 5 (ch)).
(see (d) of ~(nu))), pulse signal φ1' or φ2
Each time ' is sent out, driving is performed with a drive pulse of pulse number 3, rotation is confirmed in step 313, and the process returns to step S via steps 514 and S15. Also,
After one minute has elapsed, it is detected in step 515, but since the pulse (pulse number 3 set in register B) has already reached the minimum pulse, the process returns to step Sl via step 51B. Thereafter, unless the rotor stops rotating, the drive is continuously performed with the pulse number 3 (see (e) and (f) in FIGS. 5(h) to 5(n)).

In this manner, driving with pulse numbers 2 and 1, which cannot rotate the rotor, is avoided.

In addition, if non-rotation occurs again after the drive to recover the non-rotation is completed and the motor is being driven with a pulse that is one step higher in pulse height than the pulse at which non-rotation occurred, if non-rotation occurs again. Furthermore, driving is performed with a pulse with a pulse height that is one step higher, and if non-rotation occurs during this driving, driving is performed with a pulse that is one step higher with a pulse height. Then, driving is performed with pulses having larger pulse heights one step at a time (step 525).
．． 526), and in this way, when the drive pulse becomes several steps larger than the minimum pulse, drive with a smaller pulse height by one step every minute unless non-rotation is detected. Transfer (step S17.518),
Return to driving with the minimum pulse (step 516).

It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be modified and applied in various ways without departing from the scope of the present invention.

For example, in this embodiment, the effective value of the drive pulse is changed by the pulse height, but it is of course possible to change this by the pulse width. Furthermore, it is important to note that the setting of the minimum pulse is not limited to being performed by a switch operation, but may be performed automatically when replacing the battery or automatically at regular intervals.

[Effects of the Invention] As detailed above, the present invention determines the effective value of the minimum pulse that allows the step motor to rotate, and avoids driving with smaller pulses that do not reach this effective value. Since the present invention relates to a step motor drive circuit for a pointer type electronic timepiece, it is possible to provide a step motor drive circuit for a pointer type electronic timepiece that can always supply effective pulses to the step motor to reduce current consumption of the step motor.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the circuit configuration of an embodiment of the present invention, FIG. 2 is a diagram showing the drive circuit in FIG. 1 in detail in relation to the drive coil and latch, and FIG. 3 is a diagram showing the drive circuit in FIG. FIG. 4 is a flowchart showing the operation of this embodiment, and FIG. 5 is a time chart in an example of the operation of this embodiment. 1... Oscillation circuit, 2... Frequency dividing circuit, 3
...Pulse generation circuit, 6 ... Drive circuit, 7 ... Drive coil, 8 ... Rotation detection circuit, 9 ... Latch, 10...CPU
, 11...RAM, 12...RS flip-flop, B, 15.17...Switching transistor, 19...Decoder section, T, 1-T
ra, Tr+ "Trs'-...NA'th
transistor.

Claims (1)

[Scope of Claims] Pulse generating means for outputting a plurality of pulses having different effective values; rotation detecting means for detecting rotation or non-rotation of a rotor when a pulse is applied to a step motor; and the plurality of pulses. a minimum pulse detection means for sequentially supplying the pulses to the step motor, detecting a pulse having a minimum effective value at which the step motor can rotate from among the plurality of pulses from the output of the rotation detection means, and storing the detected pulse; , pulse supply means for supplying one pulse among the plurality of pulses to the step motor at a constant period; and non-rotation is detected by the rotation detection means when the pulse supply means supplies the pulse to the step motor. When rotation is detected continuously for a predetermined period of time, the pulse supplied by the pulse supply means is changed to a pulse with a larger effective value, and the supplied pulse is compared with the pulse detected by the minimum pulse detection means. and control means for changing the pulse supplied by the pulse supply means to a pulse having a smaller effective value by one step when the supplied pulse is larger. drive circuit.