JPH0210932A - Phase swing compensation system - Google Patents

Abstract

PURPOSE: To obtain a phase swinging compensation system in which high speed phase jitter compensation with high reliability can be attained by executing the rapid adjustment of a phase jitter compensating means at the time of operating the storage and restoration of a load coefficient parameter. CONSTITUTION: At the time of initial transmission start by each remote MO DEM, an initial training sequence constituted of the 6 segments of a prescribed table 1 is transmitted. This table is constituted of two lines, and the first line indicates the number of symbol intervals of each segment, and the second line indicates the corresponding time. In the initial training sequence, a master MODEM receiver 80 obtains an operating parameter and an equalizer coefficient, and they are stored at a transmission remote MODEM corresponding position in a receiver parameter storage device 130. Afterwards, each transmission by the remote MODEM is started with a short training signal being the latter term training sequence constituted of the 2 segments of a prescribed table 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to a phase fluctuation compensation system for compensating for phase fluctuation signals of a data modem.

[Background technology]

The invention has particular application in high speed modems in switched carrier configurations such as multipoint networks and semi-duplex point-to-point configurations. In such networks and structures, it is desirable that the training sequence provided at the beginning of the transmission be as short as possible.

One problem that occurs with modem communication systems is that the communication channel is subject to various impairments, including carrier phase book and carrier frequency shifts. For example, phase jitter induced in transmission lines, such as telephone lines used in data communications, can be caused by AC ripple in the DC power supplies for oscillators used in carrier systems, by imperfect band filtering, and by digital It is caused by incomplete digitalization of the system. Frequency shifts in transmission lines, such as telephone lines for data communications, are caused by frequency division multiplexing (F
DM) system. Especially in long hall telephone lines, such as those used for semi-open point-to-point communications, high values of phase jitter and frequency deviation occur.

Continuous transmission of both multipoint and point-to-point structures generally begins randomly in time. It is therefore not possible to start the phase book compensation circuit from a state with a previously obtained value and continue tracking.

U.S. Pat. No. 4,320,526 describes a self-weighted summation method that estimates the actual phase noise and provides the difference between the noises through the taps of the delay line and the generated phase error signal. An adaptive phase jitter compensator is disclosed that includes a receiving filter section.

A multiplier receives each tap signal and outputs a product that is used to update the tap weights for use in the filter section. The upmodulator modulates the load sum output and the carrier signal. The output of the upmodulator is provided to a lookup table to form a component compatible with the received data signal. A compound multiplier multiplies these components by the equalized data signal to provide both demodulation and phase jitter compensation.

[Problems to be solved by this invention]

However, the above-mentioned device has a problem with fast and reliable phase jitter compensation.

Accordingly, it is an object of the present invention to provide a phase fluctuation compensation system that achieves fast and reliable phase jitter compensation.

[Means for solving problems]

The present invention solves the problems of the prior art described above by having the configuration as described below. That is, the present invention provides a tapped delay line having a plurality of output taps, and a plurality of corresponding loads that adaptively generate and supply weight coefficients to the plurality of output taps to form a plurality of weighted tap signals. a loading means including a coefficient generating means;
summing means for summing the load tap signals to provide a phase error forecast signal; feedback means for feeding back the error forecast to the input means of the Tasopdo delay line; and a reference signal in response to the phase error forecasting means. a reference signal determining means for generating a reference signal, an error correcting means for correcting the phase fluctuation signal in accordance with the reference signal, and a later modem for storing a plurality of parameters generated by the weighting factor generating means during an initial modem training sequence. and storage means for restoring the stored parameters to the weighting factor generating means during a training sequence.

Storing and retrieving the weighting factors/IP parameters allows achieving very rapid adjustment of the phase jitter compensation means to achieve proper tracking.

〔Example〕

FIG. 1 shows a multipoint data modem communications system 10 having a master modem 12 and three remote modems 14, 16, 18. In an actual system, the number of remote modems may be small or large. Master modem 12
is connected to a master data terminal equipment (DTE) unit 2o, and a remote modem 14, 16.18 is connected to a remote DTE unit 22, 24.26. The master modem 12 is connected via a four-wire telephone transmission line 28 to a branch point 30 which is connected to the respective modem 14, 16, 18 via a four-wire telephone transmission line 32, 34, 36. . As before, the 4-wire telephone transmission line 28, 32
, 34, 36 each include a transmit line pair and a receive line pair. The data is normally transmitted at a carrier frequency of 18 (10) Hz and a modulation frequency of 24 (10) Hz (single rate of 24 (10) Hz).
) & -) with a data bit rate of 14,4(
10) Transmitted in bits/second. The modem has a nominal value of 96 (
10) Operate at a sample clock frequency having a value of Hz, or four times the modulation frequency.

FIG. 2 shows a block diagram of the modem transmitter section of one of the modems 14, 16, 18 of FIG. The data signal from each corresponding data terminal equipment (DTE) is input to line 50.
The signal is supplied to the scrambler 52 via. The output of scrambler 52 is connected via line 54 to the input of encoder 56. Initialization control circuit 57
8 to the encoder 56. Initialization control circuit 57 enables encoder 56 to provide training signals. The output of encoder 56 is connected via line 59 to a ronos filter 60, whose output is connected via line 62 to a modulator 64. The output of modulator 64 is connected via line 66 to a digital-to-analog converter 68 with output cuff 0 connected to the appropriate telephone line (not shown).

FIG. 3 shows a block diagram of mask modem receiver 80. The signals received from the corresponding transmission line are transferred via input line 82 to an analog signal forming a digital sampling means.
A digital converter 84 is provided. Analog-
The day-to-day converter 84 connects via line 86 to a bandpass filter 88 and an energy on/off control circuit 90.
and a timing recovery circuit 92. Timing recovery circuit 92 is connected via line 94 to analog-to-digital converter 84, which controls the sampling time. Energy on/off control circuit 90 is connected to initialization control circuit 98 via line 96. Initialization control circuit 98 is connected to line 1 (10
) to timing recovery circuit 92 through line 10
2 to the key control circuit 104 and further connected to the bandpass filter 88 via a path 106.
connected to the output of Path 106 transmits a multi-value signal as shown by double lines. line 96 when energy on/off control circuit 90 detects energy on line 86.
It should be understood that the initialization control circuit 98 provides a signal to activate the operation of the initialization control circuit 98. The initializer'/-in control circuit 98 supplies control signals to the timing recovery circuit 92, gain control circuit 104, and automatic phase control circuit 118 via control lines 1 (10) and 102.degree. 103.

The input control circuit 104 is connected via a nozzle 102 to a demodulator 110 which is further connected via a path 112 to an equalizer 114. Equalizer 114 is connected via bidirectional path 116 to automatic phase control circuit 118 and from there via bidirectional path 120 to decision circuit 122 . Automatic phase control circuit 1
18 receives a reset input from initialization control circuit 98 via line 103. The decision circuit 122 is connected via a line 124 to a descrambler 126 having an output line 128 provided with signal data representative of data received by the modem receiver 80.

Modem receiver 80 further includes bidirectional paths 132 and 134.
．． A receiver parameter storage unit 130 is included which is connected via 136 to gain control circuit 104, equalizer 114 and automatic phase control circuit 118. Receiver parameter storage unit 130 is configured to store receiver A' parameters and equalizer coefficients at locations associated with the transmitting modem during the initial training sequence and to recover the stored parameters and coefficients during later training sequences. used. The obtained parameters are stored in a location corresponding to the particular remote modem that generated these parameters. This invention essentially relates to the automatic phase control circuit 118,
The remaining circuitry of FIG. 3 is essentially not necessary for a detailed understanding of the present invention.

At the beginning of the first transmission by each remote modem 14, 16.18, an initial training sequence consisting of six segments SG, ~SG, as shown in Table 1 is transmitted.

Table In Table 1 above, the first row (1) shows the number of symbol intervals for each segment)SG1%SC;, and the second row (
The corresponding approximate time (ms) of 2) is shown.

Each segment is specified as follows.

SG,: Segment 1: Alternative (180° phase alternation) SG2: Segment 2: Equalizer condition or turn SG3: Segment 3: Structural sequence SG,: Segment 4: Alternative (180° phase alternation) SG5: Segment 5: Equalizer condition Nose turn S
G,: Segment 6: Scrambled all binary 1 The total number of symbol intervals in the initial training sequence is 3
534, and the total time is approximately 1472 mi! Corresponds to J seconds. Segment S Gl + S G2 HS G
S03 is a conventional training signal segment corresponding to JTT Recommendation v.33. Segment S03 contains conditions regarding set-up conditions such as data bit rate, nature of modulation and other transmission related parameters. .Segment) S G4 is used for calculations regarding timing adjustments. Segment SG5 provides the slight readjustment of the equalizer coefficients required as a result of transmitting segment sG3.

As mentioned above, during the initial training sequence, mask modem receiver 80 obtains operating parameters and equalizer coefficients and stores the coefficients and parameters in corresponding locations of the transmitting remote modem in receiver parameter storage unit 130. be remembered. Each subsequent transmission by the remote modem is 2 as shown in Table 2.
It begins with a short training signal called a late training sequence consisting of two segments.

The late training sequence therefore consists of a first segment formed by 25 symbol intervals of 180° phase alternation, followed by a second segment of 48 symbol intervals of predefined symbols. The remote modem can be recognized by transmitting a set of identification frequencies in synchronization with segment 1 of the late training sequence. Accordingly, previously stored receiver parameters and coefficients can be recovered from a recognized location in the receiver parameter storage unit 130.

FIG. 4 is a block diagram of automatic phase control circuit 118 and its connections to equalizer 114 and decision circuit 122. The output of equalizer 114 is connected to bus line 116 (third
A phase and amplitude correction circuit 150 is connected via a bus 116a forming part of the bus line 12o (FIG. 3), the output of which is connected to a decision circuit 122 via a bus 120a forming part of the bus line 12o (FIG. has an output of Decision circuit 1
22 has an output line 120b carrying a signal representing the amplitude error (or in-phase error), an output line 120c carrying a signal representing the quadrature error, and an output line 120d carrying a signal representing the phase error. . Each line 12
0b, 120c, and 120d form part of bus 120 (FIG. 3) and are connected to amplitude error correction determination circuit 152, reference vector determination circuit 154, and phase jitter compensation determination circuit 156, respectively. Their connection is line 120b
, 120c and paths 116b to mates 158, 16
0 and carries a complex-valued signal. Bus 116b is connected as a first input line to a complex-valued multiplier 162, which has a second input bus 116c from reference vector determination circuit 154, and at the same time multiplier 16 is supplied with a constant C.
It has an output path 116d connected to 4. Complex multiplier 162 multiplies the complex-valued input on path 116b by the complex value of the complex-valued input on path 116c. Therefore, the imaginary part of the complex-valued signal on path 116c is inverted with an inverter (not shown) prior to multiplication. The output of multiplier 164 is connected to equalizer 114 via path 116e.

Amplitude error correction determination circuit 152 is connected to phase and amplitude correction circuit 150 via line 170.

Phase jitter compensation determination circuit 156 has an output connected to vector generation circuit 174 via line 172 and has a complex-valued output connected to reference vector determination circuit 154 via path 176.

The complex value output of the reference vector determination circuit 154 is connected to a path 178.
a path 11 connected to the phase and amplitude correction circuit 150 via a path 11 forming a second input to a complex multiplier 162
Connected to 6c. In this configuration, path 116b
, 116d and 116e are provided with appropriate backward rotation.

FIG. 5 is a detailed circuit diagram of phase and amplitude correction circuit 150 (FIG. 4). The complex-valued output of equalizer 114 on path 116a is provided to complex multiplier 190, which also connects reference vector determination circuit 154 on path 178.
Receive the complex output of . Multiplier 190 uses the output from reference vector determination circuit 154 to perform phase correction. The complex output of multiplier 190 is routed to multiplier 1 via path 192.
94, and multiplier 194 receives the output of amplitude error correction decision circuit 152 via line 170. Therefore,
Multiplier 194 performs amplitude error correction using the output of amplitude error correction decision circuit 152.

FIG. 6 is a detailed circuit diagram of amplitude error correction decision circuit 152 (FIG. 4). Input line 120b is connected to multiplier 2 (10), which also receives coefficient value d1. Multiplier 2 (10
) is connected to adder 204 via line 202;
Its output is provided via line 206 to a multiplier 208 which also receives the coefficient value d2. The output of multiplier 208 is on line 21
0 is supplied to an adder 212 which is also supplied with the coefficient value d3. The output of adder 212 is connected to circuit 1 via line 214.
52 output line 170 and feedback line 21
6 to delay 218, whose output is connected to line 220
is connected to the input of adder 204 via.

The operation of amplitude error correction circuit 152 is similar to that of a leaky integrator. Circuit 152 quickly compensates for the amplitude error and slowly adapts by leaking towards the target value of 0.5. The gain control of modem receiver 80 is derived from three separate parts. The first part is performed by the key control circuit 104 (FIG. 3). The second part is performed by the amplitude correction described in FIG. The third small part is equalizer 11
4. The following coefficient values are used in circuit 152 (FIG. 6).

d+=o, o150 d2=0.9998 d3=o, oool The target value of the output of the amplitude error correction determination circuit 152 is 0.5
It is. Circuit 152 has internal feedback through delay element 218 which also has a target value of 0.5. circuit 15
2 rapidly adapts to its output to compensate for amplitude errors such as small sudden changes in telephone line attenuation. Circuit 152 then slowly adjusts due to the leakage and slowly returns to the 0.5 target value while dyne control circuit 104 (FIG. 3) adjusts slowly due to the leakage, while dyne control circuit 104 (FIG. 3) changes after the aforementioned slight rapid decay change in the telephone line. Slowly adjust to new gains for level normalization.

FIG. 7 is a detailed circuit diagram of the reference vector determination circuit 154 (FIG. 3).
is connected to multipliers 230 and 232, which are supplied with . The output of multiplier 232 is connected to adder 234 which has an output connected to adder 236 and delay 238. delay 23
The output of 8 is connected to the input of a multiplier 240 to which coefficient a2 is input and whose output is connected to the input of adder 234. The output of multiplier 230 is connected to the input of adder 236.

Components 232, 234, 238, 240 act as a leaky integrator 242 for averaging wood error feedback, and multiplier 230 acts as a proportional wood error feedback. The output of adder 236 is output to multiplier 246.
, an adder 248 and a delay 250. The output of the adder 248 is connected to a complex multiplier 252 which receives input from a vector generator 174 (FIG. 4) via a bus 176 and a reference vector determination circuit 154 (FIG. 4).
provides compensation for phase jitter present at the output of the

8A and 8B show the phase jitter compensation determining circuit 156 (fourth
FIG. Input line 120d is connected to multiplier 260 which receives coefficient value f1 and whose outputs are connected to multipliers 262 and 264 which each receive coefficient value err02. Multiplier 260°262.264 generates the gain adaptation value. The output of the multiplier 264 is connected to the subtraction input of the multiplier 266, whose output is connected to the 16 delay chain 268.
-1 to 268-16 first delay 268-1. The sixteen delay chains 268-1 through 268-16 consist of tapped delay lines 269 having tap nodes 270-1 through 270-16 connected to multipliers 272-1 through 272-16, respectively. Multipliers 272-1 to 272-
16 are respective leaky integrator circuits 274-1 to 274 which provide adaptive weighting factors in the form of coefficient values thereto;
Receives input from -16. Alternatively, the number of delay and leakage integration circuits can be varied.

The outputs of multipliers 272-1 through 272-16 are connected to an adder 276 whose output is connected to the input of a multiplier 278 that receives coefficient value f2 (Figures 8A, 8B). The output of multiplier 278 forms a phase error prediction signal provided on output line 172. The output of multiplier 278 is connected to multiplier 28 which receives coefficient value e3 via feedback line 280.
2 (FIG. 8A). The output of multiplier 282 is connected to the input of adder 266. Multiplier 282
The output of corresponds to the phase jitter forecast after gain adaptation,
The output of adder 266 corresponds to the actual phase error including noise.

The output of multiplier 262 is output from nodes 270-1 to 270-16.
Multipliers 284-1 to 284-1 with second inputs connected to
284-16. Multiplier 284
The outputs of −1 to 284-16 are each output from the leaky integration circuit 274.
-1 to 274-16, and integral circuits 274-1 to 274-16.
274-16 are adders 286-1 to 286-16 respectively
, delays 288-1 to 288-16 and multiplier 290-1
~290-16. Multipliers 290-1 to 290-1
6 receives the common coefficient value e4 that constitutes the leakage factor.

From these configurations, the outputs of delays 268-1 through 268-16 are correlated with the output of multiplier 262, and the correlation is accomplished by multiplication and integration.

Line 136 is leaky integrator 27. '4;-1~274-
16 delays 288-1 to 288-16, and the delay values obtained during the initial training can be stored in the receiver Arameta storage unit) 130 (FIG. 3) and used at the start of later training. When these are delayed they are restored again. At the start of later training, delay 26
8-1 to 268-16 are cleared in response to the signal reset on line i03.

During later training, leaky integrators 274-1 to 274
-16 provides a weighting factor that is initially set and later updated periodically. This is the phase error signal of line ]20d (factor fl+el in multipliers 260 and 262).
) and delays 268-1 to 268
This is done by multiplying the actual phase error by the noise estimate, shifted through -16. leaky integrator 274-1
~274-16 act as accumulators that store and update the final weighting factors of multipliers 272-1 through 272-16.

Delays 268-1 to 268-1.6 (delay line 269) contain continuous estimates of the actual phase pool. Adder 276 (Figure 8B) combines the outputs of multipliers 272-1 through 272-16 to provide a weighted sum output.

Automatic phase control (
The values of the various r-in factor coefficients mentioned above supplied during operation (APC) are as shown in Table 3 below.

The APC operation according to Table 3 starts at a predetermined time during the segment SC2 of Table 1 for early training (e.g., 5 (10) symbol periods after the start of the early training sequence), and for the late training sequence. starts at the beginning of its segment 2 (table 2). Moreover, the values of el+82 and e3 change during these APC periods, whereas e4 +ft
The values of +f2 +a2+a1 and b are fixed during the period.

The circuits 298A, 298B, and 298C that generate the values el+82+83 that change according to Table 3 are the 9th A to 90th circuits.
It is shown in the figure. Circuit 298A of FIG. 9A has a delay of 3 (
10) Contains A (initially set to values el, i).

The output of delay 3(10)A is connected to a multiplier 302A that receives the values el, d as inputs. The output of multiplier 302A is connected to the input of adder 304A, which also receives coefficient value eHO. Age-304A output has a delay of 3 (10) A
generates an output signal representing the coefficient 81 which is fed back to form the input of . According to this configuration, the value of el changes from its initial value el+1 to its final value e1,0.

The value of el,d is related to the speed at which eI converges to el,O. The values of el + 1; el + d; e1+0 are shown in Table 3. Coefficient 62+ shown in Figures 9B and 9C
The circuit generating 63 is the same as that of FIG. 9A, and each component is numbered the same and has the letter B.

C is attached. Suitable input values for generating coefficients 82+83 are shown in Figures 9B and 9C.

The vector generation circuit 174 (FIG. 3) in FIG.
2 is a detailed diagram illustrating receiving a real input representing a phase error prediction signal of 2 and generating a complex-valued output vector on path 176. FIG. The vector generation circuit includes adders 310 and 312 and multipliers 314 and 31 connected as shown in FIG.
6, 318, and 320. Adder 310 and multipliers 314, 316 are supplied with coefficients cO+c2rC3 of the following values:

co=1. O c2 = 0.497401 c3 = 0.166147 These values can be obtained from the following known approximate expressions.

cos x = 1-0.497401 x2sin
x = x-0, X corresponding to a phase knock level of 166147x340 degrees or less is 10, 35 (x (0,
35, which can give very accurate approximations.

FIG. 11 is a detailed diagram of the decision circuit 122 (FIG. 3).

Input path 120a carrying complex-valued input signals (p, q)
is connected to slicer 330.

Slicer 330 provides an output (A, A) on path 332 for each folded complex-valued input (p, q), whose output is the input vector point from the set of signal vector points of the recent QAM signal constellation. Corresponding to the selected target vector point. The slicer also provides a data signal on line 124 corresponding to the data represented by the target vector point. Path 332 connects line 335 with an output (p
, q ) and a table lookup unit 334 which provides an output with a vector length of one.

Knock 332 is also connected to a table lookup unit 336 which provides a real output on line 338 corresponding to the inversion of the vector length.

Adder 340 contains the value of path 342 and the value of path 335 (p*
. The output of the complex multiplier 344 is the error signal ('Q) after phase rotation to locate the error along the real axis.
Corresponds to (p, q). The imaginary part of the multiplier output corresponds to the wood grain error and is provided on line 346. The real part is provided on line 348. Lines 346 and 348 are line 120c.

120b, respectively. Line 346 also represents the table.
It is also connected to the input of a multiplier 350 which has a second input connected to the output line 338 of the Runoquag unit 336 . The output of multiplier 350 provides a phase error signal on line 120d.

In operation, long initial training according to Table 1
Sequence is supplied. Initially, the contents of the delays 268-1 to 268-16 and 288-1 to 288-16 of the 1-phase knock compensation determining circuit 156 (FIG. 4) and the delay 238 (FIG. 7) of the reference vector determining circuit 154 are in the O state. be made into During initial training, the contents of these delays are synthesized to provide the best compensation. After initial training, the mask modem receiver 80 (FIG. 3) obtains the receiver parameters and equalization coefficients stored in the receiver meter storage unit 130. These main meters are connected to the delay 128 of the phase jitter compensation determining circuit 156.
8-1 through 288-16 and the contents of delays 238 of reference vector determination circuit 154, which are transmitted to storage unit 130 via bus line 136.

During late training, a short training sequence according to Table 2 is applied. After identification of the remote modem, the previously stored parameters and coefficients involved are delayed 288-1 through 288 in phase jitter compensation determination circuit 156.
-16 value and delay 23 of reference vector determination circuit 154
The storage unit 30 containing the value 8 is also read out. Therefore, the reference vector determining circuit 15 that performs frequency shift compensation
4 is immediately loaded with the appropriate value for delay 238.

Also, the phase jitter compensation determining circuit 156 immediately sets the delay 288
The appropriate values are loaded into the load factor pools from -1 to 288-16.

Delay line element 268-1 of delay line 269 (FIG. 8B)
Since the phase of the fluctuation of the phase jitter in H.268-16 is unknown and the actual phase cannot be estimated, it starts from 0. Phase jitter compensation decision circuit 156 can then be trained quickly during the predefined 48 symbols of segment 2 of the training sequence. It is necessary to perform frequency shift compensation with a suitable set of delays 238 in the reference vector determination circuit 154 and delays 288-1 through 28.
Start with a suitable set of 8-16 pots.

The values in the second column of Table 3 give the best set for the key values, including the change values eI, e2c5, among the 48 predefined symbols starting from the state with a suitable setting of the load factor during subsequent training. Since fast training is performed on the first column, an initial setting different from the initial setting of the values in the first column is given.

Although the present invention has been described above with respect to the multipoint modem structure shown in FIG. 1, it can also be applied to a half-collar type point-to-point or point-to-point structure.

FIG. 12 shows a local station DTE connected to local modem 372.
Such a point-to-point or point-to-point structure is shown including a unit 370. Local modem 372 is connected via a two-wire transmission line 374 to a remote modem 376 which is connected to a remote DTE unit 378. Communication via the two-wire transmission line 374 is in a half-open mode, with transmission occurring in either direction. Each modem 372, 376 corresponds to the receiver of FIG. 3, except that the receiver parameter storage unit 130 uses a reserved storage location for only a single remote modem instead of for multiple remote modems. including.

In this semi-disconnected point-to-point structure, during the first local-to-remote and first remote-to-local transmissions, a long training sequence as in Table 1 is sent, during which the delay 238 (FIG. 7) and the delay at each position are 288-1~2
Receiver parameters and coefficients including the contents of 88-16 are obtained and saved.

In summary, a modem receiver has been described in which correct and reliable adaptive phase training is achieved and phase sonota and frequency deviations are compensated for. In both multi-point and point-to-point systems, continuous transmission can start at random instants, so it is impossible for the phase jitter compensation decision circuit to start with all pre-obtained values and continue tracking. It is possible. The present invention allows for fast and reliable compensation of phase jitter and frequency deviations using very short training. Therefore, the high data transmission rate allows very short training sequences to be used.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a multipoint data modem communication system including a mask modem and multiple remote modems; FIG. 2 is a block diagram of a remote modem transmitter; and FIG. 3 is a block diagram of a mask modem receiver. Figure 4 is a detailed block diagram of the automatic phase control circuit shown in Figure 3. Figure 5 is a block diagram of the phase and amplitude correction circuit shown in Figure 4. Figure 6 is a detailed block diagram of the automatic phase control circuit shown in Figure 4. FIG. 7 is a block diagram of the reference vector determination circuit of FIG. 4; FIGS. 8A and 8B are block diagrams of the phase book compensation determination circuit of FIG. , 9A to 90 are block diagrams of the coefficient generation circuit used to generate the coefficients shown in FIG. 9, FIG. 10 is a block diagram of the vector generation circuit of FIG. 4, and FIG. FIG. 12 is a block diagram of a half-disconnected point-to-point data modem communication system. In the figure, 10...multipoint data modem communication system, 1
2...Mask modem, 14,16.18...Remote modem, 20...Master DTE, 22,24°26...Remote) DTE, 28,32,34.36...
...4-wire telephone transmission line, correction circuit, 116a...path, 190.1...adder 218°0...branch point, 150...amplitude 120a, 178. 192 4... Multiplier, 204,212 38.250... Delay. Application agent Isao Saito

Claims (15)

[Claims] (1) A phase jitter compensation means that includes a tapped delay line having a plurality of output taps and receives a phase error signal, and a corresponding plurality of weighting coefficient generation means that generates a weighting coefficient and supplies it to the plurality of output taps. loading means for forming a plurality of weighted tap signals by summing the weighted tap signals to provide a phase error prediction signal; and feedback for feeding back the error prediction signal to the input means of the tapped delay line. means for determining a reference signal for providing a reference signal in response to the phase error forecast signal; error correction means for modifying the phase swing signal in accordance with the reference signal; and generating the weighting factor during an initial modem training sequence. and storage means for storing a plurality of parameters generated from the means and restoring the stored parameters to the weighting factor generating means during a later modem training sequence. dynamic compensation system. (2) The phase fluctuation compensation system according to claim 1, wherein the load factor generating means includes respective integration circuits including respective delay units, and the parameters include contents of each of the delay units. (3) The phase fluctuation compensation system according to claim 1, wherein said integrating circuit includes respective first multipliers receiving a common first multiplication coefficient. (4) the phase error signal is provided to a second multiplier that receives a fixed second multiplier, and the second multiplier is connected to a third multiplier that receives a third variable multiplier; the third multiplier having an output connected to a respective one of the integrator circuits and an output connected to a respective fourth multiplier receiving a respective input from the plurality of output taps; 4. The phase fluctuation compensation system according to claim 3, having an output with a (5) the output of said second multiplier is connected to a fifth multiplier receiving a fourth variable multiplication coefficient, having an output connected to said input means of said tapped delay line, said phase error 5. A phase shifter according to claim 4, wherein the forecast signal is fed to a sixth multiplier receiving a fifth variable multiplier and having an output connected to said input means of said tapped delay line. dynamic compensation system. (6) The first, second, and third coefficient generating means are adapted to generate the third, fourth, and fifth multiplication coefficients, respectively, and the first, second, and third coefficient generating means are configured to generate the third, fourth, and fifth multiplication coefficients, respectively, and the initial modem training sequence and the late modem training sequence - The phase fluctuation compensation system according to claim 5, which changes during the sequence. (7) The position fluctuation signal is an equalized signal generated from the output of an equalizer connected to the error correction means, and the error correction means is a determining circuit that supplies the phase error signal from a first output. 7. A phase fluctuation compensation system as claimed in claim 6, having an output connected to an input of the means. 8. The phase swing compensation system of claim 7, wherein said determining circuit means has a second output connected to said reference signal determining means for providing a quadrature error signal. (9) The reference signal determining means is the second reference signal determining means of the determining circuit.
an integrator and a delay device having an input connected to an output of the modem, said storage means for storing a second parameter formed by a value generated from said delay device during said initial modem training sequence. A phase fluctuation compensation system according to claim 8. (10) The phase fluctuation compensation system according to claim 9, wherein the phase error prediction signal is supplied to vector generating means having an output line connected to the reference signal determining means. (11) The reference signal determining means receives the output of the integrating device as an input and is connected to a first input of a seventh multiplier having a second input connected to an input of the vector generating means. Claim 1 comprising a feedback loop having an output and an output for generating said reference signal.
The phase fluctuation compensation system described in item 0. (12) The determining circuit means is adapted to provide an in-phase error signal and has a third output connected to the amplitude determining means to provide an amplitude error correction signal to the error correcting means. 12. The phase fluctuation compensation system according to item 11. (13) said second and third outputs of said decision circuit means are connected to a composite value bus connected to said combination means together with said reference signal;
13. A phase swing compensation system as claimed in claim 12, further adapted to provide a feedback signal to a second bus line coupled to form a line for feeding said equalizer. (14) The phase fluctuation compensation system according to claim 13, wherein the combining means includes a composite value multiplier. (15) The decision circuit means includes first and second tables.
a slicer having an output connected to lookup means and said first table lookup means used to provide said inphase and quadrature error signals;
the second used to provide the phase error signal;
15. A phase fluctuation compensation system as claimed in claim 14, including table lookup means for.