JPH02106830U - - Google Patents

Info

Publication number
JPH02106830U
JPH02106830U JP1359689U JP1359689U JPH02106830U JP H02106830 U JPH02106830 U JP H02106830U JP 1359689 U JP1359689 U JP 1359689U JP 1359689 U JP1359689 U JP 1359689U JP H02106830 U JPH02106830 U JP H02106830U
Authority
JP
Japan
Prior art keywords
wafer
wafer carrier
receiver
light emitter
photoelectric switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1359689U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1359689U priority Critical patent/JPH02106830U/ja
Publication of JPH02106830U publication Critical patent/JPH02106830U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図1は本考案の一実施例を示すウエーハー
枚数計数装置の正面図、第1図2はその側面図、
第2図は演算器4に入力する光電スイツチ1の出
力波形図、第31〜3はウエーハー4を支持する
ウエーハーキヤリア5の溝の部分の拡大図、第3
図4,5はそれぞれ第3図3のラインe,dでの
、反対方向に傾いた隣りあつた2枚のウエーハー
間の位置関係を示す図、第4図1は発光器1aと
受光器1bにそれぞれ収束器8、スリツト板9が
取り付けられた状態を示す図、第4図2はスリツ
ト板9の平面図、第4図3は収束器8の平面図、
第4図4は発光器1aからの光が検出しようとし
ているウエーハー4の隣のウエーハー4で反射さ
れて受光器1bに入力する様子を示す図、第5図
1〜3、第6図1〜3は従来のウエーハー枚数計
数方法を示す図である。 1……光電スイツチ、1a……発光器、1b…
…受光器、1c……光軸、2……フレーム、3…
…演算器、4……ウエーハー、5……ウエーハー
キヤリア、5a……下部の開口、5b……溝、6
……アーム、7……光軸1cとキヤリア内壁の距
離、8……収束器、9……スリツト板、9a……
スリツト、a……ウエーハーキヤリア5上の点、
b……点aを含む部分、c〜e……ライン、f,
g……ガタ、h,i……スキマ。
FIG. 1 is a front view of a wafer counting device showing an embodiment of the present invention, FIG. 1 is a side view thereof,
2 is an output waveform diagram of the photoelectric switch 1 that is input to the arithmetic unit 4, 31 to 3 are enlarged views of the groove portion of the wafer carrier 5 that supports the wafer 4, and 3
4 and 5 are diagrams showing the positional relationship between two adjacent wafers tilted in opposite directions at lines e and d in FIG. 3, respectively, and FIG. FIG. 4 2 is a plan view of the slit plate 9, FIG. 4 3 is a plan view of the convergence device 8,
4 is a diagram showing how the light from the light emitter 1a is reflected by the wafer 4 next to the wafer 4 to be detected and input to the light receiver 1b; FIGS. 5 1-3; FIGS. 6 1- 3 is a diagram showing a conventional wafer number counting method. 1...Photoelectric switch, 1a...Light emitter, 1b...
...Receiver, 1c...Optical axis, 2...Frame, 3...
...Arithmetic unit, 4...Wafer, 5...Wafer carrier, 5a...Lower opening, 5b...Groove, 6
...Arm, 7...Distance between optical axis 1c and carrier inner wall, 8...Concentrator, 9...Slit plate, 9a...
Slit, a... Point on wafer carrier 5,
b... part including point a, c to e... line, f,
g... Backlash, h, i... Gap.

Claims (1)

【実用新案登録請求の範囲】 光電スイツチと、 ウエーハーキヤリアの、搭載されたウエーハー
の正面方向から見たとき、光電スイツチの発光器
と受光器がウエーハーキヤリアの上方と下方に位
置し、光電スイツチの発光器と受光器を結ぶ光軸
がウエーハーキヤリアに搭載されているウエーハ
ーと交差し、かつ該光軸がウエーハーキヤリアの
下部の開口を通過するように発光器と受光器を保
持するフレームと、 ウエーハーキヤリアまたはフレームを、ウエー
ハーキヤリアのウエーハー搭載方向に移動させる
機構と、 光電スイツチの発光器に通電するとともに、受
光器からの、ウエーハーによつて遮光されて生じ
た信号を計数してウエーハーキヤリアに搭載され
ているウエーハーの枚数を計数する演算器とを有
するウエーハー枚数計数装置。
[Scope of Claim for Utility Model Registration] When the photoelectric switch and the wafer carrier are viewed from the front direction of the mounted wafer, the light emitter and receiver of the photoelectric switch are located above and below the wafer carrier; Hold the light emitter and receiver so that the optical axis connecting the light emitter and receiver of the switch intersects the wafer mounted on the wafer carrier, and the optical axis passes through the opening at the bottom of the wafer carrier. The frame, the wafer carrier or a mechanism for moving the frame in the wafer loading direction of the wafer carrier, and the light emitting device of the photoelectric switch are energized, and the signals from the photodetector that are blocked by the wafer are counted. A wafer number counting device having a computing unit for counting the number of wafers mounted on a wafer carrier.
JP1359689U 1989-02-09 1989-02-09 Pending JPH02106830U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1359689U JPH02106830U (en) 1989-02-09 1989-02-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1359689U JPH02106830U (en) 1989-02-09 1989-02-09

Publications (1)

Publication Number Publication Date
JPH02106830U true JPH02106830U (en) 1990-08-24

Family

ID=31224038

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1359689U Pending JPH02106830U (en) 1989-02-09 1989-02-09

Country Status (1)

Country Link
JP (1) JPH02106830U (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006156740A (en) * 2004-11-30 2006-06-15 Eibisu:Kk Inspection device for semiconductor wafer accommodating container
JP2018509751A (en) * 2015-01-22 2018-04-05 エスケー シルトロン カンパニー リミテッド Wafer transfer device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63188951A (en) * 1987-01-30 1988-08-04 Kokusai Electric Co Ltd Wafer taking-out and housing system for cassette

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63188951A (en) * 1987-01-30 1988-08-04 Kokusai Electric Co Ltd Wafer taking-out and housing system for cassette

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006156740A (en) * 2004-11-30 2006-06-15 Eibisu:Kk Inspection device for semiconductor wafer accommodating container
JP2018509751A (en) * 2015-01-22 2018-04-05 エスケー シルトロン カンパニー リミテッド Wafer transfer device

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