JPH02105461A - Solid-state image sensing device - Google Patents

Abstract

PURPOSE:To eliminate an irregularity between picture elements, to reduce a residual image by maintaining a picture-element size and to realize many picture elements by a method wherein diffusion regions whose type is identical to that of a gate diffusion region or a base diffusion region are formed inside an electrical isolation region surrounding a phototransistor or on this region and a reset switch control part used to conduct or break a part between these diffusion regions is formed between both diffusion regions. CONSTITUTION:A gate electrode 35, of a MOS transistor for reset switch use, formed so as to overlap a gate region 32 and a trench isolation region 34 is provided. Said gate electrode 35 is arranged on a gate insulating film 38 of the MOS transistor for reset switch use. A region 43, composed of a conductor, filled and formed inside a trench has a structure which is separated from an n<-> epitaxial layer 33 by an insulating film 42. The MOS transistor for reset switch use is constituted of the p<+> gate region 32, a p<+> type semiconductor region 40, the gate electrode 35 and an n-type channel doped region 36. Thereby, it is possible to prevent a picture-element size from being increased and to realize many picture elements.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an 11% solid state image device using an internally amplified phototransistor as a pixel.

[Conventional technology]

In recent years, solid-state imaging devices have been developed in the direction of increasing the number of pixels and even higher sensitivity in order to cope with applications such as high-definition televisions.
The development of D and MO3 type image sensors is reaching its limits due to problems such as random noise, amplifier noise, and transfer noise. In order to overcome this problem, research is underway to improve the sensitivity and S/N ratio by using an image sensor having an amplification function within the pixel. Static induction transistors are one of the solid-state imaging devices that use photoelectric conversion elements with internal amplification functions.
There is an image sensor using an SIT (transistor, hereinafter abbreviated as SIT).

Figure 5^ is a diagram showing the planar structure of the SIT two-dimensional image sensor, and Figure 5) is a diagram showing the cross-sectional structure along the line A-A'. The region 2 is p° arranged so as to surround the n0 source region 1.
Gate aM region, 3 is n-epitaxial region, 4 is n9
This is an isolation region for isolating pixels formed of a diffusion layer or an insulating film, and 5 is an 01 substrate constituting a drain region, and 6 is a unit pixel.

Then, S constituting the unit pixel 6 configured in this way
The transistor operation of the IT is such that an electron current that protrudes from the n' source region, passes through the n' epitaxial region 3, and flows into the n' drain region 5 is modulated by the p' game HI region 2 potential. SIT has various superior characteristics such as higher amplification factor and lower noise than ordinary bipolar transistors.

In addition, the operation of this SIT as a photosensor involves applying a bias more positive than the bias applied to the n' source region 1 at the time of reset to a gate electrode (not shown) coupled to the p' gate region 2 through a capacitance. The p゛ gate region 2 is forward biased with respect to the n° source region 1, and the holes are
゛The source boundary region 1 is swept out, and then a negative bias is applied to the gate electrode, and the p'' gate region 2 is reverse biased with respect to the n° source region 1.Then, the holes generated by light incidence are transferred to the p9 gate region 2. At this time, the photogenerated electrons flow into the n' source region 1 or the n' drain region 5. At the time of reading, the gate potential is biased more positively than the potential in the genuine bill accumulation state.

As a result, the amount of electron current flowing from the n' source region to the n' drain region is modulated by the p' gate potential change due to photogenerated charges. The light receiving operation principle of this SIT as a photosensor is to detect the amount of incident light based on changes in this current.

At this time, the problem is the operation of sweeping out holes from the p gate region to the n source region at the time of reset. In general, in vertical SITs, bipolar phototransistors, etc. in which the diffusion region is used as a hole storage region, the gate electrode is connected to the gate electrode via a capacitor so that the gate or base diffusion layer is forward biased with respect to the diffusion layer of another conductivity type. Alternatively, by applying a pulse voltage to the base diffusion layer, the generated light [ti accumulated in the gate or base diffusion layer is discharged to the diffusion layer of another conductivity type. At this time, the larger the amount of charge accumulated in the gate or base diffusion layer, the greater the forward bias between the gate or base diffusion layer and other diffusion layers, and a large amount of accumulated charge initially flows out to other diffusion layers. After a sufficiently long period of time, the gate or base diffusion layer and other diffusion layers reach the built-in voltage and the reset is completed, but when the voltage approaches the built-in voltage, the forward bias becomes smaller and the amount of discharge of accumulated charges becomes smaller.

IH in normal TV mode is about 60 μsec, and in this time the reset operation is not completed in the above phototransistor, and accumulated charges remain in the gate or base diffusion layer, which ultimately causes the solid-state imaging device to fail. As can be seen, the phenomenon of afterimages is one of the problems in solid-state imaging devices, and various proposals have been made in the past regarding the removal of this afterimage. For example, JP-A-60-
No. 232788 discloses means for improving pluming, image retention, and imaging as shown in FIGS. However, it is equivalent to a bipolar phototransistor or the like in that it has a photogenerated charge accumulation/diffusion region for signal modulation.

11-1.11-2.・・・・・・
11-Sho n is a pixel arranged in a matrix,
Reference numeral 12 denotes an optical signal amplification SIT constituting each pixel, and its gate 13 is connected to a gate selection line 16- through a capacitor 14.
1°...Connected to 16-m. Further, a PMOS reset transistor 15 is connected to the gate 13 to ensure a reset operation. The reset transistor 15 is connected to a line 24 to which a reset voltage or an overflow voltage is applied, and to a gate selection line 23 connected to the gate electrode of the reset transistor 15 during charge accumulation or resetting of the 5IT12. Appropriate selection of the applied voltages and the voltages on line 24 ensure overflow and reset operations. Furthermore, the 6th
In the figure ^, 18-1...1B-n are source lines, 19-1. ...19-n is a source line selection switch, 17 is a vertical scanning circuit, 22 is a horizontal scanning circuit, and 20 is an output line.

Figure 6 (C) is a diagram showing the planar structure of a pixel.
) is a cross-sectional view taken along the line A-A', and in the figure, 25 is a p gate diffusion layer, 26 is an n9 source diffusion layer, 27 is a drain diffusion layer of the reset transistor 15, and 28 is a The reset transistor gate electrode 29 is an isolation region.

In this improvement example, a reset transistor is placed inside the pixel to ensure the reset operation of the SIT light-receiving element, and furthermore, when the reset transistor is formed inside the pixel, the pixel size increases and it is difficult to increase the number of pixels. In order to avoid this drawback, one reset transistor is arranged for four pixels.

(Problems to be Solved by the Invention) As described above, by forming one reset transistor for every four pixels to ensure the reset operation of the SIT light-receiving element and making them shared, the pixel size can be reduced. Although it is possible to prevent the increase in pixels and increase the number of pixels, due to variations in alignment in the photolithography process, etc., the distance between the gate diffusion layer of the four SIT photodetectors and the drain diffusion layer of the reset transistor may vary. This has the disadvantage that the reset and overflow efficiencies vary among the four pixels.

The present invention has been made to solve the above-mentioned problems in solid-state imaging devices that use conventional internally amplified phototransistors as light receiving elements, and there is no variation between pixels.
Another object of the present invention is to provide a solid-state imaging device that has few afterimages while maintaining the pixel size and can have a large number of pixels.

[Means and operations for solving the problems] In order to solve the above problems, the present invention provides a solid-state imaging device comprising an internally amplified phototransistor having a gate or base diffusion region for accumulating photogenerated charges. A reset switch control unit that forms a diffusion region of the same type as the gate or base diffusion region in or on the electrical isolation region surrounding the transistor, and connects or disconnects the rediffusion region between these diffusion regions. It forms the

By configuring it in this way, the gate or base diffusion region and the portion II! Since a reset switch transistor is formed by the diffusion region formed in or on the 61 area and the reset switch control section formed between the re-diffusion region, the pixel size can be reduced by providing the reset switch transistor. The increase in the number of pixels is prevented, and it is possible to increase the number of pixels. Further, although a part of the pixel-like aperture is blocked by the reset switch control section, the area of the control section is sufficiently small compared to the pixel area, so a reduction in the aperture ratio does not pose a problem.

Further, since the reset transistor formed with the above configuration is formed for each pixel, the occurrence of variations in characteristics between each pixel is reduced.

〔Example〕

Examples will be described below. FIGS. 1(8) to (C1) are diagrams showing a first embodiment of the solid-state imaging device according to the present invention. In this embodiment, a reset switch transistor is formed using a trench isolation region. FIG. 1 is a plan view of this embodiment, in which 31 is an n"sIT source region, 32 is a p"sIT gate region,
33 is an n-epitaxial layer, 34 is a trench isolation region, and the region surrounded by dotted lines constitutes a unit pixel, which is the same as in the conventional example. 35 is the gate electrode of the reset switch MO3) transistor formed to overlap the gate region 32 and the trench isolation region 34, and 36 is the n of the reset switch MO3) transistor.
type channel doped region, the surface concentration is l×1QI4~
1. x 1Qlffc, -ff degree tonatail.

1) is a sectional view taken along line AA' in FIG. 1, and 37 is a substrate for n'sIT drain.

In Fig. 1 tB), a reset switch MO3) transistor is formed in the circled area, and an enlarged view of that part is shown in Fig. 1 (C1). In Fig. 1 C+, 38 is a reset switch. 40 is a selectively buried p-type semiconductor region, 41 is a trench, and 42 is an insulating film formed on the inner surface of the trench. The film 43 is a region made of a conductor buried in the trench, and the n-epitaxial layer 33 is the insulating film 4.
It has a structure separated by 2. And p° game HP
Area 32. P'' type semiconductor region 40, gate electrode 35, n type channel doped region 36 and MO3 for reset switch.
) consists of transistors.

Next, a photoelectric conversion operation in the solid-state imaging device configured as described above will be explained. First, when reading the signal, p
''The gate potential of the gate region 32 is raised higher than during storage,
Make SIT conductive. At this time, the potential applied to the gate electrode 35 of the reset switch MOS transistor is set to a potential at which the reset switch MO3) transistor becomes non-conductive.

After reading out the signal, the pixel SIT is reset to a new state in which photocharge accumulation is possible. The pixel SIT is normally reset by increasing the potential of the gate region 32, but in the present invention, the potential applied to the gate electrode 35 of the reset switch MOS transistor is changed so that the MO3) transistor is turned on. Set it so that it is done.

At this time, the p gate region 32 of S[T becomes the potential of the conductor region 43 in the trench (reset potential). In addition, at this time, the time required for reset is MO3 for the reset switch.
) The sum of the time for the transistor to transition from OFF to ON and the time for the gate region 32 to be charged to the reset potential is approximately several nanoseconds, and can be reset at a sufficiently high speed.

During optical signal accumulation, the gate region 32 is maintained in a reverse bias state with respect to the n' source SN region 31, as in normal SIT operation. At this time, the gate potential of the MO5 transistor for the reset switch is set to a potential that discharges the excess genuine bills accumulated in the gate HI region 32 to the conductor region 43 of the separation region 34. According to
The pixel structure of this example can also provide excellent blooming resistance without increasing the pixel size.

In the above embodiment, the conductor region 43 in the trench is
If the p-type semiconductor region 40 has a sufficiently low resistance, it may be an insulator, and the insulating film 42 in the trench is free from the stress caused by this insulating film 42 and the conductive region 43 from n-
The optimum thickness is set in consideration of the potential exerted on the epitaxial layer 33, etc.

The unique effect of this embodiment is that the conductor region 43 buried in the trench 41 is not limited to silicon;
It is possible to use a substance having a resistivity lower than that of silicon, such as a high melting point metal, and therefore, when such a substance is used, it is possible to apply a reset potential more quickly and stably. In addition, the trench isolation method has been highly developed in the memory field, and has the advantage of being able to use a process that is compatible with this technology.

To Figure 2 ~ (C1 is a diagram showing the second embodiment of the present invention,
This embodiment also uses the trench itI eI region to form a reset switch transistor. Figure 2 is a plan view of this embodiment, with 51
is n″SITSIT source region p0SIT gate region,
53 is an n-epitaxial layer, 54 is a trench region #, and the point that the region surrounded by the dotted line constitutes a unit pixel is the same as in the conventional example. 2nd issue) is A- in Figure 2, 4.
In the cross-sectional view taken along line A', 55 denotes an n''sIT drain substrate.

The reset switch MO3) transistor is formed in the area surrounded by a circle in the second issue), and an enlarged view of that part is shown in Figure 2 (C1). are two trenches arranged apart from each other in the trench isolation region 54, and 57 is an insulating film formed on the inner surface of the trench, and the insulating film 57 functions as a gate insulating film of a MOS transistor for a reset switch. Therefore, it is formed in contact with the p-gate insulating film 52. Reference numeral 58 is a region made of a conductor formed in the trench, and is a recess.

MO3I-transistor gate 111j for switching. Reference numeral 59 denotes a drain layer of a reset switch MOS transistor formed in contact with the two trenches 56a and 56b, and is formed of the same type of impurity diffusion layer as the p1 gate 6N region 52. 60 is an ion-implanted diffusion layer for adjusting the dark voltage of the reset switch MOS transistor.

The operation of the solid-state imaging device configured as described above is similar to the first embodiment, in which holes unnecessary during readout are transferred from the gate region 52 to the drain layer 59 of the reset switch MOS transistor during the photocharge accumulation period. overflow through the transistor, and at the time of reset, the gate region 5
Resetting is performed by making the potentials of the drain layer 59 and the drain layer 59 the same.

A unique effect of this embodiment is that the gate electrode of the MO3) transistor for the reset switch is formed in two adjacent trenches, and the drain layer formed between the two adjacent trenches is used for the reset switch of two adjacent pixels. M.O.
3) Since it is shared by the transistor, the aperture area within the negative layer pixel can be increased.

FIG. 3^, cB) is a diagram showing a third embodiment of the present invention,
In this embodiment, a reset switch MOS transistor is formed using a diffusion layer isolation region. Figure 3 is a plan view of this embodiment, and 61 is n''
SITSIT source region pSIT gate region, 63 is an n-epitaxial layer, 64 is a diffusion layer isolation region,
The point that the area surrounded by the dotted line constitutes a unit pixel is the same as in the conventional example.

65 is a gate electrode of a reset switch MOS transistor formed so as to overlap the gate region 62 and the diffusion layer isolation region 64.

FIG. 3 (B+ is a cross-sectional view taken along the line A-A' of the 31st prisoner, 66 is the n''sIT drain substrate substrate 7 is the gate insulating film of the reset switch MOS transistor, 68
is the gate region 62 formed in the diffusion layer isolation region 64.
This is the drain layer of the same type of MOS transistor for the centrifugal switch. Also, 69 is M for the reset switch.
This is an ion implantation diffusion layer for adjusting the threshold voltage of the OS transistor, and the gate region 62. Drain layer 68. Gate electrode 65. MOS for reset switch by diffusion layer 69 etc.
It constitutes a transistor.

The operation of the solid-state imaging device configured in this way is similar to that of the first embodiment. During the photocharge accumulation period, an unnecessary genuine tag is transferred from the gate region 62 to the diffused drain layer 68 of the same type as the gate region 62. (2) Overflow is caused through the reset switch MO3) transistor, and at the time of reset, the potentials of the gate region 62 and the drain l16B are made the same, and the reset is performed.

A unique advantage of this embodiment is that it can be formed using only the well-proven diffusion method and that a solid-state imaging device with excellent stability can be obtained.

FIG. 4 shows a reset switch M according to a fourth embodiment of the present invention.
FIG. 3 is a cross-sectional view showing the configuration of an OS transistor portion. In this embodiment, like the third embodiment, a reset switch MOS transistor is formed using the M6M diffusion region, but the structure of the transistor is different from the third embodiment.

That is, as shown in FIG. 4, the difference from the third embodiment is as follows.
MO3 for reset switch) Drain layer 6 of transistor
8 is formed so as to partially protrude outside the diffusion layer separation region 64. By forming the drain layer 68 in this manner, the dark voltage (2) of the reset switch MO3 transistor can be accurately controlled by the ion implantation diffusion layer 69. The other operations are completely the same as those in the third embodiment, and will therefore be omitted.

In the first to fourth embodiments above, an SIT was used as the photoelectric conversion element, but solid-state imaging devices using other photoelectric conversion elements having a gate or base portion with a diffusion layer structure may also be used. It is equally applicable. Also, the formation position of the reset switch MOS transistor is shown in Figure 1 ^ and Figure 2 8.

The position is not limited to the one shown in FIG. 3, but can be changed to an appropriate position so as to increase the aperture ratio of the pixel.

Furthermore, if the bias is appropriately selected, the wiring for the gate electrode of the MOS transistor for the reset switch in each embodiment can be made common to the original gate electrode line for the pixel that is connected to the SIT gate region via a capacitor. It is possible.

Further, in each of the above embodiments, the voltage applied to the SIT gate region at the time of reset was set as the reset potential;
By combining this with the conventional method of capacitively resetting T, it is not necessarily necessary to set it to a reset potential; in short, it is sufficient to configure the SIT gate jiJt region to be charged to a constant potential.

〔Effect of the invention〕

As described above based on the embodiments, according to the present invention, a reset switch means is formed in each pixel for resetting the internal amplification type phototransistor that constitutes each pixel, so that there is no afterimage and even in high-speed readout. A good image can be obtained.

Further, since a part of the reset switch means is disposed within or above the separation region, the pixel size is almost the same as that of a configuration in which no reset switch means is provided, and therefore, it is possible to increase the number of pixels.

Further, since the reset switch means is formed for each pixel, the occurrence of variations in characteristics between each pixel is reduced.

Furthermore, blooming resistance can also be improved by configuring the reset switch means with a MOS transistor and appropriately selecting the gate potential.

[Brief explanation of the drawing]

FIG. 1^ is a plan view of the first embodiment of the solid-state imaging device according to the present invention, FIG. , FIG. 3 is a partially enlarged view of 81, and FIG. , FIG. 2(C) is a partially enlarged view of FIG. 2 (Bl), FIG. 3 is a plan view of the third embodiment of the present invention, and FIG.
FIG. 4 is a cross-sectional view of the main part of the fourth embodiment of the present invention, and FIG.
, fBl are a plan view and a cross-sectional view of a general SIT two-dimensional image sensor, FIG. 6 is a circuit configuration diagram of a conventional solid-state imaging device with improved afterimages, and FIG. 6 tB+ is a planar structural diagram of its pixel. , A-A' in Fig. 6 (C1 is Fig. 6 FB)
It is a sectional view along the line. In the figure, 31.51.61 is the n' SIT source 81 area, 32.52.62 is the p'' SIT source 81 area,
33.53°63 is n-epitaxial layer, 34.54
is for trench! 35.65 is a reset switch Mos transistor gate electrode, 36 is an n-type channel doped hI region, 40 is a p semiconductor region, 41.56a,
56b is a trench, 42 is an insulating film, 43 is a conductor region in the trench, 58 is a gate electrode, 59 is a drain region, 6
8 indicates a drain layer. Patent applicant: Olympus Optical Industry Co., Ltd. Figure 5 (B) Figure 3 Figure 4 Figure 6 (A) 2nd floor

Claims (1)

[Scope of Claims] 1. In a solid-state imaging device consisting of an internally amplified phototransistor having a gate or base diffusion region for accumulating photogenerated charges, in or on an electrical isolation region surrounding the phototransistor, the A solid-state imaging device characterized in that a diffusion region of the same type as a gate or base diffusion region is formed, and a reset switch control section is formed between these diffusion regions to conduct or cut off conduction between both diffusion regions. 2. Claim 1, wherein the electrical isolation region is comprised of a groove isolation portion formed by a trench method.
The solid-state imaging device described. 3. The solid-state imaging device according to claim 1, wherein the electrical isolation region is comprised of a diffusion layer of a type opposite to that of the gate or base diffusion region. 4. The solid-state imaging device according to claim 1, wherein the reset switch control section is comprised of a gate section of a MOS transistor.