JPH021019A - One-chip microcomputer - Google Patents

Abstract

PURPOSE:To realize the protection function with a simple circuit by providing a ROM read limiting circuit and permitting read of stored information in a ROM at the time of coincidence between a preliminarily stored key code and an inputted key code. CONSTITUTION:Plural first key codes which are preliminarily and arbitrarily determined and consist of binary patterns are stored in a ROM 9. A CPU has an instruction register and its instruction decoder has a specific instruction word, which limits read of the ROM, and is provided with the decoding function. A second key code consisting of a binary pattern is inputted to ports 2-5 from the external. Then, the CPU compares first and second key codes with each other by a comparing program, and read of stored information of the ROM 9 to the external is permitted only when they coincide with each other. Thus, since the third person who does not know any key code cannot read contents of the ROM 9 though performing the operation, the softwared protection function is realized with the simple circuit using the performance of the CPU as it is.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a one-chip microcomputer that includes a built-in program ROM (IJ-only memory).

In a 1-chip microcomputer, the contents of the built-in program ROM can be read externally for purposes such as testing. (competitive relationship with ROM) can read the contents of the program using the external read function of the ROM, and the software cannot be protected.

Conventionally, in order to protect the above-mentioned software, a fuse means is used, and by blowing the fuse means, the program RO from the outside is prevented.
A method (Japanese Unexamined Patent Publication No. Sho 56-14354) that prohibits reading of M is publicly available.

However, the above method has the following drawbacks.

First, when the fuse blows out, flying metal pieces cause defects such as short circuits between circuit lines, resulting in a decrease in reliability.

Second, in addition to blowing fuses, it is necessary to take into account the dispersion of the blowing current and the dispersion of the allowable current of related circuit elements. The disadvantage is that a fusing device is required.

Thirdly, once the fuse is fused, the RO
Since external reading of M is prohibited, there are drawbacks such as making it impossible for the manufacturer to inspect the product upon receipt, or making it difficult to analyze the defects of products returned as defective.

The purpose of this invention is to enable specified persons such as manufacturers and manufacturing clients to read program ROMs from outside at any time.
An object of the present invention is to provide a one-chip microcomputer in which reading of a program ROM is prohibited to third parties other than the specified person.

Another purpose of this invention is to provide the above software protection function using a relatively simple circuit. : The purpose is to provide a realized one-chip microcombiner.

Further objects of the invention will become apparent from the following description and drawings.

Hereinafter, this invention will be explained in detail together with examples.

FIG. 1 shows a block diagram of an embodiment of a one-chip microcomputer to which the present invention is applied. In the same figure, each circuit block surrounded by dots is
It is formed on one semiconductor substrate using a known semiconductor manufacturing technique.

What is indicated by symbol 1 is a CPU (microprocessor), and its main constituent blocks are exemplarily shown as a representative. That is, the CPU 1 has an accumulator indicated by the symbol A, an index register indicated by the symbol X, a condition code register indicated by the symbol CC, a stack pointer indicated by the symbol SP, and symbols PCH and PCL. It is composed of a program counter shown, a CPU control shown by the symbol CPUCONT, an arithmetic logic unit shown by the symbol ALU, etc. Since the configurations of these CPUIs are well known, detailed explanation thereof will be omitted.

The symbols 2 to 5 are input and output ports, and the symbols 2 to 4 are the input and output ports.
A data direction register RA or RC is provided,
Used as an input/output port. Also, symbol 5 indicates an input-only board, symbol 6 indicates an oscillation circuit, and although it is not particularly limited, it is a high-precision circuit that uses an external crystal oscillator. Form a reference frequency signal. With this reference frequency signal, CP
The clock required by the UI is created. The reference frequency signal is also used as a reference time pulse of a timer indicated by symbol 7. Timer 7 above
is composed of a counter indicated by the symbol C0UNT, a grease scaler, and a controller indicated by the symbol C0NT.

What is indicated by the symbol 8 is a RAM (Random Access Memory), which is mainly used as a temporary data storage circuit.

The symbol 9 indicates a ROM (read only memory) in which programs for various information processing are written.

Each of the above circuit blocks consists of a CPU and a bus BU.
They are interconnected with S. This bus BUS includes a data bus and an address bus.

In this embodiment, the following circuit is provided in the CPUI in order to add the software protection. An embodiment of the ROMm output limiting circuit is not shown in FIG.

In the figure, the symbol 10 indicates the CPU
The instruction register, shown at 11, is its instruction decoder.

In this embodiment, a time-saving instruction word 5ETFLAG is added to limit the output of the ROM .pi.d, and accordingly, a decoding function thereof is added to the instruction decoder 1]. Above 6
1 decoder 1] specific instruction word 5ETFLA
G[The corresponding control signal is transmitted to the center power S of the flag FLAG, which is constituted by a flip-flop. The output signal Q is used as a gate control signal for AND gates G2 and G. Above flag FL
AG's reset human power R has ORGATE G,? :A, the reset control signal RE generated by the instruction decoder 11
S, a system reset signal input from an external reset terminal RES, and a power on clear signal PCL are transmitted.

What is not shown by symbol 12 is a three-value determination circuit, which determines whether the signal voltage from a specific external control terminal C1 is one of three values: 0 volts, 5 volts, or ]2 volts, and takes appropriate action. Set the operation mode signal to '1'.The three operation mode signals mentioned above are selected from operation modes that do not compete with each other. The output signal Q of the flag FLAG is inputted to an AND gate G2, and the output thereof is used as an internal &ROM start-up operation mode signal.

In addition, the internal bus check (
When performing the read) mode MOD4, the output signal Q of the flag FLAG is used as a limiting signal since this operating mode allows indirect reading of the internal gROM.

That is, the MOD4 signal is formed by an AND gate G3 that receives the output signal Q of the flag FLAG and a signal from the external terminal C7.

In addition to the circuit shown in Figure 2 above, the ROM 9K is provided with the following program and a key code that can be set arbitrarily. A flowchart diagram is shown.

In this example, an 8-bit (1-byte) CPU is used, and an 8-byte key code is used.

In step 5TPI, 8 is set in register RO as a loop parameter.

In step 5TP2, the start address of the key code table arbitrarily set in advance is set in the register R1.

In step 5TP3, the contents of register R], that is, the start address of the key code table, are transferred to accumulator AK.

In step 5TP4, the 1-byte key code written in the first address of the key code table is taken into the accumulator A.

In step 5TP5, the 1-byte key code is transferred to register R2.

In step 5TP6, register R1 is incremented (+2) and the address of the next key code is set.

In step 5TP7, the 1-byte key code input from the outside is taken into the accumulator A.

In step 5TP8, a comparison (exclusive OR) is performed between the external key code taken into the accumulator AIC and the internal key code from the ROM, which is taken into the register R2.

In step 5TP9, if any one of the exclusive ORs is 1'', that is, the key codes do not match, the execution of this program is terminated.

On the other hand, if the 1-byte key codes match, the process moves to the next step 5TPIO.

In step 5 TPIO, the register RO is decremented (-1), and if the content is not 0, the process moves to step 3. Therefore, step 5TP above
When 3 to 5 TPIO is repeated 8 times, in other words, when the 1-byte internal key code and the external key code match 8 times in a row, the process moves to step 5 TP11.

In step 5TPII, the flag F shown in FIG.
Set LAG.

Therefore, in the one-chip microcomputer of this embodiment, by executing the above program, after inputting the 64-bit key code accurately and setting the flag FLAG, the built-in R
OM's butt control Noh.

In this embodiment, a third party who does not know the above key code,
Even if we create a system that randomly generates key codes sequentially and scans them until they match the internal key code in order to continue printing i ROMs, there are 264 combinations of input key codes. , even if it takes 100M5 (microseconds) for one judgment, it will take an enormous amount of time, 2" x 100M5 = 5.12xlO"Hr (hours), so it is realistic to
Reading 7 is not possible. Also, if the above flag FL
Even if it is possible to set AGY, in this embodiment, the ROM cannot actually be read unless the external terminal is set to a high voltage of 12 volts. If only the manufacturer and the manufacturing client know about this terminal, the software can be protected more frequently.

Existence of the above terminal Even if the Yi champion had mentioned it, I don't know specifically which terminal it is, so if I randomly apply a high voltage of 12 volts to the external terminal, I can confirm that it has the above three-value judgment circuit. If a voltage as high as 12 volts is applied to a terminal that is not connected to the The number of bits itself can be easily set according to the request of the manufacturer, making it even more difficult for a third party who does not know the number of bits of the key code to read the ROM.

Furthermore, it is possible to select which input port to use among a plurality of input ports for inputting a key code from the outside, or to import key codes from different input ports in a specific order using the plurality of input ports 2 to 75. This can be done extremely easily by setting the program, thereby further strengthening the protection of the ROM program.On the other hand, the manufacturer and the manufacturing client can read the ROM at any time. Therefore, there is no problem with testing and failure analysis.

In addition, in this embodiment, many of the functions of the one-chip microcomputer can be used as is, and in order to protect the program described above, just by adding a simple circuit consisting of the flag FLAG and a few gates, it is possible to protect the program from third parties. Extremely strong program protection can be achieved.

This invention may be limited to the embodiments described above.

For example, reading of the ROM may be limited and canceled only by the output state of the flag FLAG, which is set when the key codes match.

Alternatively, an external ROM read control signal may be received as a trigger at the timing of setting the flag.

In addition, the above can be done by setting the flag with a certain command word.
Since this is to cancel the OM's inhibition of IT output, the one-chip microcomputer of the above embodiment is configured such that it cannot operate with external commands (programs).

The system configuration of the above l-chip microcomputer is as follows:
It can be modified in various ways.

[Brief explanation of the drawing]

FIG. 2 is a block diagram showing an embodiment of the l-step microcomputer to which the present invention is applied; FIG. 2 is a circuit diagram showing an embodiment of the main part of the invention; FIG. FIG. 2 is a flowchart diagram illustrating an example. ]...CPU, 2 to 5...Boat, 6...Oscillation circuit, 7...Timer, 8...RAM, 9...
ROM, ]0...instruction register, ]]...instruction decoder, 12...three-value determination circuit. Figure Figure

Claims (1)

[Claims] 1. In a one-chip microcomputer in which at least a CPU, a RAM, and a ROM are formed on one semiconductor substrate, a plurality of first key codes each consisting of a predetermined binary pattern are stored in the ROM. At the same time, the second key code and the first key code are sequentially determined by a comparison determination program that compares and determines a second key code consisting of a binary pattern input from the outside with the first key code. The one-chip micro is characterized in that the information stored in the ROM can be read out when all of the first key codes that have been compared and stored match the second key codes. Computer.