JPH0198285A - Semiconductor light emitting element with monitor - Google Patents
Semiconductor light emitting element with monitorInfo
- Publication number
- JPH0198285A JPH0198285A JP62255706A JP25570687A JPH0198285A JP H0198285 A JPH0198285 A JP H0198285A JP 62255706 A JP62255706 A JP 62255706A JP 25570687 A JP25570687 A JP 25570687A JP H0198285 A JPH0198285 A JP H0198285A
- Authority
- JP
- Japan
- Prior art keywords
- chip carrier
- light emitting
- semiconductor light
- emitting element
- face
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 238000012544 monitoring process Methods 0.000 claims abstract description 6
- 239000012777 electrically insulating material Substances 0.000 claims description 3
- 229910003460 diamond Inorganic materials 0.000 abstract description 7
- 239000010432 diamond Substances 0.000 abstract description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052802 copper Inorganic materials 0.000 abstract description 3
- 239000010949 copper Substances 0.000 abstract description 3
- 239000000919 ceramic Substances 0.000 abstract description 2
- 230000000087 stabilizing effect Effects 0.000 abstract 1
- 239000010931 gold Substances 0.000 description 6
- 230000003287 optical effect Effects 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Landscapes
- Semiconductor Lasers (AREA)
- Photo Coupler, Interrupter, Optical-To-Optical Conversion Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、光通信、光情報処理、光応用計測など各種の
光応用システムで使用され為モニタ付半導体発光素子に
関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor light emitting device with a monitor used in various optical application systems such as optical communication, optical information processing, and optical application measurement.
（従来の技術）
光通信システムなどの光応用システムでは、半導体レー
ザなどの発光素子にフォトダイオードなどの受光素子を
組合せることによりモニタ機能を付加したモニタ付半導
体発光素子が使用されている。(Prior Art) In optical application systems such as optical communication systems, a semiconductor light emitting device with a monitor is used in which a monitoring function is added by combining a light receiving device such as a photodiode with a light emitting device such as a semiconductor laser.
従来、上述のモニタ付半導体発光素子のうちフラット型
のものでは、発光素子を搭載したチップキャリアと受光
素子を搭載したチップキャリアとを共通の基板上に接近
させて搭載することによって画素子の組合せを実現して
いる。Conventionally, among the above-mentioned semiconductor light-emitting devices with a monitor, flat type semiconductor light-emitting devices have a combination of pixel elements by mounting a chip carrier carrying a light-emitting element and a chip carrier carrying a light-receiving element close to each other on a common substrate. has been realized.
（発明が解決しようとする問題点）
上記フラット型のモニタ付半導体発光素子では、発光素
子を搭載したチップキャリアと受光素子を搭載したチッ
プキャリアとを共通の基板上に接近させて搭載すること
によって画素子の組合せを実現しているので、組立に手
間がかかると共に最終的な構造も複雑で大型になるとい
う問題がある。(Problems to be Solved by the Invention) In the above flat type semiconductor light emitting device with a monitor, a chip carrier on which a light emitting device is mounted and a chip carrier on which a light receiving device is mounted are mounted close to each other on a common substrate. Since the combination of pixel elements is realized, there is a problem that assembly is time-consuming and the final structure is complicated and large.
また、画素子への配線がそれぞれのチップキャリア上に
形成されるため、配線構造が複雑になって配線の自動化
が困難になるという問題もある。Furthermore, since the wiring to the pixel elements is formed on each chip carrier, there is also the problem that the wiring structure becomes complicated and automation of the wiring becomes difficult.
（問題点を解決するための手段）
本発明のモニタ付半導体発光素子は、第１のチップキャ
リアと、この第１のチップキャリアの上面の前端部分に
装着される半導体発光素子と、左右の端面及び傾斜した
前端面によって前記半導体発光素子を左右及び後方の三
方から囲む凹部を形成しつつ上記第１のチップキャリア
の上面に装着される第２のチップキャリアと、この第２
のチップキャリアの上記傾斜した前端面上に装着され上
記半導体発光素子の後方出力光をモニタする半導体受光
素子とを備え、各チップキャリアを共通の基板を用いる
ことなく直接組合せて一体化することにより組立作業の
容易化と構造の簡易・小型化を実現するように構成され
ている。゛
また、本発明の一実施例によれば、上記第２のチップキ
ャリアは電気絶縁性の素材で形成されると共にその上面
に半導体発光素子と半導体受光素子に接続される配線パ
ターンが形成されることにより、配線構造を簡略化し配
線の自動化を容易にするように構成されている。(Means for Solving the Problems) A semiconductor light emitting device with a monitor according to the present invention includes a first chip carrier, a semiconductor light emitting device mounted on the front end portion of the upper surface of the first chip carrier, and left and right end surfaces. and a second chip carrier that is attached to the upper surface of the first chip carrier while forming a recess that surrounds the semiconductor light emitting device from three sides, left, right, and rear with an inclined front end surface;
and a semiconductor light receiving element mounted on the inclined front end surface of the chip carrier to monitor the rear output light of the semiconductor light emitting element, and by directly combining and integrating each chip carrier without using a common substrate. It is configured to facilitate assembly work and to simplify and downsize the structure. According to an embodiment of the present invention, the second chip carrier is formed of an electrically insulating material, and a wiring pattern connected to the semiconductor light emitting element and the semiconductor light receiving element is formed on the upper surface of the second chip carrier. This simplifies the wiring structure and facilitates wiring automation.
以下、本発明の作用を実施例と共に詳細に説明する。Hereinafter, the operation of the present invention will be explained in detail together with examples.
（実施例）
第１図は本発明の一実施例に係わるモニタ付半導体発光
素子の構成を示す斜視図、第２図はその分解斜視図であ
る。(Embodiment) FIG. 1 is a perspective view showing the configuration of a semiconductor light emitting device with a monitor according to an embodiment of the present invention, and FIG. 2 is an exploded perspective view thereof.
第１のチップキャリア１１は、銅製の平板で形成される
と共にその平坦な上面１１ａの前端部分には平坦な上面
を有する台部１１ｂが形成されている。この台部１１ｂ
の平坦な上面に放熱性の良好なダイヤモンド・ヒートシ
ンク１２を介在させつつフラット型の半４体レーザ１が
装着される。The first chip carrier 11 is formed of a flat plate made of copper, and has a flat top surface 11a with a base portion 11b having a flat top surface formed at the front end portion of the first chip carrier 11. This base part 11b
A flat half-quadruple laser 1 is mounted on the flat upper surface of the laser with a diamond heat sink 12 having good heat dissipation interposed therebetween.
ダイヤモンド・ヒートシンク１２の厚みは３００μｍ程
度であり、その底面にはチタニュウム（ＴＩ）、白金（
Ｐｔ）、金（Ａｕ）の蒸着膜がそれぞれ１５００人、１
０００人、２０００人程度０厚みで積層されている。ま
た、ダイヤモンド・ヒートシンク１２の上面と側面には
チタニュウムと白金の蒸着膜がそれぞれ１５００人と１
０００人の厚みで形成されて底面と上面間が電気的に導
通せしめられると共に、上面にはさらに厚み４μｍ程度
の金錫（ＡｕＳｎ）の蒸着膜が形成される。The thickness of the diamond heat sink 12 is approximately 300 μm, and the bottom surface is coated with titanium (TI) and platinum (
1,500 people and 1,500 people for vapor deposited films of Pt) and gold (Au), respectively.
000 or 2000 layers are laminated with zero thickness. In addition, titanium and platinum vapor deposited films are deposited on the top and side surfaces of the diamond heat sink 12, respectively.
000 mm thick to provide electrical continuity between the bottom surface and the top surface, and a gold-tin (AuSn) evaporated film with a thickness of about 4 μm is further formed on the top surface.
ダイヤモンド・ヒートシンク１２上に搭載される半導体
レーザ１の上下の電極面には金の蒸着膜が形成され、こ
の半導体レーザｌの下面、ダイヤモンド・ヒートシンク
１２の上下の面及び銅製の台部１１ｂの上面は上述の蒸
着膜によって相互に熱融着される。A gold vapor deposition film is formed on the upper and lower electrode surfaces of the semiconductor laser 1 mounted on the diamond heat sink 12, and the lower surface of the semiconductor laser 1, the upper and lower surfaces of the diamond heat sink 12, and the upper surface of the copper base 11b. are thermally fused together by the above-mentioned vapor deposited film.
第２のチップキャリア２１は、セラミックなどの電気絶
縁性の平板で構成されると共に、第１のチップキャリア
１１上への装着時に半導体レーザｌを左右と後方の三方
から囲むように左右の端面と傾斜した前端面２１ｂによ
って凹部２１Ｃが形成されている。第２のチップキャリ
アの上面２１ａには、フォトダイオードへの配線パター
ン２２ａ、２２ｂと、半導体レーザ１への配線パターン
２３ａ、２３ｂが金メツキなどによって形成されている
。また、第２のチップキャリア２１の底面には、金の蒸
着膜が形成されている。The second chip carrier 21 is composed of an electrically insulating flat plate made of ceramic or the like, and has left and right end faces so as to surround the semiconductor laser l from three sides, left, right and rear, when mounted on the first chip carrier 11. A recess 21C is formed by the inclined front end surface 21b. On the upper surface 21a of the second chip carrier, wiring patterns 22a and 22b to the photodiodes and wiring patterns 23a and 23b to the semiconductor laser 1 are formed by gold plating or the like. Furthermore, a gold vapor deposition film is formed on the bottom surface of the second chip carrier 21.
配線パターン２２ｂは、第２のチップキャリアの上面２
１ａからその前端部分の凹部２１を画成する傾斜した前
端面２１ｂ上に延長され、この延長部分にフォトダイオ
ード２がその一方の電極を介して装着される。フォトダ
イオード２の他方の電極と配線パターン２２ａとはボン
ディングワイヤ２２ｃを介して接続される。また、配線
パターン２３ｂは、第２のチップキャリア上面２１ａか
ら凹部２１ｃを画成する左方の端面上を通って底面まで
延長され、この底面に形成されている金の蒸着膜と電気
的に接続される。The wiring pattern 22b is the upper surface 2 of the second chip carrier.
It extends from 1a onto an inclined front end surface 21b defining a recess 21 in its front end portion, and a photodiode 2 is attached to this extended portion via one electrode thereof. The other electrode of the photodiode 2 and the wiring pattern 22a are connected via a bonding wire 22c. Further, the wiring pattern 23b extends from the second chip carrier upper surface 21a to the bottom surface, passing over the left end surface defining the recess 21c, and is electrically connected to the gold vapor deposited film formed on the bottom surface. be done.
フォトダイオード２が装着される前端面２１ｂの傾斜は
、半導体レーザ１の後方出力光がこれをモニタするため
のフォトダイオード２の表面で反射され、戻り光として
半導体レーザ１に帰還されてその動作を不安定にするの
を防止するためのものである。このように前端面２１ｂ
の傾斜によって戻り光の悪影響が防止されるので、フォ
トダイオード２を半導体レーザ■に必要なだけ接近させ
て配置することによりモニタ感度を十分に高めることが
できる。The slope of the front end surface 21b on which the photodiode 2 is mounted is such that the rear output light of the semiconductor laser 1 is reflected on the surface of the photodiode 2 for monitoring it, and is fed back to the semiconductor laser 1 as return light to control its operation. This is to prevent instability. In this way, the front end surface 21b
Since the adverse effect of the returned light is prevented by the inclination of , the monitor sensitivity can be sufficiently increased by arranging the photodiode 2 as close as necessary to the semiconductor laser (2).
上述した第１のチップキャリアｌｌ上への半導体レーザ
１の装着と、第２のチップキャリア２１上へのフォトダ
イオード２の装着は個別の作業として行われる。これら
の装着作業の終了後に、第２のチップキャリア２１がそ
の底面の蒸着膜による熱融着やはんだ付けによって第１
のチップキャリアの上面１１ａ上に結合される。このチ
ップキャリア相互の結合による一体化が終了すると、半
導体レーザ１の上部電極と配線パターン２３ａの間がボ
ンディングワイヤ２３ｃで接続され、組立が完成する。The aforementioned mounting of the semiconductor laser 1 onto the first chip carrier 11 and mounting of the photodiode 2 onto the second chip carrier 21 are performed as separate operations. After these mounting operations are completed, the second chip carrier 21 is attached to the first chip carrier 21 by heat fusion or soldering using a vapor-deposited film on the bottom surface of the second chip carrier 21.
is bonded onto the top surface 11a of the chip carrier. When the chip carriers are integrated by mutual bonding, the upper electrode of the semiconductor laser 1 and the wiring pattern 23a are connected by the bonding wire 23c, and the assembly is completed.
なお、第２のチップキャリア２１を構成する電気絶縁性
の平板の厚みは、その前端部分の側面２１ｂ上にフォト
ダイオード２の実装スペースを確保したり、このチップ
キャリア自体の強度を確保したりする必要上、あまり小
さくできない。本実施例では、上記電気絶縁性の平板の
厚みをを約２ｍｍにすると共に第１のチップキャリア１
１の上面１１ａに台部１１ｂを形成することにより、半
導体レーザ１とフォトダイオード２の高さを調整してい
る。The thickness of the electrically insulating flat plate constituting the second chip carrier 21 is determined to ensure a mounting space for the photodiode 2 on the side surface 21b of the front end portion and to ensure the strength of the chip carrier itself. Due to necessity, it cannot be made too small. In this embodiment, the thickness of the electrically insulating flat plate is approximately 2 mm, and the first chip carrier 1
The heights of the semiconductor laser 1 and the photodiode 2 are adjusted by forming a pedestal portion 11b on the upper surface 11a of the semiconductor laser 1 and the photodiode 2.
また、第２のチップキャリア２１の前端部分の傾斜した
側面２１ｂの横幅は約３ｍｍであり、フォトダイオード
２へのボンディングワイヤ２２ｃを前後方向に延在する
ことにより、ワイヤボンディングの作業を容易にしてい
る。Further, the width of the inclined side surface 21b of the front end portion of the second chip carrier 21 is approximately 3 mm, and by extending the bonding wire 22c to the photodiode 2 in the front and rear direction, wire bonding work is facilitated. There is.
以上、寸法や素材などに関し具体的な例を挙げて説明し
たが、これらは−例にすぎず本発明の技術的範囲を限定
するものではない。Although specific examples regarding dimensions, materials, etc. have been described above, these are merely examples and do not limit the technical scope of the present invention.
（発明の効果）
以上詳細に説明したように、本発明のモニタ付半導体発
光素子は、第１のチップキャリアの上面の前端部分に装
着される半導体発光素子と、この半導体発光素子を左右
及び後方の三方から囲む凹部を形成しつつ第１のチップ
キャリア上に装着される第２のチップキャリアと、この
第２のチップキャリアの′前端面上に装着されるモニタ
用半導体受光素子とを備える構成であるから、各チップ
キャリアを共通の基板を用いることなく直接組合せて一
体化できる。(Effects of the Invention) As described above in detail, the semiconductor light emitting device with a monitor of the present invention includes a semiconductor light emitting device mounted on the front end portion of the upper surface of the first chip carrier, and a semiconductor light emitting device mounted on the left and right and rearward portions of the first chip carrier. a second chip carrier mounted on the first chip carrier while forming a recess surrounding it from three sides; and a monitoring semiconductor light-receiving element mounted on the front end surface of the second chip carrier. Therefore, each chip carrier can be directly combined and integrated without using a common substrate.
この結果、工数の低減などに伴い組立作業が容易になり
、最終的な組立構造も簡易、小型になるという効果があ
る。As a result, the assembly work becomes easier due to a reduction in the number of man-hours, and the final assembly structure becomes simpler and smaller.
また、上記半導体受光素子が搭載される第２のチップキ
ャリアの前端面の傾斜により、半導体発光素子に対する
戻り光の悪影響を有効に防止される。Furthermore, the inclination of the front end surface of the second chip carrier on which the semiconductor light-receiving element is mounted effectively prevents the adverse effects of returning light on the semiconductor light-emitting element.
さらに、本発明の一実施例によれば、第２のチップキャ
リアが電気絶縁性の素材で形成されると共にその上面に
半導体発光素子と半導体受光素子に接続される配線パタ
ーンが形成される構成であるから、配線構造が簡易化さ
れ自動配線が容易になるという効果がある。Furthermore, according to an embodiment of the present invention, the second chip carrier is formed of an electrically insulating material, and a wiring pattern connected to the semiconductor light emitting element and the semiconductor light receiving element is formed on the upper surface of the second chip carrier. This has the effect of simplifying the wiring structure and facilitating automatic wiring.
また、上記配線パターンをマイクロストリップ線路など
で構成することにより、外部電気回路とのインピーダン
ス整合の好な信号線を実現できるという効果もある。Further, by configuring the wiring pattern with a microstrip line or the like, it is possible to realize a signal line with good impedance matching with an external electric circuit.
第１図と第２図は本発明の一実施例のモニタ付半導体発
光素子の構成を示す斜視図と分解斜視図である。
１・・・半導体レーザ、２・・・フォトダイオード、１
１・・・第１のチップキャリア、ｌｌｂ・・・第１のチ
ップキャリアの前端部分に形成された台部、１２・・・
ダイヤモンド・ヒートシンク、２１・・・第２のチップ
キャリア、２１ｂ・・・傾斜した前端面、２１Ｃ・・・
第２のチップキャリアの前端部分に形成される凹部、２
２ａ。
２２ｂ、２３ａ、２３ｂ−・−第２のチップキャリアの
上面に形成される配線パターン、２２ｃ。
２３ｃ・・・ボンディングワイヤ。1 and 2 are a perspective view and an exploded perspective view showing the structure of a semiconductor light emitting device with a monitor according to an embodiment of the present invention. 1... Semiconductor laser, 2... Photodiode, 1
DESCRIPTION OF SYMBOLS 1...First chip carrier, llb...Base portion formed at the front end portion of the first chip carrier, 12...
Diamond heat sink, 21... second chip carrier, 21b... inclined front end surface, 21C...
a recess formed in the front end portion of the second chip carrier;
2a. 22b, 23a, 23b--wiring pattern 22c formed on the upper surface of the second chip carrier. 23c...Bonding wire.
Claims (2)
る半導体発光素子と、 左右の端面及び傾斜した前端面によって前記半導体発光
素子を左右及び後方の三方から囲む凹部を形成しつつ前
記第１のチップキャリアの上面に装着される第２のチッ
プキャリアと、この第２のチップキャリアの前記傾斜し
た前端面上に装着され前記半導体発光素子の後方出力光
をモニタする半導体受光素子とを備えたことを特徴とす
るモニタ付半導体発光素子。(1) A first chip carrier, a semiconductor light emitting element mounted on the front end portion of the upper surface of the first chip carrier, and a semiconductor light emitting element mounted on the front end portion of the upper surface of the first chip carrier; a second chip carrier mounted on the upper surface of the first chip carrier while forming a surrounding recess; and a second chip carrier mounted on the inclined front end surface of the second chip carrier to emit rear output light of the semiconductor light emitting element. 1. A semiconductor light-emitting device with a monitor, comprising a semiconductor light-receiving device for monitoring.
で構成されると共にその上面に前記半導体発光素子及び
半導体受光素子に接続される配線パターンが形成された
ことを特徴とするモニタ付半導体発光素子。(2) A semiconductor with a monitor, wherein the second chip carrier is made of an electrically insulating material and has a wiring pattern connected to the semiconductor light emitting device and the semiconductor light receiving device formed on its upper surface. Light emitting element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62255706A JPH0198285A (en) | 1987-10-09 | 1987-10-09 | Semiconductor light emitting element with monitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62255706A JPH0198285A (en) | 1987-10-09 | 1987-10-09 | Semiconductor light emitting element with monitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0198285A true JPH0198285A (en) | 1989-04-17 |
Family
ID=17282504
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62255706A Pending JPH0198285A (en) | 1987-10-09 | 1987-10-09 | Semiconductor light emitting element with monitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0198285A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0579440A2 (en) * | 1992-07-15 | 1994-01-19 | AT&T Corp. | Method of making an assembly including patterned film submount with self-aligned electronic device |
| EP0571907A3 (en) * | 1992-05-29 | 1994-02-16 | Eastman Kodak Co | |
| KR100515765B1 (en) * | 2002-11-18 | 2005-09-23 | 김학연 | A per forator for a ditch |
-
1987
- 1987-10-09 JP JP62255706A patent/JPH0198285A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0571907A3 (en) * | 1992-05-29 | 1994-02-16 | Eastman Kodak Co | |
| EP0579440A2 (en) * | 1992-07-15 | 1994-01-19 | AT&T Corp. | Method of making an assembly including patterned film submount with self-aligned electronic device |
| EP0579440A3 (en) * | 1992-07-15 | 1994-02-09 | AT&T Corp. | Method of making an assembly including patterned film submount with self-aligned electronic device |
| KR100515765B1 (en) * | 2002-11-18 | 2005-09-23 | 김학연 | A per forator for a ditch |
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