JPH0197141A - Charging circuit for storage battery - Google Patents

Abstract

PURPOSE:To enable controlling a charging quantity appropriately, by equipping an apparatus with a means for surely holding information about the peak value of a divided voltage obtained by dividing the terminal voltage of a storage battery. CONSTITUTION:A storage battery 1 is connected with a charging power source 3 via a charging control circuit 2. In an initial state, the output of a comparator 9 is at a low level, and when a timer circuit 11 is reset and its output reaches a low level, the output of OR circuit 10 also reaches a low level, said charging control circuit 2 is in the ON state, and charging of said storage battery 1 is started. The terminal voltage of the storage battery 1 is divided by a voltage divider circuit 4. The first divided voltage is given to a comparator 6 via a low-pass filter 5 and the output voltage of a memory circuit 7 rises. After the memory circuit 7 held a peak value at the end of charging, the outputs of the comparator 9 and the OR circuit 10 reach a high level, and the charging control circuit 2 controls charging of the storage battery 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a charging circuit for a storage battery, and more particularly to a charging circuit that controls charging by detecting the peak value of terminal voltage of a storage battery.

[Conventional technology]

Various charging methods have been proposed for storage batteries, one of which is to detect the peak value of the terminal voltage of the storage battery during charging, and then charge the battery when the terminal voltage drops by a certain value Δ■ from the peak value. There is a method to stop it.

As a specific example of this method, for example,
Publication No. 4 (hereinafter referred to as the first conventional example) describes the detection voltage of a voltage detection unit that detects a voltage lower than the terminal voltage of a storage battery by a constant voltage (Zener voltage) caused by a Zener diode, and the storage voltage of a storage unit. When the detected voltage is larger than the stored voltage, the stored voltage is increased to make the stored voltage approximately equal to the detected voltage corresponding to the peak value of the terminal voltage of the storage battery. A method has been disclosed in which the difference between the voltage and the detected voltage is amplified by an operational amplifier and compared using a Zener diode, and when a predetermined value is exceeded, charging is stopped.

In addition, Japanese Patent Publication No. 18177 (hereinafter referred to as the second conventional example) discloses a voltage lower than the terminal voltage of the storage battery by the Zener voltage of the first Zener diode and the forward voltage of the reverse current element diode (i.e., the peak The output voltage of a storage circuit composed of a capacitor that stores the corresponding voltage corresponding to the point voltage, and the voltage that is one minute lower than the terminal voltage by the Zener voltage of the second Zener diode (i.e., corresponds to the terminal voltage of the storage battery after the peak) The comparison circuit compares the output voltage of the detection circuit that outputs the corresponding voltage), and when the corresponding voltage decreases and the two types of voltages compared by the comparison circuit match, that is, the terminal voltage decreases by Δ■. A circuit for stopping charging is disclosed.

[Problem that the invention attempts to solve]

However, in the first conventional example, charging is stopped when the voltage obtained by amplifying the difference between the storage voltage and the detection voltage with an operational amplifier exceeds the Zener voltage, but since the Zener voltage changes depending on the ambient temperature, charging may be insufficient. This may shorten the operating time of the device or, conversely, cause overcharging, which can significantly impair the performance of the storage battery.

On the other hand, since the second conventional example also uses a Zener diode, ΔV varies greatly due to temperature changes, so there is a risk of insufficient charging or overcharging.

In addition, ΔV is determined by the combination of Zener diodes, but the Zener voltage of commercially available Zener diodes is discrete (0.2 to lv intervals), and the appropriate ΔV for the storage battery is
It is difficult to obtain a combination that provides V, and from this point as well, the same problem as above occurs.

Moreover, when the number of storage batteries connected in series is small, the appropriate ΔV is small; for example, when the number of storage batteries is about 1 to 3, ΔV is about several mV to several tens of mV, and such a value cannot be achieved with a combination of Zener diodes. It is not practical because it is industrially difficult to obtain.

Furthermore, the first. In both of the second conventional examples, the circuit constants have to be changed depending on the number of storage batteries connected in series, which is complicated.

By providing means for reliably retaining information on the peak value of the divided voltage obtained by dividing the terminal voltage of the storage battery, the present invention can appropriately control the amount of charge, and even when the number of storage batteries connected in series is changed. However, the purpose of this invention is to provide a storage battery charging circuit that can always obtain the optimum amount of charge without making any special changes.

[Means for solving the problem] The charging circuit according to the present invention divides the terminal voltage VB of the storage battery into a first divided voltage VDI and the first divided voltage V by a voltage dividing circuit.
A memory circuit is provided to divide the voltage into a second divided voltage VD2 higher than Dl and - and to store the first divided voltage VD1, and the output voltage v out of this memory circuit and the first divided voltage VDI are Compared with the first comparator, Vout<VDI
By increasing the output voltage of the memory circuit during the period, the output voltage V out becomes the peak value VI of VD1.
I) and further this output voltage v ou
t and a second divided voltage VD2 by a second comparator,
The charging of the storage battery is controlled when V out≧VD2.

[Effect]

During the period when Vout<VDI, the output voltage Vol of the memory circuit
As t increases, even if the first divided voltage VD1 decreases as the terminal voltage VB of the storage battery decreases past the peak point P2 indicating the maximum value VBp, V out remains V
The approximately maximum value VDP of Dl is held.

If the value of VB when the second divided voltage VD2 is equal to Vout is VBe, then V out is Vout-
Since VDp, ΔV-VBp-VBe. From this, by appropriately selecting the voltage dividing ratio of the voltage dividing circuit and setting VDl and VB2, it is possible to freely determine the value of ΔV, and an appropriate value that matches the characteristics of the storage battery can be obtained.

In addition, when a plurality (n) of storage batteries are connected in series and charged at the same time, the terminal voltage VB and its peak voltage VBP are multiplied by n, and the divided voltage VDl,
Since VB2 is also multiplied by n and Δ■ is also multiplied by n, there is no need to change complicated circuit constants, etc.
The same amount of charge as with one storage battery is automatically obtained.

Furthermore, VDi.

Even if VB2 exceeds the input voltage range of the first and second comparators, it is only necessary to change the value of one resistor in the voltage divider circuit, and there is no need to change the Zener voltage or resistance value of the Zener diode. .

〔Example〕

FIG. 1 shows a charging circuit for a storage battery according to an embodiment of the present invention. The storage battery 1 is connected to a charging power source 3 via a charging control circuit 2. The charging control circuit 2 is composed of a switching circuit. As the charging power source 3, a DC power source that rectifies an AC power source to obtain a direct current, or another relatively large capacity battery is used.

There are three resistors R1+R2 on both ends of the storage battery 1.

A voltage dividing circuit 4 formed by connecting R3 in series is connected,
The first divided voltage Vx generated at the connection point of resistors R2 and R3 is passed through a first low-pass filter 5 for noise removal to one input terminal (non-inverting input terminal) of the first comparator 6. terminal). The output of the first comparator 6 is input to the memory circuit 7, and the output voltage V out of the memory circuit 7 is input to the other input terminal (inverting input terminal) of the first comparator 6 and one of the second comparator 9. is input to the input terminal (non-inverting input terminal).

The other input terminal (inverting input terminal) of the second comparator 9 receives a second divided voltage higher than the first divided voltage VDI, which is generated at the connection point between the resistors R1 and R2 of the voltage dividing circuit 4. VD2 is input via a second low-pass filter 8 for noise removal. Note that the time constant of the second low-pass filter 8 is selected to be shorter than that of the first low-pass filter 5.

The output of the second comparator 9 is input to one input terminal of the OR circuit 10. The output of the timer circuit 11 is input to the other input terminal of the OR circuit 10. The output of the OR circuit 10 is supplied to the charging control circuit 2 as a control input. The charging control circuit 2 controls charging by causing a charging current to flow when the output of the OR circuit 10 is at a low level, and by stopping charging or reducing the charging current when the output of the OR circuit 10 becomes a high level.

The CR time constant circuit 12 is a circuit that detects power-on,
The output is input to one input terminal of the OR circuit 13. The other input terminal of this OR circuit 13 is connected to the OR circuit 1
An output of 0 is input.

The output of the OR circuit 13 is applied to the reset input terminal R of the flip-flop 14. A start pulse is input to the set input terminal S of the flip-flop 14. The inverted output terminal of the flip-flop 14 is supplied to the memory circuit 7 and the reset input terminal R of the timer circuit 11.

On the other hand, a resistor 15 is inserted in the charging path of the storage battery 1 to detect the charging current. The terminal voltage of this resistor 15 is input to one input terminal (non-inverting input terminal) of the third comparator 16. The other input terminal (inverting input terminal) of the third comparator 16 is supplied with a - constant reference voltage VS. The output of the third comparator 16 is input to the trigger input terminal of the timer circuit 13.

Next, the operation of the charging circuit shown in FIG. 1 will be explained with reference to the voltage waveform diagram shown in FIG. 2.

When the circuit is powered on, a pulse with a width determined by the time constant is input from the CR time constant circuit 11 to the reset input terminal R of the flip-flop 14 via the OR circuit 13.
The inverting output terminal ζ of the flip-flop 14 becomes high level, and the memory circuit 7 and the timer circuit 11 are reset. Next, the set input terminal S of the flip-flop 14
When a start pulse is input to , the output terminal ζ becomes a low level and the reset state of the memory circuit 7 and the timer circuit 11 is released.

In the initial state, the output of the second comparator 9 is at a low level, so when the output of the timer circuit 11 becomes a low level due to release of the reset state, the output of the OR circuit 10 also becomes a low level, and the charging control circuit 2 is turned on, and charging of the storage battery 1 starts.

The terminal voltage VB of the storage battery 1 gradually increases as the charging time passes, as shown in FIG. Eventually, at the end of charging, storage battery 1 is charged to its capacity t-t(1
00%), the terminal voltage VB rises suddenly, and t
A peak P1 appears at time -tp. This terminal voltage V
Let the peak value of B be VBp. Terminal voltage VB is peak P
When it exceeds 1, it decreases.

The terminal voltage VB of the storage battery 1 is divided by the voltage dividing circuit 4,
A first divided voltage VDI and a second divided voltage VD2 are obtained. Among these, the first divided voltage VDI is given by the following equation.

The voltage obtained by passing this first divided voltage VDI through the first low-pass filter 5 and the output voltage V out of the memory circuit 7 are the first
are compared by the comparator 6.

During the period of VDI≧V out, the output of the first comparator 6 is at a high level, so the output voltage of the storage circuit 7 V out
t also increases.

■When old<Vout, V out stops increasing and V Dl=V out .

As charging progresses, the terminal voltage VB of storage battery 1 further increases,
When the voltage VDI increases accordingly, the same operation as described above is repeated, and the output voltage V out of the memory circuit 7 further increases.

If the voltage VDI at the time t-tp at which the terminal voltage VB reaches its peak value at the end of charging is VDp, then the following equation is obtained. In the period t≧tp after this point tp, Vou
Since t −VDp, V out holds a value equal to equation (3).

On the other hand, the second comparator 9 compares the second divided voltage VD2 from the voltage dividing circuit 4 through the second low-pass filter 8 with the output voltage V out of the memory circuit 7 . During the period of t≧tp, the output of the second comparator 9 remains at a low level during the period of t<te where Vout<VD2, but
When t>te, Vout −VDp>VD2, so the output of the second comparator 9 becomes high level.

As a result, the output of the OR circuit 10 becomes high level, and the charging control circuit 2 controls charging of the storage battery 1. That is,
If VB at the time of t-te is VBe, then Vo
Since ut-VD2, it follows from equation (3), and since ΔV-VBp-VBc, the terminal voltage VB of storage battery 1 can be expressed by equation (4) from its peak value VBP. Charging is controlled at the time te when the voltage decreases by ΔV.

By the way, in the conventional technology described above, the value obtained by amplifying the difference between the storage voltage and the detection voltage is compared with the Zener voltage of the Zener diode (first conventional example), or the value is compared with the peak value of the terminal voltage of the storage battery. A voltage that is lower by the Zener voltage of the first Zener diode and the forward voltage of the reverse current element diode is stored in a memory circuit, and this memory voltage and the Zener voltage of the second Zener diode are lower than the terminal voltage by the Compare the voltage with the second conventional example),
Since charging is controlled when the compared voltages of both types match, there has been a problem that over or under charging occurs due to fluctuations in Zener voltage due to fluctuations in ambient temperature. Since charging is controlled at the time when the maximum value of the obtained first divided voltage and the second divided voltage match, excess or insufficient charging does not occur due to the influence of ambient temperature.

Furthermore, in conventional technology, when n storage batteries are connected in series for charging, circuit constants such as the Zener voltage of the Zener diode and the resistance value must be changed accordingly, which requires complicated measures. I needed it. On the other hand, in the present invention, when the number of storage batteries connected in series becomes n, the terminal voltage VB and its peak value VBp, the first voltage VDI obtained by dividing this voltage and its peak value VDI), and the second divided voltage V
Since both D2 are multiplied by n, ΔV is also multiplied by n, and the same charge amount as in the case of one storage battery can be obtained. Moreover, as the number n of storage batteries connected in series increases, the first and second divided voltages VDI and VD2 become higher and do not exceed the input voltage range of the first and second comparators 6 and 9. Even if there is, the value of ΔV does not depend on the value of resistor R1 of voltage divider circuit 4, as seen from equation (4), so it can be dealt with simply by increasing the value of resistor R1 and lowering VDI and VD2. , the same charge ff1ffi as in the case of one storage battery can be obtained.

In the above embodiment, the timer circuit 11 prevents the storage battery 1 from being destroyed due to overcharging in the event that the charging circuit fails or the characteristics of the storage battery 1 deteriorate, for example, when a peak does not appear in the change in terminal voltage during charging. The time limit is selected to be slightly longer than the maximum charging time under normal conditions. That is, if the charging time does not become V out ≧ VD2 even after the time limit of the timer circuit 11 has elapsed due to the above-mentioned causes,
A time limit output (high level) of the timer circuit 11 is generated and supplied to the charging control circuit 2 via the OR circuit 10, whereby charging is forcibly controlled.

Note that this timer circuit 11 is activated when the voltage across the resistor 15 exceeds the reference voltage Vs and the output of the third comparator 16 becomes high level and is supplied as a trigger signal. The time-limited operation starts when the value is reached.

FIG. 3 shows a connection relationship between a specific example of the storage circuit 7 in FIG. 1 and the first comparator 6. The first comparator 6 is constituted by an operational amplifier or a voltage comparator. The first divided voltage VDI is applied to the non-inverting input terminal of the first comparator 6, and the output voltage of the memory circuit 7 is applied to the inverting input terminal.

The memory circuit 7 is mainly composed of a diode D1, a resistor R6, and a capacitor C. One end of the diode D1 (an anode) is connected to the output terminal of the first comparator 6, and the other end (cathode) is connected to a resistor R5 and a capacitor C. are connected in series to a reference potential point (earth point in this example). The connection point between the diode D1 and the resistor R5 is connected to the non-inverting input terminal of a fourth comparator 17 constituted by an operational amplifier or a voltage comparator. terminal) is connected to its own inverting input terminal and to the inverting input terminal of the first comparator 6.

The first comparator 6 compares the first divided voltage VDI and the output voltage Vout of the memory circuit 7, and when VDI>Vout, the output voltage of the first comparator 6 is at a high level, so the diode By charging the capacitor C via D1 and the resistor R5, the output voltage v out of the storage circuit 7 increases via the fourth comparator 17, but 'V out
When t further increases to V DI −V out, capacitor C is no longer charged and v out stops increasing. Then, as the first divided voltage VDI increases as the charging of the storage battery 1 progresses, the above operation is repeated and V
This continues until DI reaches the peak value VDp. After the first divided voltage VDI reaches the peak value VDp, VDI decreases and the output of the first comparator 6 becomes a low level.
Diode DI is in cut-off state and capacitor C
By blocking the current from flowing from the current to the output side of the first comparator 6 via the resistor R5, the potential of the capacitor C is kept constant, and the output voltage V out of the memory circuit 7 is VD.
I) is retained.

Note that the resistor R5 may be located anywhere within the path from the output terminal of the first comparator 6 to the reference potential point (earth point) via the diode D1 and the capacitor C. Furthermore, the retention characteristics of the memory circuit 7 in FIG. 3 largely depend on the leakage current of the diode D1, but by adding a resistor R7 and a diode D as shown by the broken line, the reverse voltage applied to the diode D1 can be reduced and leakage can be reduced. Retention characteristics can also be improved by reducing the current.

Further, instead of the resistor R5 in FIG. 3, a constant current circuit whose resistance value changes so that a constant current flows may be used.

By the way, in an inactivated storage battery, a peak as shown by P2 in FIG. 2 may appear at the beginning of charging. If such a peak P2 is mistakenly recognized as the original peak P1 at the end of charging, and the peak value appearing on MDI corresponding to this peak P2 is held in the memory circuit 7, the terminal voltage VB will be reset immediately after passing the peak P2. Charging is controlled by the output of the second comparator 9, resulting in a significant charging shortage. However, in this case, the time constant determined by the resistor R5 and the capacitor C is increased, and after 5 to 80% of the time t (100%) for the charge amount of the storage battery 1 to reach its capacity, the change in VDI is Output of memory circuit 7 v ou
This can be solved by making t follow the problem.

That is, in the period t<ta in FIG.
Even if a peak P2 appears in B and a corresponding peak also appears in VDI, as shown in the figure, it will continue to rise although there will be some distortion before and after the peak of P2, as long as the relationship of Vout<VDI holds. , the peak is ignored and Vout
continues to rise. Then, in the period tl<t<tp, Vout follows the change in the terminal voltage VB. Note that when the resistor R5 is used in a constant current circuit, the output voltage of the memory circuit 7 changes linearly as shown by V out in FIG.

In FIG. 3, resistors R6, R8 and transistor Q constitute a reset circuit, and when the input reset signal is at a high level, transistor Q becomes conductive, so that the charge in capacitor C is discharged via resistor R6, and the memory is stored. circuit 7
will be reset. This reset operation occurs when the power is turned on, when the relationship between the output voltage V out of the memory circuit 7 and the second divided voltage VD2 becomes V out ≧ VD2, or when the charging current of the storage battery 1 does not reach a predetermined value. held during the period.

〔Effect of the invention〕

According to the present invention, the terminal voltage of the storage battery is set to the first divided voltage V
dividing the voltage into DI and a second divided voltage VD2 higher than DI,
■By retaining the old peak value VDp in the memory circuit and controlling charging when the terminal voltage VB passes the peak and becomes less than VDP, there is no possibility of excess or deficiency in the amount of charge as in the past. , appropriate charging control can be performed.

Furthermore, even if the number of storage batteries connected in series is changed, the divided voltage V
As long as DI and VO2 do not exceed the input voltage range of the first and second comparators, there is no need to change the circuit constants, etc. If VDI and VO2 exceed the input voltage range of the comparators, It is only necessary to change the value of the resistor R1 of the voltage circuit, and there is no need to change the Zener voltage or resistance value of the Zener diode as in the conventional technology.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a charging circuit according to an embodiment of the present invention, FIG. 2 is a voltage waveform diagram for explaining the operation of the embodiment, and FIG. 3 is a concrete diagram of a storage circuit in the embodiment. It is a figure which shows an example. DESCRIPTION OF SYMBOLS 1...Storage battery, 2...Charging control circuit, 3...Charging power source, 4...Voltage dividing circuit, 6...First comparator, 7
... Memory circuit, 9 ... Second comparator, 11 ... Timer circuit, 12 ... Time constant circuit, 14 ... Flip-flop, 15 ... Current detection resistor. Applicant's agent Patent attorney Takehiko Suzue Figure 2 *rst Figure 3

Claims (5)

[Claims] (1) The terminal voltage VB of the storage battery is divided into a first divided voltage VD1 and a second divided voltage VD2 higher than the first divided voltage VD1.
a voltage dividing circuit that divides the voltage into two; a memory circuit that stores the first divided voltage VD1; and an output voltage Vout of this memory circuit and the first divided voltage VD.
1 and increases the output voltage Vout of the storage circuit only during the period of Vout<VD1; and the output voltage Vout of the storage circuit is compared with the second divided voltage VD2. A storage battery charging circuit comprising: a second comparator; and means for controlling charging of the storage battery when Vout≧VD2 based on the output of the second comparator. (2) The storage circuit includes a diode with one end connected to the output terminal of the first comparator, a resistor and a capacitor connected in series between the other end of the diode and a constant potential point, and a storage battery. The output voltage Vou of the memory circuit increases within the time when the amount of charge reaches within the range of 5 to 80% of its capacity.
2. The storage battery charging circuit according to claim 1, wherein the values of the resistor and capacitor are selected so that t follows the change in the first divided voltage VD1. (3) When the capacitor is turned on, the relationship between the output voltage Vout of the memory circuit and the second divided voltage VD2 is Vou.
3. The storage battery charging circuit according to claim 2, wherein the storage battery is discharged when t≧VD2 or during a period when the charging current of the storage battery does not reach a predetermined value. (4) It has a timer circuit that starts in conjunction with the charging operation of the storage battery, and the time-limited output of the timer circuit starts before the relationship between the output voltage of the storage circuit and the second divided voltage becomes Vout≧VD2. 2. A storage battery charging circuit according to claim 1, wherein said storage battery charging circuit controls charging of said storage battery when said power is generated. (5) The storage battery charging circuit according to claim 4, wherein the timer circuit starts a time-limited operation when the charging current of the storage battery reaches a predetermined value.