JPH0196575A - Radar signal simulating device - Google Patents

Abstract

PURPOSE:To raise an operator's attending sense by adding an interpolation arithmetic part for executing a high speed interpolation processing by a hardware, between an azimuth distance memory and a comparator. CONSTITUTION:By a control use computer 1, a clutter generating range is determined and sent out to an azimuth distance memory 4. The memory 4 outputs distance signals R1(B), R2(B) to interpolation arithmetic parts 5a, 5b. The arithmetic parts 5a, 5b executes an interpolation processing by bringing the present input signal to proportional distribution into equal parts. A distance interpolating signal as a result of interpolation processing is outputted synchronously with a trigger signal. This distance interpolating signal is compared with a reference distance signal of a distance counter 6 by comparators 7a, 7b, and a gate control use pulse is generated. By this pulse, a gate signal is generated by a gate generating circuit 9, and in a gate 11, only a necessary part of an attenuation characteristic signal is fetched and a modulating signal is generated. A clutter original signal which has been modulated by the modulating signal becomes a clutter signal, displayed on a radar indicating machine 13 and becomes a clutter echo being similar to a clutter shape in an actual radar.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for generating clutter in a device for generating a simulated radar signal used for training radar indicating machine operators of a search radar.

[Conventional technology]

Figure 5 is a block diagram of the clutter generation control section of a conventional radar signal simulator, in which (1) is a control computer that controls the clutter generation range, and (2) is the actual radar transmission timing and antenna rotation. A timing generation circuit that simulates
(3) is an azimuth counter that converts the antenna azimuth into a memory address; (4) is an azimuth/distance memory that stores the clutter occurrence range as distance information in correspondence with the antenna azimuth; and (6) is the timing generation circuit. Distance counters that synchronously generate reference distance signals, (7a), (7b)
(8) is a comparator that compares the distance signal output of the azimuth and distance memory with the reference distance signal output of the distance counter and outputs a pulse when the two match; This is the damping characteristic control section. Figure 6 is the same block diagram of the clutter generation modulator and radar indicator of the conventional radar signal simulator.
9) is a gate generation circuit that generates a gate signal only in the clutter existing range using the comparator output pulse;
+11 is a clutter original signal generator that generates an original signal that simulates the reflection of radar radio waves from clutter, and U is a gate signal generator that gates the attenuation characteristic signal of the attenuation characteristic control section using the gate signal output of the gate generation circuit. , aX5 is a modulation circuit that amplitude modulates the clutter original signal, (I3 is a radar indicator. Fig. 7 is an image diagram showing an example of the display of clutter on the radar indicator that occurs in a conventional radar signal simulator. (41b) is a clutter echo.

Next, the operation will be explained. In the control computer +11, the range in which clutter is to be generated is stored in the azimuth distance memory (4) according to the azimuth angle of the antenna using a polar base system formula of near end distance R1 (B) and i far end distance R2 (B). Send and store.

The timing generation circuit (2) generates an azimuth signal at the same rate of change as the rotation speed of the antenna of the actual radar to be simulated, outputs it to the azimuth counter (3), and generates a distance signal stored in the azimuth and distance memory (4). It+(B) and R2(B)
Read out. The timing generating circuit (2) simultaneously generates a trigger signal R, and operates a distance counter (6) in synchronization with this trigger signal to generate a reference distance signal. Comparator (7a).

(7b) is the distance signal output of the above azimuth distance memo month 4).

Compare with the reference distance signal of the distance counter (6).

Generates a pulse when a match occurs. Gate generation circuit (9)
inputs the above pulse and generates a gate signal from R1(B) to R2(B). Attenuation characteristic control section (8)
Then, an attenuation characteristic signal is output based on the reference distance signal of the distance counter (6), and this attenuation characteristic signal is gated by the gate signal of the gate generation circuit (9) at the gate αυ to obtain a final modulation signal. Using this modulation signal, the output of the clutter original signal generator αQ is amplitude-modulated in the modulation circuit α2 to obtain a clutter signal. The clutter signal is displayed on the electron tube of the radar indicator a3 in synchronization with the antenna azimuth B and the trigger signal RO, and the clutter image (41b
).

[Problem that the invention seeks to solve]

Since the conventional radar signal simulator is configured as described above, the shape of clutter on the radar indicator largely depends on the azimuth resolution, and it is difficult to increase the resolution due to limitations in the processing speed of the control computer and the capacity of the azimuth and distance memory. However, the clutter was fan-shaped and did not resemble the clutter of an actual radar, making it unsuitable for use in operator training.

This invention was made to solve the above-mentioned problems, and provides a radar signal simulating device that can bring the clutter shape appearing on the radar indicator closer to the actual radar and enhance the operator's sense of reality. The purpose is to

[Means for solving problems]

The radar signal simulator according to the present invention uses hardware to perform high-speed interpolation between the azimuth and distance memory and the comparator in order to improve the azimuth resolution of the clutter shape without changing the processing speed of the control computer or the capacity of the azimuth and distance memory. It has an additional interpolation calculation section that performs processing.

[Operation J] The interpolation calculation unit in this invention calculates the distance signal R1 (Bt) of a certain direction Bi in the direction and distance memory.

R2 (B i ) and the distance signal R1 of the next direction 13i+1
(J+1).

The R2 (Bi-H) bolts are proportionally interpolated into equal parts, and the azimuth resolution is improved by one equivalent.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

In Figure 1, (1) is a control computer, (2) is a timing generation circuit, (3) is an azimuth counter, (4) is an azimuth distance memory, and (5a) and (5b) are interpolated distance signals from the azimuth and distance memory. The processing interpolation calculation unit (6) is a distance counter.

(7a) and (7b) are comparators, and (8) is an attenuation characteristic control section. In FIG. 2, (9) is a gate generation circuit, IIG is a clutter original signal generator, αυ is a gate, (13 is a modulation circuit, and (131 is a radar indicator). This is a timing diagram showing the signal timing of each part.
11 is the trigger signal 0 country is the read timing of the distance signal.

(35a) and (35b) are the output timings of the distance interpolation signal.

(34a) and (34b) are comparator output pulses for gate control, @ is a gate signal, (to) is an attenuation characteristic signal, @ is a modulation signal, (to) is a clutter original signal, and 01 is a clutter signal. FIG. 4 is an image diagram showing the clutter display on the radar indicator in the embodiment of the present invention, and (41a) is a clutter echo.

Since the present invention is configured as described above, the operation from determining the clutter occurrence range to the azimuth and distance memory in the control computer (1) is the same as that of the conventional radar signal simulating device, but the distance signal The reading timing (2) is performed in synchronization with an integral multiple of the period of the trigger signal (in the example, it is set to 4 times for convenience of explanation), and the direction counter (3) outputs the ten-man direction to the radar indicator. B for angle Bi! +1
The advanced address is specified in the azimuth and distance memory (4). The azimuth distance memory (4) contains the distance signal R1 (J-H),
R2(B++,) is output to the interpolation calculation units (5a) and (5b) at the above timing. In the interpolation calculation section, the previous input distance signals R1 (J) and R2 (Bi) are input into registers, and the current input signals R+ (B H-1),
Interpolation processing is performed by equally proportionally allocating between R2 (B i-H). The interpolated distance interpolation signal is synchronized with the trigger signal 0σ, (33a) (55b')
It is output at the timing shown in . The distance interpolation signal is the reference distance signal of the distance counter (6) and the comparator (7a).
, (7b) and the gate control pulse (34a
), (34b) occur. This pulse generates a gate signal (to) at the gate generation port m+91.
At Lll, only the necessary portion of the attenuation characteristic No. 2 (1) is taken out and a modulated signal 0η is generated. The crack original signal (to) modulated by the modulation signal (b) is displayed on the radar indicator 03 as a clutter signal (to), and is a clutter echo (41a) close to the clutter shape in the actual radar.

For convenience of explanation, in the first embodiment, the number of distance interpolations is set to 4. The output timing was set to be the same as the trigger signal period, but
The output timing may be any number as long as it is an integer multiple of the trigger signal, and similarly the number of distance interpolations may be an integer, producing the same effects as in the above embodiment.

〔Effect of the invention〕

As described above, according to the present invention, since the interpolation calculation unit is added, a clutter simulation signal close to the clutter shape in an actual radar can be obtained without changing the specifications that affect the entire device, such as the control computer or azimuth distance memory. It has the effect of providing a high sense of realism as a radar signal simulating device for training radar indicating machine operators.

[Brief explanation of the drawing]

1 and 2 are block diagrams showing one embodiment of this invention, FIG. 3 is a timing diagram showing operation timing in one embodiment of this invention, and FIG. 4 is a signal table in one embodiment of this invention. FIGS. 5 and 6 are block diagrams of a conventional radar signal simulator, and FIG. 1 is an image diagram illustrating an example of a signal display in the conventional radar signal simulator. In the figure, (1) is a control computer, (21fi timing generation circuit), (3) is an azimuth counter, (4) is an azimuth distance memory, (sa), (5b) is an interpolation calculation unit,
(6) is a distance counter, (7g) and (7b) are comparators, CB) is an attenuation characteristic control section, (9) is a gate generation circuit, αl is a clutter original signal generator, 09 is a gate,
α2 is a modulation circuit, 113 is a radar indicator, C3υ is a trigger signal, oa/ri distance signal reading rB L timing, (33a), (33b) are distance interpolation signal output timing f, (5431), (54b) are hump parators Output pulse, (to) is gate signal, 0 [9 is attenuation characteristic signal, 0 to modulation signal, (to) is clutter original signal,
(to) is the clutter signal. (41a) and (41b) are clutter echoes. Note that in FIG. 1, the same or corresponding parts are designated by the same reference numerals. Figure 2 M4 Figure 6 Figure B Figure 7

Claims (1)

[Claims] A control computer that generates and outputs the range of clutter occurrence in polar coordinates, a timing generation circuit that generates a trigger signal equivalent to that of the radar to be simulated, and an azimuth of the antenna;
an azimuth counter that converts the azimuth of the timing generation circuit into a memory address; an azimuth-distance memory that stores the output of the control computer and sends out the two fastest distance signals recently in the clutter occurrence range according to instructions from the azimuth counter; two interpolation calculation units that temporarily store the distance signal in the azimuth and distance memory and perform interpolation processing by proportional allocation; and a distance counter that generates a reference distance signal in synchronization with the trigger signal output of the timing generation circuit; Two comparators that compare the reference distance signal and the distance interpolation signal of the interpolation calculation unit and output a pulse when they match, and output an attenuation characteristic signal that simulates the attenuation characteristic of clutter in synchronization with the reference distance signal. an attenuation characteristic control section; a gate generation circuit that generates a gate signal using the comparator output pulse;
a Clutter original signal generator, a gate for extracting only a necessary portion of the attenuation characteristic signal using the gate signal and generating a modulation signal, a modulation circuit for amplitude modulating the output signal of the Clutter original signal generator using the modulation signal, and a radar indicator. A radar signal simulator equipped with