JPH0192963A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE:To reduce the phase deviation due to a peak shift of a readout signal by measuring the pulse interval of the readout signal to detect a readout signal pulse having a peak shift over a prescribed value caused next to the consecutive '1s' of the data thereby stopping the phase comparison to the readout signal. CONSTITUTION:A readout signal a1 read from a recording medium and shaped is supplied to a phase difference detection circuit 1, a reset terminal of a counter 7, an inverter 8 an AND circuit 10. The phase difference detection circuit 1 detects a phase difference between the readout signal a1 and a synchronizing signal a5 being an output of the phase synchronizing circuit and outputs a phase lag signal a2 when the synchronizing signal a5 is delayed and outputs a phase lead signal a3 when the synchronizing signal a5 is advanced for a time width of the phase difference. In detecting the transient peak shift after '1s' of data are consecutive, an L level is obtained. An and circuit 6 stops the lead signal a3 from being given to the phase voltage conversion circuit 2 when the signal a13 is at L level. Thus, the synchronizing deviation due to peak shift is reduced without losing the frequency fluctuation tracking performance to prevent data discrimination error.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase synchronization circuit used in a data discrimination circuit of a magnetic recording device.

[Conventional technology]

In magnetic recording devices and the like, a phase synchronization circuit is used to generate a synchronization signal synchronized with a read signal, which is necessary when demodulating a read signal read from a recording medium or the like.

As shown in FIG. 6, the phase synchronization circuit includes a phase difference detection circuit 1
9-phase voltage conversion circuit 2. Low pass filter 3. It is composed of a voltage controlled oscillator (hereinafter abbreviated as vCO) 4 and a divider 5, and operates so that the phases of the input signal and the output signal always match.

Now, consider the case where a read signal α1 having a pattern of 1-110011J is input as shown in FIG. "0
“1” on both sides of “0” becomes “00” due to pattern peak shift.
The bit position shifts to the `` side.

Detecting the phase difference T1 due to this shift, the phase synchronization circuit outputs an advanced phase signal α6 and operates to lower the oscillation frequency of vCO4, that is, to delay the phase of the synchronization signal α5. However, the "1" that comes after l'-00J is
Because of the shift in the opposite direction (advanced direction), the phase difference ΔT between the readout signal α1 and the synchronization signal α5 becomes large, overlapping with the delay of the synchronization signal α5 due to the previous peak shift. If the slam peak shift is large, ΔT will increase, leading to incorrect data discrimination.

For this reason, in conventional phase-locked circuits, when reading data, the response of the phase-locked circuit to peak shifts is suppressed by lowering the loop gain of the phase-locked circuit or lowering the cut-off frequency of the loop filter. There is. Incidentally, as a technology related to this, for example, U.S. Patent No. 38
No. 18501 is mentioned.

[Problem that the invention seeks to solve]

However, the above-mentioned conventional technology has a problem in that when attempting to suppress the response to the peak shift of the phase synchronization circuit, the ability to follow frequency fluctuations of successive signals is limited.

An object of the present invention is to reduce the phase shift due to the peak shift of the read signal without reducing the followability of the phase synchronized circuit to frequency fluctuations.

[Means for solving problems]

In order to achieve the above objective, the pulse interval of successive signals is measured, successive signal pulses having a peak shift of more than a predetermined value that occur after %1' of data are detected, and the phase of the successive signals is compared. We have provided a means to stop this.

[Effect]

By stopping the phase comparison of the readout signal that has a peak shift of more than a predetermined value that occurs next to the 11' series of data, unnecessary responses of the phase synchronization circuit can be prevented, and the phase difference between the successive signal and the synchronization signal can be prevented. is reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the circuit configuration, and FIG. 2 shows signal waveforms at each part thereof.

The successive signal α1 read from the recording medium and shaped is sent to the phase difference detection circuit 1. Reset terminal of counter 7, inverter 8. The signal is input to the AND circuit 10.

The phase difference detection circuit 1 detects the phase difference between the synchronization signal α5, which is the output of the phase synchronization circuit, and the readout signal a1, and outputs the synchronization signal α5.
is delayed, the delayed phase signal a2. Synchronization signal α
5 is ahead, an advanced phase signal α3 is output for the time width of the phase difference.

The phase voltage conversion circuit 2 and the low pass filter 5 are as follows.

The lagging phase signal α2 serves to raise the voltage level of the signal α15, and the signal α14 obtained by gating the leading phase signal α3 lowers the voltage level of the signal α15.

Voltage controlled oscillator (VCO) 4 changes the frequency of its output signal α4 according to the voltage level of signal α15. The frequency divider 5 generates an output signal α5 obtained by frequency-dividing the signal α4 to a frequency suitable for phase comparison and a signal necessary for demodulating a subsequent signal (not shown). The counter 7 counts using the output α4 of the VCO 4 as a clock, and is reset when the successive signal α1 becomes the “H” level.
The pulse interval of the read signal α1 is measured using the vCO clock as a reference. The counter value is a predetermined count value N
A or NB, the respective signals α6. α7
Output. Here, NA is set to a value when the pulse interval of the read signal α1 corresponds to an excessive peak shift,
NB is set to the value when the pulse interval is based on 101 of the data.0 Edge trigger D type flip-flop (hereinafter referred to as
Abbreviated as D-F, F. )9 is set when the signal α6 becomes the 1H level, and is triggered at the moment the signal α1 changes from the 1H level to the ``L'' level, and sets the signal α8 to the 1H level -r.

The AND circuit 10 performs an AND operation on the signals a8 and al, and outputs the signal α9. Therefore, the signal α9 is output when the pulse interval of the read signal α1 is such that the data “1” continues normally.

D-F, F, 11.12 is triggered at the moment the signal α6 changes from the %L' level to the 1-H level, and is reset by the signal α9. D - F, F, 11 D-cover 'H' Level K Fixed I Thio'), D -
F, F, 12 (7) D-F, F, 1 for D input
1 output signal α10 is connected. The signal α10 is
After the reset signal α9 is input, the first pulse of the signal α6 changes from the 'L level to the %H level.

Then, the signal α11 is changed by the next pulse of the signal α6.
'H Lepere changes to 1L Lepere.

The SR latch 13 is set by the signal α7.

It is reset by signal α9. Therefore, signal α1
2 becomes 1L level when the pulse interval of the read signal α1 corresponds to the data ``0'', and holds the ``L'' level until the next data 111 is normally continued.

The output signal α13 of the NAND circuit 14 is the signal α10. α1
1 and α12 are all at the %Hl level, that is, when an excessive peak shift is detected after successive "1's" of the data, the signal becomes the %LJ level.The AND circuit 6 outputs the signal α
13 is 1L level, input of the advanced phase signal α3 to the phase voltage conversion circuit 2 is stopped.

With the above operation, 11' stops the phase comparison for the next consecutive excessive peak shift.

This prevents unnecessary responses of the phase synchronization circuit and prevents an increase in the phase shift between the successive signal α1 and the synchronization signal α5.

In this embodiment, since the output signal α4 of the VCO 4 is used as the clock for the counter 7, the function can be maintained normally even if a frequency fluctuation occurs in the successive signal α1.

Also, in cases where excessive peak shifts are detected consecutively or are detected following "01" in the data, etc.

Phase synchronization circuit so that phase comparison does not stop.

The following characteristics are not restricted.

〔Effect of the invention〕

According to the present invention, it is possible to prevent an unnecessary response of the phase locking circuit to an excessive peak shift following a series of ``1''s in the readout signal, so that the frequency fluctuation tracking performance of the phase locking circuit is not impaired (synchronization due to peak shift is prevented). Discrepancies can be reduced and data discrimination errors can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a phase locked circuit according to an embodiment of the present invention, FIG. 2 is a signal waveform diagram of each part shown in FIG. 1, FIG. 3 is a diagram of a conventional phase locked circuit, and FIG. 4 is a diagram of a conventional phase locked circuit. It is a signal waveform diagram of each part. 1... Phase difference detection circuit, 2... Phase voltage conversion circuit, 3... Low pass filter, 4... Voltage controlled oscillator, Attorney Masaru Ogawa 1 Okan 3 Kananawa 4 [! 1

Claims (1)

[Claims] 1. In a phase synchronization circuit installed in a magnetic recording device and generating a synchronization signal from a read signal, means for measuring the pulse interval of the read signal, and means for detecting a peak shift of a predetermined value or more from the measured pulse interval. 1. A phase synchronization circuit comprising means for stopping phase comparison of pulses of a read signal having a peak shift of a predetermined value or more.