JPH0192840A - Data processor - Google Patents

Abstract

PURPOSE:To optionally set up the internal state of a processor at the time of starting an EIT processing handler by fetching information indicating the internal state of the processor simultaneously with the reading of the leading address of the EIT processing handler from an external storage device. CONSTITUTION:The internal state variable of the data processor is read out from the external storage device together with the leading address of the EIT processing handler. Thereby, a program designer can program the internal state or the like of the data processor in each EIT processing by previously writing the internal state variable of the data processor to be used at the time of executing each EIT processing together with the leading address of the EIT processing handler at the rate of 1 to 1. The internal state variable is arranged on a position adjacent to the leading address of the EIT processing handler and automatically read out at the time of EIT processing. Consequently, it is unnecessary for the program designer to individually specify the rewriting of the internal state variable every EIT processing.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a data processing device, and more specifically, to an interrupt processing device.
Exception handling and internal interrupt instructions for
This paper proposes a data processing device that integrates multiple step instructions.
be. [Prior art] Conventionally, interrupt handling mechanisms, exception handling mechanisms, and internal interrupt
Data with an EIT processing mechanism such as an embedded instruction processing mechanism
In the data processing equipment, a request to process ε1 is generated, and
When the receiver is attached and EIT processing is started, the internal state
After saving the information indicating the
Internal state variables defined as functions of the data processing device
Processing is performed by automatically rewriting the internal register value to the value of
was. Figure 388 shows the flowchart of the conventional EIT processing startup method.
-Show a chart. EIT processing at 1007 in Figure 388
When the request is accepted, 100B is sent to the data processing device.
The start address of the EIT processing handler is stored in
The address of the external storage device is generated and the EIT is sent in 1009.
Reads the start address of the processing handler and starts data processing.
A program program that stores data indicating the internal status of the
The status word (hereinafter referred to as PSW) is a data processing device.
to a predetermined value for EIT processing in
Updated. For example, when an external interrupt is accepted
etc., its receiver has a higher priority than the external interrupt it is attached to.
External interrupts are accepted until the EIT processing is completed.
Priority is given to acceptance of EIT processing during PSW for prohibited purposes.
The variable indicating the degree is automatically changed to '8'. next
, Stack of processor information at 1010 in FIG.
After evacuating to 1011, the contents of the EIT are
EIT processing handler pre-programmed with
Start. [Problems to be solved by the invention] However, in this method, when the EIT processing handler is started,
The internal state of the data processing device is uniquely determined.
Therefore, there are many restrictions on program creators, especially when multiplexing
For data processing equipment when performing εIT processing on
It was difficult for the program creator to set the state in which the
. In other words, as mentioned above, in the past, the EIT processing handler was activated.
When the internal state is predetermined by the data processing device,
This is something that can only be done and is a challenge for program creators.
This was a constraint on program creation. Also,
The program creator uses the data when starting the EIT processing handler.
It is necessary to be fully aware of the internal state of the processing equipment, and if
Depending on the situation, it may be necessary to reset the internal state variables yourself.
The process was complicated. The data processing device according to the present invention solves the above problems.
The EIT process was initiated and
The start address of the εIT processing handler is saved from an external storage device.
At the same time, when loading the
It also reads some of the internal state variables of the data processing unit.
and start the EIT processing handler based on that information.
Allows you to set the internal state of the data processing device at the time,
Additionally, if multiple EIT processing requests occur at the same time,
Determine the content of IT processing and based on the priority of that processing
It includes a multiple EIT processing means for determining the processing order, and
When returning from one EIT processing handler, the subsequent E
Provide a means for special treatment of 11 conditions for IT processing
and a data processing device that facilitates program creation.
The purpose is to provide. [Means for Solving the Problems] A data processing device according to the present invention is a data processing device that processes a program consisting of a plurality of instructions.
interrupts from outside at the boundaries of each instruction process.
means for detecting interrupt processing in response to a read request signal, means for detecting an instruction exception event, and detecting trap processing that is the execution of an internal interrupt instruction.
means, and a plurality of E classified into any one of the above three types of processing.
Each IT process has its own priority and processing method.
a means for selecting whether to start an IT process;
This is the state at the time the EIT processing was started.
The internal information that contains the first information group that will be rewritten at the time of system startup.
A means for storing the state in an external storage device, and a series of processes corresponding to the EIT process selected above.
The starting address of the EIT processing handler to be executed is stored.
The address of the above external storage device that is located in the above selected EIT processing
1 'i! for each theory! and means for generating J1.
, Furthermore, the above EIT is placed at the address of the external storage device generated above.
The above EIT processing hand along with the starting address of the processing handler
becomes part or all of the new internal state at the start of execution of the
The second information group, which is a candidate for
Stored on a one-to-one basis for each part or all of the processing.
It is characterized by [Function] In the data processing device according to the present invention, the EIT processing handler
The internal state variables of the data processing device as well as the start address of
Since each EI can be read from an external storage device,
The program creator must perform EIT processing in advance for T processing.
When each EIT process is performed with the start address of the management handler,
Writes the internal state variables of the data processing device on a one-to-one basis.
By keeping each EIT processed separately in the data processing device
It is possible to program the internal state, etc. Also this
The internal state variable is next to the start address of the EIT processing handler.
It is located in the same position and is automatically read during EIT processing.
Therefore, the internal state variables are updated every time EIT processing is performed.
It is not necessary for the program creator to make individual specifications. Also
EIT processing is included in the internal state variable stored by this function.
By including the priority specification information of
When T processing occurs, EIT processing with high priority
Prohibiting the activation of low-priority EIT processing by
Can be done. Easy for program creators as described above
A wide range of processing can be specified. Also, EIT
Installed a function that handles EIT processing detection processing specially after processing.
11ﾾ allows single-step processing by exception handling.
When executing a backup, the same EIT process is repeated.
Avoid situations where instruction execution does not proceed due to
be able to. [Embodiment Fig. 389 shows a data processing device which is an embodiment of the present invention.
Flowchart 1 of the EIT processing startup method is not shown. First, when a request for EIT processing is accepted in 1001,
In step 1002, E is received according to the contents of the EIT process.
An IT vector number is generated and its EIT vector number
The EIT processing handler is stored in the value multiplied by 8.
Set the thread bottom address (1α (EITVTR) of the IT table to
In addition, the start address and PS of the EIT processing handler
A part of W (hereinafter referred to as EITVTE) is stored.
An address for the external storage device is generated. That in 1003
EITVTE, which is address data, is read and 1
Partial comparison with the value of p s'w when EIT processing occurs in 004
and updated. The data specified by the updated PSW value
Under the internal state of the processor information
Tack evacuation (1005) and activation of EIT processing handler (
1006) is performed. FIG. 390 shows E I TVTE which is an embodiment of the present invention.
The format is shown below. EITVTE not shown in Figure 390
consists of 8 bytes, of which 4 bytes are EI.
vPC (1025
) value so that 2 bytes specify part of psw.
The remaining 2 bytes are set in consideration of flexibility and expandability.
It's dawn. In Figure 1003, VS (1020) is
Stack pointer usage mode when starting EIT processing handler
1-bit data for specifying the code, VA (1021) is E
Context data size when IT processing handler starts
1-bit data indicating whether it is 32 bits or 64 bits,
VAT (1022) is the address when the εIT processing handler starts.
2-bit data indicating address conversion mode designation, VD
(1023) is debugging when starting the EIT processing handler
1-bit data indicating the presence or absence of a mode, V IMASK
(1024) is an interrupt when starting the EIT processing handler
This is 4-bit data that specifies the reception level. PS%I! when starting EIT processing! These five fees in
updateable. Also, these fields are simple
EITV for some fields instead of updating to
Compare the value during TE and the value at EIT detection and then update.
You can also determine whether For example,
The attached level specification field is E for cases other than external interrupts.
I The value during TVTE and the value before update are at a high level (value
(smaller) is the new value, and occurs in the case of an external interrupt.
The priority of the external interrupt and the level during EITVTE are
The higher (smaller) value is the new value. FIG. 391 shows EIT processing in the data processing device of the present invention.
The external storage device pointed to by the stack pointer when the system is started
A group of information indicating the internal state of the data processing device that is saved to the location
This figure shows an example of the above. In the figure, 1026 indicates data processing at the time when EIT processing is started.
The PSW of the physical equipment, 1027, depends on the type of EIT processing.
1 byte of data indicating the type of stack format,
1028 is 1 byte of data indicating the type of EIT processing;
1029 is lO bit data indicating the EIT vector number.
1030 is the data processing at the time when the EIT processing is started.
4-byte area for storing the PC value of the management device, 1031
stores various additional information depending on the type of EIT processing.
Each indicates an area of several bytes. FIG. 392 shows a data processing device which is an embodiment of the present invention.
Stack format according to the type of EIT processing in
shows. In the figure, 1032 is format 0, 1033 is
Format l, 1034 is format 2, 10
35 is the step in each EIT process of format 3.
In this example, each stack format is
The content of additional information differs depending on the format. FIG. 393 shows a data processing device which is an embodiment of the present invention.
The internal state that is updated when multiple EIT processing is performed in
It shows the state variables and the stack frame formed.
be. In Figure 393, the internal interrupt instruction
Wrap instruction (TRAP) and external interrupt request (El)
An example of multiple occurrences is shown below. Data in the example of Figure 393
In data processors, trap instructions are better than external interrupt requests.
Since this is a high-priority EIT process, the trap instruction is processed first.
Activates EIT processing for external interrupts, and then responds to external interrupts.
Activate the EIT processing. Therefore, the above multiple EIT processing
After acceptance, EI for external interrupt is sent to PC 1036.
The start address of the T processing handler is fetched and 1037
The PSW contains E which is taken in during external interrupt processing.
Values compared and updated by ITVTE become obsolete.
. In addition, the stack formed by the above multiple EIT process
What is initially stored for the frame, i.e.
We will explain the contents stored in the lower address first. First, 1044 indicates the PC at the time the trap instruction occurred.
value (EXPC), and 1043 is the next instruction of the trap instruction.
P Cf+W of the command, 1042 is the trap command figure 1
Not shown in 004 and corresponds to 1027.1028.1029
EIT processing information is stored in 1041 before executing the trap instruction.
PSW heat, 1040 for trap command
Set the start address of the EIT processing handler to 1039.
1038 contains the EIT processing information of the interrupt.
P S compared and set by instruction EITVTE
'VV values are stored respectively. Store as above
When the EIT processing handler is started by
First, the EIT processing handler for external interrupts is attached.
to respond to a trap instruction from the stack frame information.
The EIT processing hands are activated, and the multi-ffi E I
T can handle it. The following is a more detailed example of data processing of the present invention.
I will explain. Since the explanation is long, I have included a table of contents and
Parts that require detailed explanations are provided in the form of appendices. Much is said about EIT, especially in Appendix 9.
. Table of contents 1. Features of the device of the present invention 1-1. Basic design philosophy 1-2.05-oriented architecture 1-3. Tuned instruction set 1-4. Compa
Irresistible instruction set 2, device of the present invention 32 and device 64 of the present invention 3, classification of device specifications of the present invention 4, register set 5, data type 5-1. Bit 5-2. Bit field 5-3. Integer 5-4. Floating point number 5-5. Decimal number 5-6. String 5-7. Queue 6, Instruction Format 6-1.2 Operand Short Form 6-1-1. Between register memories (S-format, L-format) 6-1-2.
Between registers (R-format) 6-1-3. Literal-memory (Q-format)
6-1-4. Immediate-memory (1-form
at) 6-2.1 Operand - Hull format (Gl-format) 6
-3.2 Operand - Ship shape 6-3-1. The first operand is memory read G-f
ormat) 6-3-2. The first operand is an 8-bit immediate
(E-format) 6-3-3. The first operand is address calculation (GA-f
ormat) 6-3-4. Other 2-operand instructions 6-4. show
Tobranch 6-5. Others 7. Addressing mode? -1, P bit 7-2. Symbols used in the format 7-3. Regis
7-4. Register indirection 7-5. Register Relative Indirect 7-6, Immediate 7-7.7 Busolyute? -8, PC relative indirection 7-9. Stack pop? -10, Stack Bush? -11. Register relative addition mode? -12, PC relative addition mode? -13, Absolute addition mode? -14, FP relative indirect? -15, SP relative indirect? -16. Format of append mode? -17. Additional mode specification level 8, implementation related matters 8-1. Virtual memory support 8-2. Rewriting instructions by program 9, EI
T processing 10, PSW configuration 10-1. PSS configuration 10-2. PS) I configuration 10-3. Changes in flags 11, description of instruction set 11-1. Overview of description format 11-2. Instruction bit pattern and assembler notation 11-3. Field name 11-4. Operand field name 11-5. Restrictions regarding addressing mode 11-6. Notes on Explanation 12, Instruction Set of the Device of the Present Invention 12-1. Data transfer instruction 12-2. Comparison, test instruction 12-3. Arithmetic operation instruction 12-4. Logical operation instruction 12-5. Shift instruction 12-6. Bit manipulation instruction 12-7. Fixed length bit field manipulation instruction 12-8.
Arbitrary length bit field manipulation instructions 12-9. Decimal operation
Instruction 12-10. String instructions 12-11. Cue instruction 12-12. Jump command 12-13. Instructions for multi-processors 12-14.
Control space, physical space operation instructions 12-15. O5 related instructions 12-16. MMU Seki Destiny Luck Instructions 10 Invention Device Instruction Set Reference Appendix 20 Books
Appendix 31 About the assembler notation of the invention device Appendix 40 Overview of the memory management system of the invention device
Device flag change Appendix 5. Appendix 6 regarding operations between different sizes. Subroutine call appendix 7 for high-level languages. control
Registers and control space Appendix 80 CTXB of the device of the present invention Appendix 90 EIT processing of the device of the present invention Appendix 10. Instruction set pattern appendix 11 for the device of the present invention.
Detailed specifications of high-performance instructions and register values at end Appendix 12. Appendix 13. Operation when operands interfere.
Ensuring consistency of cache and TLB 1, H 1-1.・The device of the present invention is not a RISC. High-speed execution of basic instructions
With this as our first goal, we added more advanced instructions.・32 bit version of the present invention device 32 and 64 bit version of the present invention device 32
32-bit version and 64-bit version.
The version chips were made into a series. Therefore, 64 bits
Is expansion to 64-bit addressing the first step?
are taken into consideration. -ITR is a real-time O5 developed with O5.
0N (Industrial-TRON) and Works
BTRON (Bus in
ESS-TRON) was designed to run at high speed. The device of the present invention satisfies the TR0N<<LIR>> specifications and has special
The focus is on high-speed processing in real memory environments.・Microprocessor that will be the core of future ASIC LSI
shall be. 1-2. O5a -” - Performs bitmap movement and calculations required by the bitmap operation support instruction BTRON.
To perform high-speed task switching in the now instruction φ context switch instruction lTR0M
command/queue operation instruction lTR0N ready queue and wait queue operation
memory management with now instructions and two-level ring protection (future expansion
We have prepared two more levels of rings for you. ) 1-3. Yuunin taa"se...high frequency
short instructions and short addressing modes
Tuning Shorten the instruction length for inter-register operations and literal operations 1-4. Copper-a's loss%1 ・Orthogonalized instruction set ・Data retention, address retention, index value retention
16 general-purpose registers that can be used for various purposes such as
light is possible.・Source operan that allows calculations between different data sizes
Specify the size of the command and destination operand separately.
Can be determined.・High-performance jump instruction 2, +1" for high-level languages
The bit version of the device 64 of the present invention is handled as a series.
, expansion to a 64-bit version was considered from the beginning.
This is a major feature. In the device 64 of the present invention, the 64-bit
A space of linear addresses is provided. The device 64 of the present invention also handles data handled by the device 32 of the present invention.
In addition to data types, it can handle 64-bit integers.
. How to switch between 32 bits and 64 bits in the device 64 of the present invention
The law is as follows: - Regarding the data size of the operand, the size specification bit that exists for each instruction and each operand
Therefore, 32 bits and 764 bits per instruction and operand.
Select. For data size, 32 bits,
In addition to 64-bit, 8-bit and 16-bit are also available.
Therefore, the selection of four sizes can be specified using a 2-bit field.
to be determined. The device 32 of the present invention does not handle 64 cut data;
An instruction that specifies a bit data size is treated as an error. Regarding the size of the φ pointer, the device 32 of the present invention normally uses a 32-bit pointer;
Although a 64-bit pointer is used in the device 64, the device of the present invention
64 executes the object code for the device 32 of the present invention.
Therefore, the device 64 of the present invention has a pointer size of 32 bits.
A mode is provided to enable This mode is specified in the PSW.
Therefore, each context (process or task)
32-bit program and 64-bit program
It is possible to mix. In addition, expansion for 64-bit addressing is required.
Operands that involve memory access are used as expansion bits.
A reserved bit called the "P bit" is provided for each
Ru. Command to switch pointer size from 32 bits to 764 bits
The reason why we chose the mode instead of the instruction unit is for the following reasons.
Ru. For pointers, mixing different sizes
is essentially impossible. That is, a pointer
is used to distinguish between locations, so at least one bit is 64 bits.
If there is, do not make the entire pointer a 64-bit pointer.
This is because it cannot be distinguished. Therefore, a 32-bit pointer and a 64-bit pointer
Even if you switch it for each instruction and make it possible to mix them,
Most of the time, the same specifications are repeated in each context.
This results in inefficient bit allocation. In such situations, modes are more appropriate. When changing the mode between 32/84, change the mode.
When to set the compatibility between the inventive device 32 and the inventive device 64
Questions may arise as to whether compatibility is possible. death
However, the default is a 32-bit pointer.
and change the mode when using 64-bit address.
If the present invention device 64 is configured to
You can run the program for 32 as is.
. Also, it is possible to switch between 32-bit pointer and 64-bit pointer.
Even if switching is done by instruction instead of mode, the O5
where to set the stack, the system call parameters
Whether the meter is 32 bits or 764 bits.
In order to determine that each context is
You need to be aware of whether it is 64-bit or 64-bit.
Ru. In that case, in psw (saved to the stack)
Those who can determine 32-bit/64-bit by looking at the mode.
is sometimes useful. 3. El's -ζ In the device of the present invention, expansion to a 64-bit version, serialization,
In order to respond to requests such as adaptation to various uses, etc.
, implementation is optional.
It has a function. Positioning of such “optional features”
In order to clarify, the specifications of the device of the present invention are classified as follows.
Separate. <(Log> Specification (Level O) As the device of the present invention
This is a specification that must be met. An example of the <<IQ>> specification is the program seen from the user program.
logging model (most of the ISP, general purpose registers,
PSH), machine language bit patterns, etc. In the specifications, there are parts where nothing is written in particular.
Specifications. <<Ll>> Specification (Level 1) Implementation
As a general rule, it is important to keep the
If you want to create a processor with specifications, it is not necessary to create an input processor.
This is a specification that does not require rement. <<Ll>> Specifications include string instructions and additional modules.
Advanced functions such as codes, queue manipulation instructions, and bitmap instructions
function commands, etc., but specifically which commands are <<Ll>> function commands?
It shall be determined separately whether the <<LIR>>Specifications (Level I Real)
<<Ll>> From the specifications, the function of the instruction re-execution intermediary and the MMU
This is a specification that removes the related functions, and is compatible with lTR0N and μBTR.
Specifications for efficiently running ON etc. based on real memory.
be. The instruction set of <<LIR>> is almost the same as <cll>>
The compiler and user programs can be used in common.
make it possible to do so. However, MMU intermediaries (MOVPA, etc.)
), regarding some orders of the O5 staff (JRNG)
, there are things that are not supported. <<L2>> Specification (Level 2) Future hardware
This is a specification that is scheduled to be introduced as the amount of hardware increases.
. Specifications for increasing the symmetry of instructions and speeding up operations.
There are new instruction specifications to be added accordingly. An example of the former is the 2/B' option of the BVSC) I instruction.
string instructions, complex termination conditions in string instructions, and infinite stages.
An example of the latter is the INDEX command.
and so on. In the specifications, the <<L2>> specification part is replaced with <<L2>>
Shown. <<LX>>Specifications (eXtension) Inventive device 6
This is a specification that is scheduled to be introduced with the expansion to 4. It has the same meaning as the L2 specification, but for the device 64 of the present invention.
Therefore, it is treated as a separate class. An example of the <<(, x>> specification is a 64-bit operation instruction, etc.)
be. In the specifications, the <<LX>> specification part is replaced with <<LX>>
Indicated by <<LU>> Specification (Undefined) For future expansion
Therefore, this is a specification that is scheduled to be introduced, but at this stage it is not yet possible.
No specific specifications have been presented. <<1v>> Specifications (Variable) Each manufacturer has all
This is a part where you can freely decide on the specifications. Regarding chip bin placement, pipeline stages and performance
Specifications, instruction bit patterns assigned to each manufacturer
Examples of <<Lv>> specifications, such as how to use control registers and control registers.
It is. Among these, the instruction bit pattern assigned to each manufacturer
For bit patterns, refer to L in the bit pattern reference.
It is indicated by Vreserved. <<LA>> Specifications (Alternative) This invention system
The standard specifications for the installation are presented (or
), but if there are other unavoidable reasons
This is a specification that may be changed. Of course, the specifications can be changed.
Compatibility may be lost between modified parts. <
<LA>> The specifications do not guarantee compatibility as TR0N.
It has very good specifications. <<LA>> Examples of specifications include memory management method, control register
This includes some data and privileged instructions, mainly related to O5.
It's a minute. The device of the present invention does not have a built-in MMU, and is particularly suitable for high performance in a real storage environment.
Aim for fast processing. ＜＜LA＞ Regarding secondary memory management
>Most of the specifications are not supported by the device of the present invention. 4. Register t1 - In the device 32 of the present invention, there is one general-purpose register with a length of 32 bits.
In the device 64 of the present invention, there are 6 general-purpose registers with a length of 64 bits.
There are 16 pieces. Stack Pointer
-SP), frame pointer (Frame Point
er-FP) is included in the general-purpose registers. SP is
R15 and FP become R14. -Program Counter
r-PC) are not included in the general-purpose registers.・General-purpose registers hold data, hold base address,
Alternatively, it can be used as an index register for various purposes.
Can be used.・Registers that hold the state of the processor (Process
sor 5tatus Word -PSW). FIG. 1 shows the register of <<LX>> in the case of the device 64 of the present invention.
Showing tassets.・SP is context (ring number, interrupt processing)
Switches accordingly.・PS connection consists of 4 bytes. The lower first byte is
Processor 5tatus By
te-PSB), the lower second byte is the user mode setting.
(In conjunction with PSB, Processor 5tatu
s Halfword -PSH)% Top 2 bytes
This is used to display the system status.・The device of the present invention is a so-called big-endian chip.
The data on the register is 8 bits, 1
The 6-bit data is packed and arranged on the LSB side. However,
So, the absolute bit number that is unrelated to the data size is
cannot be defined. When discussing bit numbers
must be handled in combination with the data size. this
is called a "bit position".・For 8-bit data on the register, the bit position
is 0.1 from the MSB side. ,,． It can be numbered 7. Also,
For 16-bit data on the register, the bit position
is 0.1 from the MSB side. ,,． 15, Regis
For 32-bit data on a computer, the bit position is MS
0.1 from the B side. ,,． It is numbered 31. therefore
, 8-bit data bit position 70 bits, 16 bits
Data bit position: 150 bits, 32 bits
The 310 bits in bit position are physically the same bit.
Ru.・Instructions that use registers as destination operands
In this case, the data size on the register side is 8 bits and 16 bits.
If it is a bit, the upper byte is unaffected and
There will be no change. This is true if the operation is not performed in memory.
This is in line with the specifications of Even the upper bits are affected
If you want to give it, use operations between different sizes. c Example MOV #)l'12345678. R.O., W.M.
OV #) l'aa, Ro, 8RO=H' 12
It becomes 3456aa.・When placing 8-bit or 16-bit data on a register
For example, MOV,
W #l('12345678. RONOV, B
The result of #H'aa, RO NOV, W RO, R1 is R1=H'123456aa. On the other hand,
If you do the same thing for Mori) NOV, W #H'12345678. @RONO
V, B #H'aa, @RO M0V, W @RO, R1 contains the MSB side of 8-bit and 16-bit data.
Therefore, RI=H'aa345878. Care must be taken as the results are different in registers and in memory.
It is. In the device of the present invention, a so-called big-end is adopted.
are doing. That is, byte address specification, bit number
When specifying the number, the smaller number (address) is MSB (
Most 51gn1ficant Bit/Byte
). In big-endian, certain data in memory
When viewing it as 8-bit data and 16 (32
) The address will be different when viewed as cut data.
Therefore, caution is required. For example, address:
N N+I N+2 N+3 data
: 0 0 0 H'12
In this case, the content of address H as 32-bit data is
H'00000012 (H' represents hexadecimal)
), treat data with the same content as 8-bit data
In this case, address N+3 must be referenced. However, regarding the data on the register, 8-bit data
Since the 16-bit data capacitor is packed and placed on the SB side,
Therefore, the data placed in the register can be transferred as is to another size.
data. For example, MOV #O,RO,W MOV #)l'12. The result between Ro, 8 and V RO, enemy, R1, enemy is R1=H'0OO00012. (of command
(See main text for meaning) On the other hand, if you do the same thing to memory, MOV
#O, @RO, W between V #H'12. @RO,B MOV @RO,W, R1,W contains 8-bit data H'12 and 32-bit data M
Since the SB side will be aligned, R1=H'120000
It becomes 00. The data types supported by the device of this invention are explained below.
I will clarify. As shown in FIG. 2 on the top of the screen, the target bits are inside the bold lines. For bit operations in memory, offset is an arbitrary register.
For bit operations on the register, offset is one register.
Specifying bits limited to within the star (ignoring the upper bits of offset)
is the base-address specification, base-ad
Set of dress size specification and offset specification
It is carried out by When targeting bits in memory, base-a
The MSB of the memory address indicated by ddress is of
The bit fset=0. At this time, base-ad
The specification of the size of ddress depends on the bits actually manipulated.
It does not affect the Bit manipulation instructions
access to read-modify-write
trace-address to specify the space size.
size specification is used, but the access size is different.
However, the bits that are actually manipulated are the same. On the other hand, when targeting bits on a register, ba
Data specified as the size of se-address
The MSB of the size becomes the bit of offset=o. If the base address size is different, the actual
The bits that are manipulated will also be different, so be careful.
It is essential. 5-2. Bill ~ - Rule' - Signed bit field As shown in Figure 3, the area inside the thick line is the target bit field.
Ru. 0 < Width ≦ 32 (<<LX>
>O< width ≦S: From the MSB of the sign bit base-address, select the target bit file.
Bit spacing up to the MSB (sign bit) of the field
is the offset. 8F: Bit field operation on memory using G instruction
In this case, offset is arbitrary. 8F: Bit field operation on memory using E instruction,
and 5ba for bit field operations on registers
1 word (10 words) of se-address
Preserves the behavior of bit fields that protrude.
I don't testify.・Unsigned bit field As shown in Figure 4, the area inside the thick line is the target bit field.
Ru. 0 < width ≦ 32 (<<LX>
>O< width ≦base-adre
From MSB of ss to MSB of target bit field
The distance between the bits is the offset. BF: Bit field operation on memory using G instruction
In this case, offset is arbitrary. 8F: Bit field operation on memory using E instruction,
and for bit field operations on registers, ba
1 word (10 words) of se-address
Preserves the behavior of bit fields that protrude.
I don't testify. - Arbitrary length bit field Both offset and width are arbitrary. However, widt
Figure 5 shows the integer data type. Floating point operations are handled by a coprocessor. The floating point format is the IEEE standard. Details separately
stipulate.・ Single accuracy 32 Bitsuto floating decimal Copro sessa〉〉〉〉 倍 倍 ６ ６ ６ ６ く く く く く く く く く く く く く く く く く く く く く くOperations are handled by a coprocessor. The main processor of the device of the present invention operates as shown below.
Fixed length unsigned PACKED format decimal format decimal number
Handles EO format decimal numbers in numbered PACs. However, the sign
PACKED format lO decimal format l Upper numbers are all <
<L2>>. Figure 6 shows the data types. 5-8. 1- Figure 7 shows the data type for strings. Data of linear list connected by double link to Dan 21yo-LL2 Figure 8
Indicates type. 6.1+1-ma... The instruction has a variable length in units of 16 bits, and an odd number of bytes
There is no order from the chief. Broadly speaking, 2-operand instructions require 4 bytes + extension.
It has a configuration of
) available general forms and frequently used commands and addresses.
Short form that can only use shing mode (Sh), 02
There are two formats. Required instruction functions and code
You can choose the most suitable one according to your size.
Ru. The instruction format of the device of the present invention requires careful attention to detail.
It can be divided into many different types. However, it is difficult to understand
For ease of explanation, the instruction format of the device of the present invention will be described here.
We will roughly categorize and explain. instruction format
See Appendix 10 for details. The meanings of the symbols that appear in the format are as follows:
. Part where the operation code is placed # Part where the literal or immediate value is placed Ea General addressing mode specified with 8 bits
Sh Short addressing mode specified in 6 bits
The description of the partial format for specifying the Rn register has the LSB side on the right side and the high address side.
I'm wearing a dress. (big-endian) four
An example of mat description is shown in FIG. If you don't see the 2 bytes of address N and address N+1, the command
The format cannot be determined, but this
The instruction is always fetched in units of 16 bits (2 bytes).
This is because it is assumed that the data will be decoded. In either format, the Ea value of each operand is
The extension of Ea or Sh must be the base of Ea or sh.
placed immediately after the halfword that contains it. This is the command
More implicitly specified immediate data and instructions
Prioritizes extensions. Therefore, an instruction of 4 bytes or more
The instruction opcode is separated by the Ea extension.
There may be cases. In addition, additional modes can be added to the expansion section of Ea.
Even if an extension is attached, it is
These are given priority. For example, if the first half word contains Eat and the second half word
6 bars containing Ea2 in the word and up to the third half word
Consider the case of an ``ite'' instruction. Use append mode for Eal
Therefore, in addition to the normal extension part, there is also an additional mode extension part.
shall be taken as a thing. At this time, the actual instruction bit pattern is the first halfword of the instruction (including the basic part of Eal), the extension of Eat, the additional mode extension of Eal, the second halfword of the instruction (including the basic part of Ea2), the extension of Eat This is the order of the third halfword of the division instruction. Note that due to alignment, the 16-bit field
In the case where only 8 bits are used, the 8 bits used are
The bits are packed in descending order (larger address).
shall be This applies when the operand size is 8 bits,
Specify #imm-data mode for EaR and ShR.
If the operand size is 8 bits in I-format,
5S with 8RA:G, Bcc:G, BSR:G
=00, etc.
”For example, MOV:1. B 1tH'12. In the case of @ROj, the
One byte is MOV:1. B's opcode, second byte is
Part of the opcode and ShW<@RO) specification, third byte
The first byte is 0, the fourth byte is H'12, and the bit pattern is
is as shown in Figure 1O. In this case, the upper side of the 16-bit field (address
8 bits (the smaller one) must be filled with 0.
Must be. If the upper 8 bits are not O, this
The data expressed as
shall be. In other words, l-format, #im
In m-data mode, the operand is
BRA:G, Bee:G, BS
In the case of an R:G instruction, the jump destination is undefined. Either
In this case, it is not considered an EIT (or an exception). 3-1.2 Open ゛-poor 3-1-, Shigu-Moi. -or at -fo m An example is shown in FIG. L-format and S-format instructions have a size
(7) (MOV: L, MOV: S, C)
MP: L) and items whose size cannot be specified (ADD: L,
Sue:L). For instructions that can specify the size, specify the size using RR etc.
applies only to the memory side, and the size of the register side is 32
The bit is fixed. If the sizes on the register side and memory side are different, the source
Sign extension is used when the destination size is small.
If the size of the side is small, cut the upper byte and
A check is made for overflow. On the other hand, ADD:L, Sue:L life where size cannot be specified
For instructions, both the register side and memory side operand size are
It is fixed at 32 bits. The reason why the size of the register side is fixed at 32 bits is because of this development.
In bright devices, ``data in registers is
The following principle was established:
This is because This principle applies to L-format,
In addition to S-format instructions, bit field instructions and
Also suitable for placing operands in registers with high-performance instructions.
used. 6-1-2. Cash register - cash register βR-forlT
An example is shown in FIG. 6-1-3.1--Room Q-format
An example is shown in FIG. An example is shown in FIG. 1-format immediate value size is
8.1 in common with the operand size on the destination side.
6,32.64 bits, zero extension and sign extension are row
I can't get used to it. 6-2.1 Open゛-' Gl-format No. 15
An example is shown in the figure. 6-3.2 Page-I Included here is a single ship address specified with 8 bits.
This is an instruction with two operating mode operands.
. The total number of operands may be three or more. An example is shown in FIG. 6-3-2. - Vane is 8bi... Me Eiji]
An example of this is shown in Figure 17. This format and the immediate-to-memory format
Pine) (1-format) is functionally similar.
However, they are very different in terms of way of thinking. E-fo
rmat is just a 2-operand-ship shape (G-for
mat), and the size of the source operand is
Fixed to 8 bits, destination operand size
You can choose from 8/IS/32/64 bits.
. In other words, assuming calculations between different sizes, dest's
The 8-bit src is zero-extended or signed depending on the size.
The number is expanded. On the other hand, I-format has a high frequency, especially in NOV and CMP.
It is a shortened form of an immediate pattern with many
Yes, source and destination sizes are equal
. An example of this is shown in Figure 18. 6-3-4. Part 2 Vane'. ΔFigure 19 shows the
Give an example. 6-4. Figure 20 shows an example. In addition to those who are minor offenders, there are cases such as those shown in Figure 21. 7. The addressing mode of the device of the present invention includes registers.
The abbreviated form (Sh) is specified in 6 bits, and the short form (Sh) is specified in 8 bits.
There is a general form (Ea) to specify. If an undefined addressing mode is specified or the meaning
A set of addressing modes that is obviously strange when you think about it
If combination is specified, if an undefined instruction is executed,
As in the case, a reserved instruction exception (RIE) is generated and the exception handling
Start. This applies if the destination is an imide
In the case of real estate mode, the address calculation instruction
For example, when using eight mode. In the device of the present invention, one bit is stored in response to each memory access.
You can assign optional feature specification bits for
This bit is called the P bit. The P bit has some other meaning associated with memory access.
This bit is used when you want to add. The P bit is specified independently for each memory access.
. Therefore, register indirect addressing, absolute
In cases such as mute addressing, it corresponds to the operand.
specifies one P bit, but using append mode
In multi-stage indirect addressing mode, only the number of stages
This will specify the P bit of . The P bit is used for tag checking, logical space
Switching between 32-bit addressing and 64-bit addressing
There are switching of lettings, etc., but all of these are
This is for future expansion, and the P bit is reset in the current specification.
It is rVed. In the explanation of the instruction format, the P bit part is referred to as lpl.
This is displayed, but this must be set to 0.
No. If the P bit is not O, the
An instruction exception (RIE) occurs. The function related to the P bit is the <<LU>> specification. 7-2. -Ma... -wa Yuki 0Rn
Register specification PP bit (must be 0) mem[:EAI In memory at the address indicated by EA
The part surrounded by a dotted line below the figure indicates an expanded part. 7-3. Official assembler notation: n Operand: n Format: Shown in Figure 22. 7-4. cash register . Assembler notation: @Rn Operand: mem[Rn coformat: Shown in Figure 23. 7-6, 9 ・μ Assembler notation: Operand: mem[disp + Rnn Column shown in FIG. 24. Note that disp is treated as signed. 7-6, Mini assembler notation: #imm-data Operand: imm-data Format: Shown in Figure 25. Note that the size of imm-data is the same as the operand size.
specified in the instruction. 7-7, ~τ Uniassembler notation: @abs @abs:16 @abs:32 @abs:64 <<LX>> Operand: mem[abs] Format: Shown in FIG. In addition, when using 32-bit addressing, ABS: 16
The address specified by is sign-extended to 32 bits. Ma
In addition, when using 64-bit addressing, abs:16.
The address specified with abs:32 is sign expanded to 64 bits.
It is stretched. 7-8. P.C. Assembler notation: @(dJsp, pc) @(dJsp:18.PC) @(disp:32.PC) Operand: mem[disp + PC] Format: Shown in FIG. The PC value referenced in PC relative indirect mode is
This is the start address of the instruction containing the operand. However,
So, for example, an infinite loop is realized by the command JMP @(0,PC). The same applies when the PC value is referenced in attach mode.
Similarly, the first address of the instruction is used as the PC-relative reference value.
use. 7-, , - Assembler notation: @SP+ Operand: mem[SP] Increment SP Format: Shown in FIG. In 9SP+ mode, SP is imported by the operand size.
Increment. For example, with the device 64 of the present invention, a 64-bit
When handling data, SP is updated by +8. B
, @SP0 can also be specified for operands of size H.
ability, and each has +1 SP. Updated by +2. However, the stack alignment is broken and the speed decreases.
Please be careful when using it as it may cause. The @SP1 mode has no meaning for the operand.
A Reserved Instruction Exception (RIE) is generated for such cases. Specifically, the reserved instruction exception (RIE) is write.
e operand, read-modify-write
0SP+ for the operand. 7'-10,--' Your assembler notation: @-SP Operand: Decrement SP mem[:SP] Format: Shown in FIG. In @-5P mode, SP is decoded by the operand size.
Crimment. For example, in the device 64 of the present invention, a 64-bit
When handling data, SP is updated by -8. B,
@-SP can also be specified for an operand of size H
, and SP is updated by −1 and −2, respectively. Ta
However, the stack alignment is broken and the speed decreases.
It is better to be careful when using it as it may cause the problem. operan
For those where the mode of @-5P has no meaning for the
If so, a reserved instruction exception (RIE) is generated. concrete
The reserved instruction exception (RIE) occurs when the read opera
read-modify-write operand
It is @-5P for. 7-11. Register...Lomo operand: Rn ==> tmp Additional mode processing format: Shown in FIG. Additional modes will be explained in a later chapter. ''' 2... -〇 Operand: PC==> tmp Additional mode processing format: Shown in Figure 31. -3,...Model operand: 0 ==> tmp Additional mode processing format: Shown in Figure 32 7-14.FP statement/□ Assembler notation: @(disp, FP) @(disp:4.FP) Operand: mem[d4 * 4 + FP code(disp
= d4 * 4) Format: Shown in Figure 33. d4 is treated as signed and is independent of the size of the operand.
Always use d4 multiplied by 4 regardless. Therefore, this
Depending on the mode (FP -8 * 4) to (FP + 7
*Memory addresses in multiples of 4 up to 4) can be referenced.
It is. When writing in assembler, display
Write the value multiplied by 4 as the statement. This addressing mode is <<L2>>. Main departure
Since the FP relative indirect mode is not implemented on bright devices, this
If addressing mode is specified, reserved instruction example
It will be outside (RIE). This addressing mode is not available in abbreviated form, so
, for example, MOV @(disp, FP), R1
ni, MOV: G, enemy@(disp:4.FP), RIM
OV:L, W @(disp:16.FP), R1 is
Both are 4 bytes, and if there is ambiguity in the code selection,
There is a problem. The reason why this mode is called <<L2>> is as follows.
Due to reasons. This mode is the device 64 of the present invention.
The aim is to make effective use of abbreviations when the proportion of abbreviations decreases.
It is something that @(d4:4.FP), @(d4:4.SP) mode
Then, regardless of the operand size, use d4 times 4.
8-bit, 16-bit, and 32-bit raw
@(d
4:4. FP), @(d4:4.SP) mode is used.
When trying to do so, the device of the present invention is big-endian.
For some reason, align the MSB side of each variable with a word boundary.
need to be placed. This causes particular problems.
It's not a big deal, but you need to be careful. @(d4:4.FP), @(d4:4.SP)%-de
Figure 34 shows an example of local variable arrangement for use.
. 7-15. SP vs. 13F Assembler notation: @(disp, SP) @(disp:4.SP) Operand: mem[d4 * 4 + SP co(disp
= d4ne4) Format: Shown in Figure 35. d4 is treated as signed, and d4 is always multiplied by 4 regardless of the size of the operand. However, the operation when d4 is a negative value is not specified. Therefore, with this mode, the number of 4 from (SP) to (SP + 7 * 4) is
Multiple memory addresses can be referenced. When writing in assembler, write the value multiplied by 4 as the displacement. This addressing mode is <<L2>>. Main departure
Since the FP relative indirect mode is not implemented in modern devices, if this addressing mode is specified, a reserved instruction exception (RIE) will occur. This mode is also the same as @(disp:4.FP).
This is aimed at making effective use of the invention device 64 when the proportion of abbreviated forms decreases. ? -16,・Romo's -pine Complex addressing can basically be broken down into a combination of addition and indirect references. Therefore, if addition and indirect reference operations are given as addressing primitives and can be combined arbitrarily, any complex addressing mode can be realized. Addition mode is an addressing mode based on this idea. Complex addressing modes are particularly useful for inter-module data references and A1 language processing systems. However, in the device of the present invention, if the memory indirect addressing mode is used frequently, the processing speed may decrease, so sufficient care must be taken when using the memory indirect addressing mode. The addition mode is specified in units of 16 bits, and this is repeated any number of times. One-stage addition mode allows addition index of constant (displacement)
Register scaling and addition scaling perform x1, x2, x4, x8 memory indirect reference. The N-stage addition mode allows indirect references up to N+1 stages. Basic addition mode processing: tmp + Rx * 5cale + d4 * 4
==> jmp When I=o, o=o, tmp
+ Rx * 5cale + dispx==>
tmp l=0. When D=1, mem[tmp
+ Rx * 5cale + d4 * 4] ==>
tmp I=1. When D=O, mem[tmp +
Rx * 5cale + dispx ==> t
mp I=1. Basic format when D=1: Shown in FIG. E l =00 No indirect reference, continue addition mode tmp + disp 10Rx * 5cale ::> tlImp EI=01 Indirect reference, continue addition mode mem[tmp + disp + Rx * 5cale] ==> tmp El=10 Indirect No reference, end of addition mode tmp + disp + Rx 5calel ==> address of operand EI=11 Indirect reference, end of addition mode mem[tmp + disp + Rx * 5calel ==> address of operand M=0 <Rx> Use as index = 1 Special index <Rx> = Do not add O index (Rx = 0) <Rx> = I Use PC as index Rx (Rx = PC) <Rx> = 2 ~ reser ed D = The 4-bit d4 in the 0 addition mode is multiplied by 4 to obtain disp, and this is added. d4 is treated as signed, and d4 is always multiplied by 4 and used regardless of the size of the operand. D=1 Set dispx (16/32/64 bits) specified in the extension section of the addition mode to disp, and add this. The size of the extension part is specified in the d4 field. d4=0001 dtsp X is 16 bits d4=oo10 disp X is 32 bits d4=0011 disp Size S=O<Rx> is 32 bits sign extended S=1 <Rx> is 64 bits <<LX>> PP bit <<11>> ・P bit is included in each stage of addition mode. P bit is It is called "a pit that can be specified independently for all memory references." - You can choose whether or not to use indirect references. Stages that are not indirectly referenced are used for addition of multi-stage pace registers and index registers. ( mem [R1+R2+R3, etc.) This is the knee f level.
f) Et telelocation base reg
It may be used when you want to introduce ister etc.・Size of index register Because it is expected that 32-bit data will appear quite frequently even when using 64-bit addresses, the size can be switched between 32,764 in each stage of the addition mode.・Register relative indirection @(disp:64,Rn) and
The memory indirect addressing mode is also realized using the additional mode. -pccz is scaled by i'' The resulting effective address will be an unpredictable value, but no exception will occur. Care must be taken not to specify x2, x4, x8 scaling for the PC in the manual, etc. Variations of ?-17, ~ How to use the level addition mode of mode' include ordinary indirect references, external variable table references for modularizing object code, and A1-oriented is used to execute instructions, and for A1 purposes, a fairly large number of stages of indirect references may be used, but for normal purposes, indirect references of up to 3 to 4 stages are often sufficient. If the optional number of stages addition mode can be used, the compiler does not need to differentiate between cases based on the number of stages, which has the advantage of reducing the burden on the compiler.Even if the frequency of multi-stage indirect references is very low, the compiler This is because it must be possible to generate correct code.However, from an implementation standpoint, allowing an arbitrary number of stages and accepting interrupts during execution would be quite burdensome, so the overall balance Therefore, it is unavoidable to limit the number of stages to some extent.Therefore, the device of the present invention is designed to be able to use up to 4 stages of additional modes (4 stages of the basic format of additional modes). arbitrary stage
Implementations of the number addition mode are classified as <<L2>> specifications. Even with the <<Ll>> specification, up to five memory indirect references are possible. For append modes of five stages (five halfwords) or more, a reserved instruction exception (RIE) is activated. However, since the format allows for any number of columns, it is possible to expand the number of columns in the future with the same format. The device of the present invention allows an arbitrary number of stages to be added. However, in the device of the present invention, if the additional mode is used and memory indirect addressing is used extensively, the processing speed may decrease, so care must be taken. Particularly when the second operand uses a multi-stage addition mode, care must be taken because interrupts may not be accepted during the addition mode processing. Furthermore, considering that the device 232 of the present invention also handles floating point numbers, '×8' scaling is implemented. The scaling of ′×8′ is based on the <<11>> specification, not the <<l×>> specification.
be. 8. 1-8-1.
(The device of the present invention does not support virtual memory.) In order to realize virtual memory, it is necessary to
It is necessary to perform a good recovery process against a disaster fault.
be. In principle, the device of the present invention adopts an instruction re-execution method.
use If a page fault occurs in the instruction re-execution method,
, the processor updates all the registers that have been changed so far.
After reverting, start the page-in processing routine.
Ru. Therefore, after resuming processing, the instruction is re-executed from the beginning.
However, no contradiction arises. In the instruction re-execution method, as a general rule, the state in the middle of execution is maintained.
The implementation mechanism is relatively simple. Ma
In addition, the device of the present invention takes into account re-execution of instructions and processes
Instructions that leave side effects or addressing modes (optional)
(e.g. start increment) as much as possible.
. However, replaying from a page fault requires an extra
memory access may occur, and the input/output device is not connected to O5.
Care must be taken when operating it. For example, in the -ship shape command, the first operand is 17
Performs a read of 0 and causes a page fall on the second operand.
If a crash occurs, re-execute the command to reset 110 again.
This may cause conflicts depending on the type of Ilo.
vinegar. Therefore, 110 with side effects depending on the lead.
If accessed, the other operand of the instruction
Be careful not to cause page faults with
It is also necessary to specify in Al. Specifically, the other operand is always a register or
It suffices if it is a parked page. Also, the source operand and destination can be set using the MOV instruction etc.
If the operation operands partially overlap, a simple replay is performed.
Inconsistency may occur in execution, so
Caution is also required. Example: Shift 2 bytes of data by 1 byte. Destination spans page boundaries. In FIG. 39, NOV, l (by command [N-2:N-1
] to [N-1:N, the destination
The write bus cycle is divided into two. First, the data of [:N-2] is written to [:N-11], and then
Assume that [original N-1] is written in [N]. page M-1 causes a fault when writing to [N-1]
, after page-in, [N-2:N-1 calls> [N-1: N calls are tried again]
Even if you try to do so, the contents of N-1 have already been rewritten, causing a contradiction. Furthermore, instructions that perform multiple data transfers such as LDM
However, if the transfer source and transfer destination overlap, it is necessary to avoid conflicts when re-executing the instructions. For example, in the case of LDM @Re, (R6-RIO), R6,
Page fall when reading R8 after loading R7
If this occurs, R6 will have already been rewritten when the instruction is re-executed, and if the instruction is actually executed from the beginning, a contradiction will occur. To avoid this, it is necessary to take the following measures. - Check that a page fault does not occur at the beginning of the instruction.・Save a temporary value indicating the address being transferred on the stack when a page fault occurs.・Memorize the initial value of R6, and return it to the original value when a page fault occurs. The same applies to STM and other instructions. In addition, in order to re-execute instructions without contradiction, in LDM, STM, and LDCTX, additional
Forbidden mode. Also, ENTER, EXIT,
In JRNG, addresses that involve memory access are
All operating modes are prohibited. 8-2. Advancing to Professional Games In stored program type computers, it is generally possible to rewrite the instruction program itself to be executed from now on. However, in recent high-performance processors that have instruction briefetching and instruction caches, attempting to guarantee operation even when instructions are rewritten in a program places an extremely heavy burden on the hardware. Moreover, this function is not necessary and is not desirable in terms of software education. Therefore, in the device of the present invention, it is prohibited in principle to rewrite the instruction code to be executed by software, and the operation is not guaranteed in such a case. However, if you look at the operation of the entire system, from O5 to the user, there is a flow such as loading and executing a program at some point, so it is not possible to say ``operation is not guaranteed'' in all cases. . In addition, for special purposes, it may be necessary to generate an instruction code using a user program and execute it. Therefore, when certain conditions are met, it is necessary to guarantee that the instruction code rewritten by software will execute. Therefore, in the device of the present invention, an instruction PIB is prepared that informs the processor that the instruction code has been rewritten, and this instruction is executed.
This ensures that the rewritten instruction code will continue to be executed. There is a possibility that the instruction code to be executed from now on for this instruction has been changed since the previous time (at reset or when the previous PIB instruction was executed).
Used to notify the processor that there is a In implementation, this instruction purges the vibe line, instruction queue, and instruction cache. 9. EIT processing In the device of the present invention, EIT processing is performed asynchronously with the flow of program execution.
The processing performed is collectively called EIT processing. EIT processing is usually called exception processing or interrupt processing.
It is something that EIT processing includes the following:
included.・Internal interrupt (inter-ring calls, traps) system
It is generated consciously by the programmer when issuing a call. It is related to the context in which it is being executed at the time. - Exception interrupt (exception) Occurs when some kind of error occurs during the execution of a general instruction. It is related to the context in which it is being executed at the time. - External interrupt (interrupt) Generated by an external hardware signal. It has no relation to the context in which it is running at the time. EIT is Exception (exception interrupt), I
interrupt (external interrupt), Trap (internal interrupt)
The name is a combination of the first letters of ``interrupt''. EIT department
See Appendix 9 for detailed details. 1, W psυ (Processor 5tatu) of the device of the present invention
s Word) is 32 bits. PSW bottom 16
bit (PSH-Processor 5status)
) ralfword) is for user programs;
It can be freely operated from the user process. Top PSW
16 bit (PSS-Processor 5 tat
us halfword for System)
This is for the stem, and from the user program (ring 3)
It can not be operated. The upper 8 bits of PSH are used for various modes.
This is the part that configures the PSM (Process
or 5 status byte for Mode)
call. In addition, the lower 8 bits of PSH are used for various statuses and
This is the part that displays the calculation results, and the PSB (Proc
essor 5 status Byte). 40th
As shown in the figure. 10-1. It is shown in Figure 41 of PSS. If an attempt is made to write reserved '1' to 20', a reserved function exception (RFE) will occur. SM, RNG = 000 externally divided by ringo
Included stack pointer (SP 1) used SM, RNG = 001 reservedSM
,RNG=010 reservedSM,R
NG = 011 reservedSM, RNG
= 100 Stack port for ring O with ringO
Inter (SPO) used SM, RNG = 101 reserved (
for ringl) SM, RNG = 110 res
erved (for ring2) SM, RNG = 11
1 Use ring3 to set the stack pointer for ring 3 (S
P3) SM and RNG used are <<LA>> XA = 0 32-bit context XA
= 1 64-bit context <<LX>> AT = 00 No address translation AT =
01 With address conversion (M of the device standard of this invention)
MU specification) AT = 10 No address conversion, address
Memory protection by (<<LIR>>) AT = 11 reserved (Add
Res Translati. n mode) DB = O Context not being debugged DB = 1 External interrupt, DI (DeIaye
Interrupt priority IMASK = 0000 NMI (priority O)
Only non-maskable interrupts) are accepted in IMAS = 0001 Masks (unmaskable interrupts) up to priority 1 are accepted.
In the end, only NMI will be accepted) IMASK = 0010 Mask I up to priority 2
Accept only interrupts with higher priority than the interrupt indicated by MAS IMASK = 1110 Mask up to priority 14
Group ASK = 1111 No mask/Invention device
The device has 4 levels of ring protection as the <<LA>> specification.
Perform memory management using (see appendix). With the device of the present invention
performs memory management using two levels of ring protection. The RNG field indicates which ring the processor is currently in.
This indicates a situation where the For example, if you do not use ring protection,
, use this field to switch user mode.
Ru. - The XA bit is reset in the device 32 of the present invention.
d, and if you try to write 1, an exception will occur.・For information on debugging staff such as tracing, see the details.
Since it is difficult to unify the details, a separate control register (O
CR-Debug ControlReg 1ster
). However, it does not indicate whether debugging is in progress.
PS will include only this information as a DB.・For external interrupts of the device of the present invention, lower priority is more important.
It becomes a number. The priority of external interrupts is from 0 to 607 levels.
priority 0 is a non-maskable interrupt (NMI
).・It is difficult to completely unify cache and MMU control information
Therefore, it is separated from PSW.・Insert AT (address translation specification field) into PS
address translation and memo for each context.
change the protection method, or while the EIT processing handler is running.
It is now possible to temporarily stop address translation.
It has become. In addition, LDC, REIT, LDCTX, EIT startup, etc.
As a result, the AT (address translation bit) in the PSW is 0.
If changed from 0 to 01, TLB and cache
The purge of TLB and logical cache is performed automatically.
The integrity of the information shall be guaranteed. Also, is AT 01?
00, the cache (in this case
(logical cache and physical cache) consistency is guaranteed.
shall be 10-2. It is shown in Figure 42 of PS) I. If an attempt is made to write reserved 21' to 20', a reserved function exception (RFC) will occur. PRNG The state before entering this ring
The ring number PRNG is <<LA>> p P-bit ErrorFlag
<<LUG> P-bit6! Set when a function-related error occurs, and cleared otherwise. Currently reserved in O
It is used to determine the cause of instruction termination. X, Extension Flag
Shows the results of double length multiple length calculations, etc. V Overflow Flag over
– Indicates that a flow has occurred. L Lower Flag comparison life
Indicates that the first operand is smaller in commands, etc. (Both signed and unsigned operations) M MSB Flag Indicates that the MSB of the operation result is 1. l Zero Flag operation result is
Indicates that the value has become 0.・In the PRNG field, "previous ring" means "previous ring".
"outer ring" or "service that ring"
It represents the requested ring. Therefore, the change in PRNG when EIT occurs is PSW<RNG
＞ ==> When PSW<PRNG> returns (RE
The change in PRNG in an IT instruction is as follows: Stack ==> PS corruption (including RNG and PRNG). When returning, instead of copying from RNG
, it is necessary to return from the stack. RNG≦PRNG always holds true. P
RNG is intended for reference in AC5 instructions, etc.
, the actual ring transition only uses RNG information.・In processors other than the device of the present invention, comparison ~ condition jump
When using a flow of instructions such as jump, it is common to distinguish between signed and unsigned data using a conditional jump instruction rather than a comparison instruction. For example, compare unsigned integers with CMP 5rcl, 5rc2 BLTS next Branch Lower Than (Signed
), the signed integer comparison is performed using CMP 5rcl, 5rc2 BLTU next Branch Lower Than (Unsigned
Perform step d). Therefore, in addition to the information expressed by flags, the information expressed by flags is
It is also necessary to distinguish between However, in the device of the present invention, the distinction between signed and unsigned instructions is different from CMP instructions and CMPU instructions.
Conditional jump instructions are the same for both signed and unsigned instructions. Therefore, the flag configuration can be simplified.・CarryFlag used in normal processors is
The meaning of expressing the magnitude relationship of unsigned integers, and the meaning of multiple precision
It has the meaning of representing the carry of an operation. However, regarding the latter, since the device of the present invention uses XJlag, the Carry Flag is not aligned.
It is used only to express the magnitude relationship between numbers. Therefore, TR0NCHIP
Define the flag as a flag that expresses a magnitude relationship, and name
The front is L-flag (Lower Flag). This frame
The lag behaves the same as the conventional Carry Flag for unsigned operations, but
In the case of a ``CarryFlag'' operation, it is different from the conventional CarryFlag.
It expresses a true large-booth staff that takes into consideration everything from
Ru.・Other termination conditions for string instructions and queue instructions
FJlag (General Flag) to indicate
and PJIag(P-
bit ErrorFlag). PJIag is
, in the current specifications it is reserved at '0'.
Ru.・In a normal processor, bits that are left over by a shift instruction are
I am using Carry Flag to insert the
, in the device of the present invention, LJ is used instead of Carry flag.
Since lag is implemented, the protruding bits are X-f
I will put it in lag. 10-3. -G's addition/subtraction instructions, comparison instructions, and logical operation instructions are two-operand instructions.
and the form of dest, op, src ==> dest
Take. If the dest and 5rcO sizes are different, the small
The smaller size is sign extended (A) to match the larger size.
DDU, 5LIBtJ. In the CMPU, the calculation is performed after zero extension), and the calculation result is
is converted to the size of dest and then stored in dest.
It will be done. For CMP, CMPU, SUB, 5UBU, L-fl
ag indicates that the first operand had a smaller value in the previous operation.
to show that Unsigned calculation CMPU. In case of 5UBU, L-flag is normal processor
It has the same meaning as the Carry (Borrow) Flag of
Ru. For signed operations, Ljlag is simply Mj
Unlike copying lag, even overflow is included.
Expressing true size relationships. In case of ADD instruction, LJ
Iag indicates that the result is negative. This is also just M
Unlike JIag copy, even overflow is included.
It shows the true positive and negative. In the case of ADDU, the result is always correct.
Therefore, the flag becomes O. VJlag specifies that the result of the operation is the size specified by dest.
This shows that it could not be expressed in the In other words, the performance
The calculation result is dest signed integer (ADDU,
5UBu, when it cannot be expressed as an unsigned integer), v-
flag is set. In CMP and CMPLI commands
, V-flag are unchanged. XJIag performs a carry when performing multiple-precision operations.
Used to hold the state of. Signs are also used in signed operations.
The change is similar to that of unsigned arithmetic. This is usually
It has almost the same meaning as the processor's Carry Flag.
However, the instructions that change XJIag are addition/subtraction instructions and
This is limited to commands such as foot commands. CMP instruction and SUB instruction, and CMPU instruction and 5uB
The change in L-flaH of the U instruction is exactly the same. XJIag does not change for Sue, 5UBU, and 5UBX instructions.
, but it does not change with CMP and CMPU instructions. MOV, MOVU, ADD, ADDU, ADDX, S
uB, 5UBU. In the case of 5UBX instruction, M-flag and Z-flag are
Based on the value after converting the calculation result to the size of dest
and change. Therefore, when the destO size is smaller than the src size
Z-f la8 is set even if the operation result is not 0.
It is possible that On the other hand, in the case of CMP and CMPU instructions,
The Z-flag in the case is based on the value of the calculation result itself.
It is not related to the size of dest. Example: @dest, Sue when 8 = 1 #) l'lo1. W, @dest, B=;
〉Operation result, result 1-)! 'lo1 is not 0, but dest is O, so ZJl ag is set. CMP #H'lO1, W, @dest, B==>
Since the calculation result 1-H'lO1 is not O, the 2-flag is cleared. Changes in flags for ADDX and 5U8X instructions are somewhat irregular.
It has become. This is a command sign for extension operations on unsigned integers.
This is to deal with extended operations on signed integers. this place
In this case, the conditional jump instruction mnemonic corresponds well.
However, the extended operation itself is infrequent and irregular.
It is unavoidable because I have a face. LJ l ag Large and small scale as a signed operation (
SUBX), positive and negative (ADD X). VJlag Overflow as signed operation
shows. For Xjlag ADDX, dest + sr
c+ The carry from the size of dest in the calculation of XJlag, and in the case of 5 usx, represents the subtraction from the size of dest in the calculation of dest - src - Xjlag. However, in any case, if the size of SrC is smaller than the size of dest, src is sign extended. In 5tJBX, if the sizes of src and dest are equal, XJIag will eventually represent the comparison result as unsigned data. When performing calculations between different sizes using ADDX and 5UBX
, the smaller size is sign-extended. But the sign
Either treat the value after expansion as a signed number, or use it as an unsigned number.
Whether it is calculated based on the number depends on the flag. In the MOV instruction, MOVU instruction, and logical operation instruction,
JIag and L-flag do not change. With logical operation instructions
In this case, VJIag also does not change. Changes in the flags corresponding to each instruction are explained in the instruction set description.
shown inside. ′☆ゝ are points that require attention. 11. OA set! Regarding the description 11-1. [Mnemonic] Indicates the mnemonic in the name of the command. [Function of the command] An overview of the function of the command is shown. [Instruction options] Indicates the types of instruction options that can be used with the instruction. Instruction options are used to change details of an instruction's functionality.
'/xxx in assembler notation.
Described by ゝ. [Instruction bit pattern and assembler notation] Instruction bits
Patterns, their assembler representations, and available size species
Indicates the type, etc. In the device of the present invention, one instruction mnemonic
Multiple instruction formats such as general and abbreviated forms for
There may be multiple addresses, each with an address that can be used.
They have different sing modes and sizes. In this section, life
The contents will be clarified by order format. [Flag change] Indicates the change in status flag (PSB) after instruction execution
. [Explanation] Explain the function of the command. Please note that the details of assembler mnemonics that appear in the explanation are
For details, please refer to the appendix at the end of the book. 11-2. . ΔBi...Pa -ゝSeゝ 1 instruction
The bit pattern and assembler notation are formatted.
mnemonic, operand name, operand field
name, consisting of an instruction bit pattern. Description example: Shown in Figure 43. AMONG--Explain mnemonics by format
Indicates mnemonics for each format of instruction bit patterns (see appendix). 3rc, dest--operand name A variable used to describe the function of the instruction. This variable is used to determine the function of the instruction and
Referenced in ``Theory''. Order of operands written here
is the order of the operands in the assembler. EaR, EaM--operand field name operand
The field name collectively represents information such as correspondence with bit patterns, operand sizes and addressing modes that can be used, memory access methods, and other restrictions. Certain principles are established between the characters representing operand field names and their meanings, so that various meanings can be expressed concisely. Framed area - Instruction bit pattern The instruction bit pattern indicates the positions of operand fields and size specification fields, instruction opcodes, etc. The bits marked ``*'' are don't care bits.
It is a cut. This bit 071 is used for instruction decoding.
It does not affect. 1- j , + +T , j =+ , ) #
The bit indicated by t currently has no instruction function or operation.
This bit is not used to distinguish between lands. However, in the user program, ξ9. ':' part is O, + 49, j #
You must put l in the 9 part. If the bit '-9 is not O or the bit '+2 is
If it is not 1, a reserved instruction exception (RFE) occurs. ′:′ bit is not 0 or 2#ゝ bit is 1
If not, it is simply ignored. In other words, in terms of hardware, l*j, ′;l, l#2 are the same.
It has the meaning of However, for future expansion, the user
In the manual for
must be clearly stated. 11-3. - In addition to the operand field, the instruction bit pattern includes an option field and a size specification field. The option field names and size specification field names used in the device of the present invention include the following.・Size specification field name RR Size specification of the operand that performs read access WW Specifies the size of the operand that performs write access
size specified MM read-modify-write access
8B Memory access size for bit manipulation instructions XX General size specification other than the above, especially when specifying register size SS General size specification other than the above Displacement size, CMP size Used for two operands, string instructions that implicitly specify an operand, MOVA:U instructions that implicitly specify a stub, etc. Always repeat the same character (uppercase). However, if you can only specify 32 bits and 64 bits,
If so, use only the - character. - Option field name Lowercase letters are mainly used for the names of option bits that specify instruction options. (Excluding P-bit related) Option field names include the following. In either case, the one written first (the one with an option value of 0.00.) is the one written by the assembler.
default. cccc Bcc, condition specification in TRAP/cc e
eee Termination with string instruction, QSCII instruction
Condition specification P, Q, P bit specification (Q9. is P bit specification
(If multiple operands are required) b /F=0. /B=1 (BSCH, BVSC
)I. BVMAP, BVCPY, SCMP, 5M0V. ascH) r /F=O, /R=1 (SSCH)c
/N=0. /S=1 (C)l)-CHK. 'C2d of change 1ndex value
10=O, /1=1 (BSCH, BVSC)I)
--data ldj m /NM=O, /MR=1 (QSCI()
--mask 1m1 p /AS=O, /5S=1 (PTLB, PS
T.L.B. LDATE) --PTLB, 5Specific
5pace jpj ttt /PT=000. /5T=OO1,/AT
=110°/reserved=010~101,11
1 (PSTLB, LDATE, 5TATE)xx
/LS=OO, /C3=01 reserved=
=10.11 (LDCTX, 5TCTX) or more items
Field names that do not apply to the field name indicate the operand field name. As much as possible, we try to avoid using the same character to have multiple meanings. 11-4. Open'−R' The characters representing operand field names have the following meanings. Since operand field names are composed of a combination of these characters, information such as available addressing modes, operand sizes, and access methods can be obtained from the field name alone.・Basic addressing mode Ea 8-bit single-ship addressing mode is used.
Uses Sh 6-bit abbreviated addressing mode.
# Literal old Immediate #d Displacement Rg Register Ll Register list (for LDM) Ls Register
Star list (for 57M) Ln Register list (E
(for NTER) and X Register list (for EXITD)
- Access method In some basic addressing modes, the following access method is determined as the default. In this case, no special characters indicating the access method are added. #, #i, #d readLs, L from instruction space
n register read I, Lx register
For star access and other basic addressing modes, the following characters are used to indicate the access method. Rread W write M read-modify-write
To shorten the field names, change RgRftRR to RgRft, RgM to R
May be abbreviated to M. (OF instruction, C5I instruction) A Only address calculation is performed. The memory address at which the actual operation is performed is determined by the combination with the f bit offset. (R2M suffix) Example: Two-bit manipulation instruction fq A bit offset is attached, but the bit offset is
does not cross byte boundaries. The address to be accessed is determined without looking at the offset. (R, H suffix) Example: Shortened bit operation table command bf Combination with bit offset and bit field width
The memory address and range to actually perform the operation are determined by the combination. (R, M suffix) Example: Fixed-length bit field manipulation instruction q Performs complex access using a queue instruction. (Suffix for other access methods) Example: QINS, QDEL instruction i Performs access by interlocking the bus. (M suffix) χ Accesses special spaces such as control space and physical space. (R, W, M suffix) d Perform operations on two data (double)
Now. (Suffix of R) Example: CHK instruction li for multiple data
Perform the operation. (R, W suffix) Example: LDM, 57M instruction/Restrictions on addressing mode Once the basic addressing mode and access method are determined, restrictions on addressing mode (imide
etc.) is determined. However, if there are any other restrictions specific to the command, add the following characters at the end. ! 1 Example of prohibition of immediate mode: Second operand of CMP instruction! Examples of prohibited memory object addressing modes: ENTER: local operand of G instruction! A Prohibited example of append mode: ctxaddr operand of LDCTX instruction! S Example of prohibition of stack pop and stack bush modes: QDEL instruction dest operand size specification Size specification is, in principle, performed using the fields shown below. The access method is R RR field access method 4 field access methods are RlI, R1 gate, R25S field access method is *f B8 field However, this means the access size of memory operation. Access method is A. Size is not specified. If there are any exceptions to this, they will be distinguished by adding the following characters. As a general rule, numbers and lowercase letters represent fixed sizes, and uppercase letters represent variable sizes. For example, 'l is 32 bits (word)
While it indicates a fixed size, 'V indicates that resizing is specified by four fields. W Operand size is always 32 bits Example: MUL: R instruction h Operand size is always 16 bits Example: I/AIT instruction b Operand size is always 8 bits Example: MOV: 5rc of E instruction S8 Operand (displacement) size
is specified by the SS field. However, this operand specification field is only used when 5S=OO (8 bit specification).
Ru. Otherwise, the operand is specified by the extension and this field is ignored. (Must be set to 0) Example: The size of the 5rc S operand (displacement) of the BF:l instruction is specified by the SS field. Example: BRA:G instruction R operand size is specified by the RR field in common with the size of the other operand. Example: CMP:l instruction The operand size is specified by four fields in common with the size of the other operand. Example: MOV: l instruction The operand size and the size of the other operand are specified by the interval field. Example: :1 format instruction Since no bit pattern has been assigned to specify 8 bits or 16 bits as the operand size, only 32 bits or 64 bits can be specified. The size specification is not the RR, 4, MM, BB fields, but the R, M, and SI fields.
, B field. Since the P pointer is handled, the size is not specified in the instruction. The actual size is specified by the P bit or mode (XA bit in PS). Example: QINS, QDEL instruction × Operand size is specified from the x×X field
be done. Example: Ace, SCB instruction xreg Xw operand size is determined by X field.
Specified in common with the operand. This is for specifying Wi6th of the BF instruction. Xs The operand size is determined by the X field.
Specified in common with the operand. This is for specifying src of the BF instruction. Xd The operand size is determined by the X field.
Specified in common with the operand. This is for specifying dest of the BF instruction. The C operand size is specified in common with other operands by the RR field. This is for specifying the comparison value of the CSI instruction. 3 3-bit literal 4 4-bit literal example: TRAPA instruction 6 6-bit literal 8 8-bit displacement example: BRA: 8 instructions 1616-bit displacement example: MOVA: R instruction In addition, advanced functions such as string instructions In an instruction, SS is used as a field name to specify the size of an operand implicitly specified by the instruction. X is also used in arbitrary length bit field instructions.・Other 2 Indicates a literal case in which 0 in the bit pattern corresponds to 0 (zer.) in the operand value. The correspondence between bit patterns and operand values is as follows. (N is the number of literal pits) o,,,ooo. O,,,OOl 1 0,,. 010 2 1,,. 110 2=N-2 1, , 1112"N-1 Example: In the offset n literal of BTST:Q, the case where 0 of the bit pattern corresponds to 2"N of the operand value is shown. The correspondence between bit patterns and operand values is as follows. (N is the number of literal bits) 0, . 000 2"N o,,,ooi i O,,,0102 1,,,1102-N-2 !,,,111 2"N-1 Example: In the 5rc C literal of MOV:Q, the bit pattern is 2. Indicates the case where the complement is expressed.
vinegar. The correspondence between bit patterns and operand values is as follows. (H is the number of literal bits) 0, . 000-2=N. 0,,. 001 -(2~N-1) 0,,. 010 −(2°N−2) 1,,. 110 -2 1,,. 111-1 Example: Shift for right shift with SHA:C, SHL:C
Tokalant 1.2. ,, have the same access method within one instruction.
Used to distinguish between multiple operands. Note that among the various size-related restrictions, those that have a significant relationship with the instruction function are indicated in the description of each instruction, rather than in the operand field name or size specification field name. This includes cases where a size other than 8 bits is specified in the shift count, logical operations between different sizes, etc. Among the operand field names, there are restrictions on the addressing modes that can be used for the following: EaR, ShR @-5P cannot be used. Ea, She, #imm-data, @SP+ are not available. EaM, ShM #imm-data, @-5P, @SP+ cannot be used.
stomach. aA @SP+, @-5P, Rn, #imm-data are available
Can not. In addition, restrictions regarding addressing modes are also stated in the explanation of each instruction. 11-6.・5. In the stack operation command, the top of the stack is moved by TO5.
It shows. ↑TO5 is a pop from the stack, ↓TO5 is a block to the stack.
It's Tsushu. 2-operand basic instructions (MOV, MOVU. ADD, ADDU, ADDX, Sue, 5UBU, 5U
BX, AND. OR, XOR, CMP, CMPU)
The Act explains its operation. The size (number of bits) of dest (src2) is d, 5
The size (number of bits) of rc(srcl) is represented by S,
5rc (srcl), dest (src2) for bits
The solved value is 00,01. ,,Dd-1,50,Sl,
, , 5s-1. Therefore, dest(src2) = CDO, Dl, . Dd-2, Dd-1 5rc (srcl) = [SO, Sl, . 5s-2, 5s-1]. [1, ko means binary representation, ′, ′ means the separator of each digit. At this time, the value set to dest according to the calculation result is dest, op, src = result = [
RO, R1, , Rd-2, Rd-1]. M
For commands other than OV, MOVU, CMP, and CMPU, r
esu+t is set to dest. Also sad
In this case, generally only the lower pit of the calculation result is set to dest. At this time, the value before cutting the upper bits of the operation result is result = [FO, Fl, . Fs-2, Fs-1]. The number of bits of R is dSF and the number of bits of S is S. In addition, in the explanation of the fixed-length bit field instruction, bitfield = [Bo, Bo+1. ,,. Bo+w-2, Bo+w-1] Detailed bit-by-bit operations are explained using notations such as Bo+w-2, Bo+w-1]. As an abbreviation, [Sn, Sn+t, . Sm-2,5m-1] [Represented by Sn~m-11, [SO, Sl, . 5d-2, 5d-1=[SO~S-1] may be simply expressed as [S]. [:D], [:Rco, [8]. The same applies to [F]. 12, r II mouth Δsera 12-1. ---"口Δ [Mnemonic] MOV src, dest [Instruction function] src ==> dest Data movement and sign extension [Instruction options] None [Instruction bit pattern and assembler notation] Figure 44 (a
). [Flag change] Shown in FIG. 44(b). [Explanation] Source operand src is used as destination operand
transfer to dest. The size of the source operand is the size of the destination operand.
source is sign-extended.
Ru. Destination is smaller in size and source value
is expressed as a signed integer of the size of the destination.
If it cannot be displayed, VJlag is set. MOV: Z is a so-called clear instruction, but it is
Since the works and flag changes are the same, it is one of the abbreviated forms of NOV.
It is treated as one. MOV, ADD, MOV, and CMP instructions are signed operations.
These are instructions that perform calculations, but MOV:Q, ADD:Q, S
The range of literals that can be used in ue:Q and CMP:Q is 1.
~8 (operand field name #3n),
Care must be taken as it only includes positive ranges. M
src is an immediate value in OV and MOVU instructions
its immediate value and available formats.
The relationship between the two can be summarized as follows. [:MOV] :Z 5rc=:0 :Q 1≦src≦8 :E −128≦src≦127 :l src is arbitrary: G src is arbitrary [MOVU] 2E O≦src≦255 :G src is arbitrary The same applies to ADD, Sue, and CMP instructions. (When d≧S) [50, Sl,..., 5s-2, 5s-1 ==>[
5O1so, ,,,,,,,so. SO, Sl,..., 5s-2, 5s-1 ==>d-
Sign extension by s bits (:RO, R1, , , Rd-s+1.Rd-s, R
d-s+1. ,,,Rd-2゜Rd-1 (to dest
set) (at the time of DOS) [SO, Sl,,,,5s-d-1,5s-d. 5s-d+1. ,,． 5s-2, 5s-1] ==>[
:5s-d, 5s-d+1. ,,． 5s-2゜5s-1
] ==> SO, Sl, , , 5s-d-1 s-d bits are cut. [RO, R1, Rd-2, Rd-1] (set to dest) MJIag RO ZJIag [RO~d-1co = 0VJl
ag☆S[:Sl<-2°(d-1), or. SCS co ≧ +2° (d-1) In other words, if d≧S, it is cleared, and if d<s, So = Sl, 1. , = : 5s-d
Clear when -1 = 5s-d(:RO), otherwise
It becomes a set if [Program exceptions] - Reserved instruction exception - When RR = 'll' - When - = 'll' - When EaR and ShR are @-5P - EaW, Sh1#imm-data,, @SP+
[Mnemonic] MOVU src, dest [Instruction function] zex (src) ==> dest Data movement and zero extension [Instruction options] None [Instruction bit pattern and assembler notation] Shown in Figure 45
vinegar. [Flag change] Shown in Figure 46. [Explanation] Source operand src is used as destination operand
transfer to dest. The size of the source operand is the size of the destination operand.
source is zero-extended.
Ru. Destination is smaller in size and source value
is expressed as an unsigned integer of the size of the destination.
If it cannot be displayed, VJlag is set. (When d≧S) [SO, Sl, , 5s-2, 5s-1] ”>[0
,O,,,,,,,,,O,So,Sl,,,
, 5s-2°5s-1] ==> Zero extension by d-s bits [RO, R1, , , Rd-s+1. Rd-s, Rd
-s+1. ,,,Rd-2゜Rd-1 (at the dest
set) (when d<s) [SO, Sl, , , 5s-d-1, 5s-d, 5s
-d+1. ,,． 5s-2゜5s-1 ==> [5s-d, 5s-d+1. ,,． 5s-2゜5s-1
] ==> SO, Sl, , , , 5s-d-1 s-d bits are cut. [RO, R1, Rd-2, Rd-1 (set to dest) MJIag RO Zjlag [RO~d-11= OVjlag
☆ U [S co ≧ +2°d, that is, d≧S
If it is DOS, it is cleared, and if it is DOS, then 50 = 51 =,,,,, =Ss-d-1 = 0
Cleared when , set otherwise. [Program exception] - Reserved instruction exception - When RR = 'll' - When Wen = 'll' - When EaR is @-5P When φEaW is #imm-data, @SP0 [Nemo
Nick] PUSfl src [Instruction function] push to 5tack Push to stack [Instruction options] None [Instruction bit pattern and assembler notation] Shown in Figure 47
vinegar. [Flag change] Shown in Figure 48. [Explanation] Pushes the source operand src onto the stack. This command can be thought of as an abbreviation for MOVne, @-5P.
However, the flag must not change and the POP
Due to symmetry with src/EaRL, it becomes a separate command.
In the addressing mode specified by
The code cannot be used. This is the POP instruction dest/
In line with the fact that @-5P mode cannot be used with EaWL.
It is something that Pu5) l Includes SP in the src operand, such as SP.
Please refer to Appendix 12 for the instruction operation rules in this case.
. [Program exception] - Reserved instruction exception - R = '1. 'When EaRL is @SP+, @-SP [Mnemonic] POP dest [Instruction function] pop from 5tack Pop from stack [Instruction options] None [Instruction bit pattern and assembler notation] Shown in Figure 49
vinegar. [Flag change] Shown in Figure 50. [Explanation] Transfers the value popped from the stack to dest. This command is considered an abbreviation of MOV @SP+, *
However, the operation when SP is included in src is M
It is different from OV @SP 10, and the flag changes.
There is no such thing as a different instruction. Addressing mode specified by dest/EaWL
Therefore, it is prohibited to use the @-5P mode.
If specified, a reserved instruction exception RIE occurs. this
is, when the instruction POP @-5P is executed, S
Misunderstandings regarding when P updates occur
This is because it is easy. pop sp, if the dest operand includes SP.
Please refer to Appendix 12 for the operation rules of the instruction when
. [Program exception] - Reserved instruction exception - When W = 'l' - EaWL is #imm-data, @SP+, @-5P
When [Mnemonic] LDM src, reglist [Instruction function] 1 load multiρle registers multiple
Load register [Instruction option] None [Instruction bit pattern and assembler notation] Shown in Figure 51
vinegar. [Flag change] Shown in Figure 52. [Explanation] Load multiple registers from memory. The record to load
Register is Bitmap regl ist/LIRL (
, register list). LIRL is EaRm
It is placed after the extension of L. Bits of the register list (regl 1st) to be loaded
Tomap designation is performed as shown in FIG. When specifying the addressing mode of @SP10 in EaR ridge
If so, the registers with the lowest number are popped and the
increases by 4 times (or 8 times) the number of loaded registers
do. When specifying another addressing mode
is the method by which the obtained effective address should be loaded into the register.
Points to the beginning of the memory data. In either case, in memory
Then the register with the lower number is placed at the lower address.
Ru. The format of the bitmap of the register to be loaded is:
Used with BSC) I/F, BVSC) I/F instructions
circuit (MS bit of 20' or l' that appears next)
The next search is performed using the same circuit as the circuit searched in the B direction.
It was decided so that the register to be sent can be found.
. Therefore, in the case of LDM @SP+, a small number
To transfer from a register, the one with the smaller register number
It's on the MSB side. Other addressing modes
In the case of a code, the start address of the register save block is
Since it is an effective address, the lower register number is also used.
It is best to transfer from the smallest side, same as LDM @SP+
format. Note that these formats are limited to the register transfer order.
This is a well-thought-out decision, and is recommended when hardware resources are scarce.
The transfer order described here is best when
it is conceivable that. However, the actual transfer order is
It is not specified by the
That's why. In EaRmL addressing mode, @-5P,
Register direct mode Rn, immediate mode
#imm-data, addition mode specification is illegal
do. Prohibiting additional modes is due to LDM and STM.
The registers and register save area that were saved and restored,
Overflow between registers and memory used in append mode
This makes it difficult to re-execute instructions if there is a lap.
If the register list is all 00, execute the command without doing anything.
end. (This is not considered an error in particular) LDM @S
Operation rules when SP is included in the register list for P+
Please refer to Appendix 12 for details. [Program exception] - Reserved instruction exception - When R = 'l' - EaRmL is Rn, #imm-data, @-5P,
When in addition mode [Mnemonic] STM reglist, dest [Instruction function] 5tore multiple registers
Store number register [Instruction option] None [Instruction bit pattern and assembler notation] Shown in Figure 54
vinegar. [Flag change] Shown in Figure 55. [Explanation] Save multiple registers in memory. Cash register to save
The star is bitmap regl ist/LsWL (register).
Specify in starlist). LsWL is the expansion of EaWmL.
It is placed after Haribe. Bits of register list (regl 1st) to store
When EaWmL is in @-5P mode, the topmap specification is
As shown in Fig. 56, in other modes, the 57th
Do as shown. Specify @-5P addressing mode for EaWmL.
, the registers with the highest number are
, SP is 4 times (or 8 times) the number of saved registers.
decreases. Specify another addressing mode.
, the resulting effective address saves the register.
Points to the beginning of the desired memory area. In either case, note
During storage, registers with lower numbers are placed at lower addresses.
It will be destroyed. This format is BSCI (/F, BVSCH/
The circuit used in the F instruction (the next '0' or 'l'
’ bit in the MSB direction)
so that you can find the next register to transfer by
It was decided. Therefore, when STM @-5P
is the register number to transfer from the higher numbered register.
The larger number is the MSB side. Other addresses
In the saving mode, the first address of the register save block is
Since the address is the effective address, the register number
It is best to transfer from the smallest register number.
The vise is on the fMsB side. Note that these formats are limited to the register transfer order.
This is a well-thought-out decision, and is recommended when hardware resources are scarce.
The transfer order described here is best when
it is conceivable that. However, the actual transfer order is
It is not specified by the
That's why. [:aWmL addressing mode, @SP+,
Register direct mode Rn, immediate mode #im
The designation of m-data and addition mode is illegal. Prohibiting the additional mode is due to evacuation by LDM or S resistance.
, restored registers, register save area, and additional modes.
There is overlap between the registers and memory used in the
This is because if there is a problem, it will be difficult to re-execute the instruction. In the DM and STM instructions, registers that are not transferred are
Do not allocate memory area for For example, STM, W
(R1, R3, R9), @-5P as follows
Perform the action. (However, if the SP value before instruction execution is i
Let it be n it SP. )R9==> mem[1n
itsP -4koR3==> mem[1nitSP
−8] R1==> mem[1nitsP −1
2 pieces 1 nitsP -12==> SP When the register list is all O, the instruction ends without doing anything.
Complete. (Not considered an error) STM @-SP
Regarding the operation regulations when SP is included in the register list in
Please refer to Appendix 12 for details. [Program exception] - Reserved instruction exception - When -='1' - EaWmL is Rn, #imm-data, @SP+,
When in addition mode [Mnemonic] MOVA 5rcacldr, dest [Command machine]
] address of src ==> dest effective
Obtain address [Instruction options] None [Instruction bit pattern and assembler notation] Shown in Figure 58
vinegar. [Flag change] Shown in Figure 59. [Explanation] Destination as effective address of source operand
Transfer to operand. The operation of this instruction itself is the MOV instruction, etc.
can be substituted by
Address
Because it uses a calculation circuit, faster calculations can be expected.
This is a separate instruction depending on the situation. The abbreviation MOVA:R@(disp:16.Rs), Rd is the actual
Qualitatively, it is a 3-operand addition instruction Rs + disp:16->Rd, but since it does not cause a flag change, it can be used as a MOVA instruction.
Classified. Specify PC relative indirect mode for 5rcaddr, and
If the displacement of the pair is 0, the current
dest the PC value, that is, the start address of the MOVA instruction.
It will be stored in. Also, the display relative to the PC
When specifying the instruction length of the MOVA instruction as a statement
stores the address of the next instruction after the MOVA instruction in dest.
I will pay it. These functions are implemented at the user program level.
This is effective when performing online processing. In assembler, operation> or dest side
Specify the size with . 5rcaddr side is address meter
Since it is only a calculation, the size is not specified. In the addressing mode specified by EaA, the imide
Modes such as ieate, @SP+, and @-5P cannot be used.
do not have. [Program exception] - Reserved instruction exception - When +:20' - When W = 'l' - EaA is Rn, #imm-data, @SP+, @-
When 5P・Eaw is #imm-data, @SP10
[Mnemonic] Pu5) IA 5rcaddr [Instruction function] push address to 5tack - effective address
Push the address onto the stack [Instruction options] None [Instruction bit pattern and assembler notation] Shown in Figure 60
vinegar. [Flag change] Shown in FIG. 61. [Explanation] The effective address of source operand 5rcaddr is
Shout out to the listener. This command is a short form of MOVA *, l1l-5P and
I can think of ways to improve execution speed or use the MOV command.
~In order to correspond to the distinction between PUSH commands, different commands and
There is a lot of trouble. For operation regulations when SP is included in SrC, see the appendix.
See 12. [Program exception] - Reserved instruction exception - When S = 'l' - EaA is Rn, #imm-data, @SP+, @-
12-2 when 5P. , − mouth Δ[d
Monic] CMP 5rcl, s'rc2 [Instruction function] 5rc2-5rcl, flags affected
Comparison, sign extension and comparison [Instruction options] None [Instruction bit pattern and assembler notation] Shown in Figure 62
vinegar. [Flag change] Shown in Figure 63. [Explanation] Compare the 5rcl operand with the src2 operand,
Based on the results, PSB (LJIag, Z-flag)
set. The size of the 5rcl operand and the support of the 5rc2 operand.
When the sizes are different, the operand with the smaller size is
The numbers are expanded and compared. In addition, in the mode of EaRl l and 5hR1I, imide
Eating is prohibited, but O5P+ is possible. CMP @SP+, @SP 10, stack point
The data changes by twice the operand size, compared to other instructions.
Although it is anomalous when compared to
It may be used when simulating. CMP:Z has so-called tes as a command, but it also has actions and
Since the flag changes are the same, it is a shortened form of CMP.
It is treated as such. In the following, 5rcl = [:SO,Sl,,,,5s-2
,5s-1ko5rc2 = [DO, Dl, ,,,D
d-2,0d-1] to explain the operation.
. (When d≧S) [DO, Dl, , , Dd-s-1, Dd-s, Dd
-s+1. ,,,Dd-2゜0d-1co - [SO,SO, ,,,,,,,SO,So,S
l, , , 5s-2゜5s-1] ==> Sign extension by ds bits [:RO, R1, , , Rd-s-1, Rd-s, R
d-s+1. ,,,Rd-2゜Rd-1 (not installed anywhere)
(not determined) (when d<s) [DO, DO, , , , , , , DO, DO, Dl, ,
,, Dd-2゜Dd-1 code - sign extended by s-d bits [SO, Sl, ,,, 5s-d-1, 5s-d, 5s
-d+1 ,,,. 5s-2゜5s-1] ==> [FO, Fl, , , , Fs-d-1, Fs-d, F
s-d+1. ,,,Fs-2゜Fs-11 (not installed anywhere)
not determined) LJIag☆ S[D co < S[S]SUB order
ZJlag [:RO~d-1] = 0 (d≧S
) ☆ [FO ~ s-1 code = 0 (at the time of DOS) [Program exception] - Reserved instruction exception When φRR = 'll' When φ5S = jll' - Conflict when EaR and ShR are @-5P EaR11,5hR1I is # imm-data, l
i! -5P [Mnemonic] CMPU 5rcl, 5rc2 [Instruction function] 5rc2- srd, flags affected
Compare with zero extension [Instruction options] None [Instruction bit pattern and assembler notation] Shown in Figure 64
vinegar. [Flag change] Shown in FIG. 65. [Explanation] Compare the 5rcl operand with the 5rc2 operand,
Based on the results, PSB (LJIag, Z-flag)
set. src! Operand size and 5rc2 operand support
If the sizes are different, the operand with the smaller size
It will be expanded and compared. Immediate is prohibited in EaRII mode.
However, @SP+ is possible. In the following, 5rcl = [SO, Sl, , , 5s-2, 5s-
1]5rc2 = [DO, Dl, , , Dd-
2, the operation will be explained by Dd-11. (When d≧S) [DO, Dl, , , Dd-s-1, Dd-s, Dd
-s+1. ,,,Dd-2゜0d-1] - C0,0,,,,,,,,,,OSO,Sl,,,,
5s-2゜5s-1 ko ==> Zero extension by ds bits [RO, R1, , , Rd-s-1, Rd-s, Rd
-s+1. ,,,Rd-2゜Rd-1] (Nowhere set
(undefined) (when d<s) [0, O, , , , , , , 0, Do, Dl,
,. , Dd-2゜0d-1] - Zero-extended by 5-d bits [50, Sl, , , 5s-d-1, 5s-d, 5
s-d+1. ,,． 5s-2゜5s-1] ==> [:FO, Fl, ,,, Fs-d-1, Fs-d, F
s-d+1. ,,,Fs-2゜Fs-11 (not installed anywhere)
not determined) LJIag☆ U[D co < U[S co5ueu
Same as instruction ZJIag [RO~d-11=0 (when d≧S
) ☆ CFO~s-1] 20 (when d<s) [Program exception] - Reserved instruction exception - When RR = 211' - When SS = 'll' - When EaR is @-5P - EaRll When is #imm-data, @-5P [
Mnemonic] CIl bound, +ndex, xreg [
Function of command: check upper and lower bou
Check the range of nds array [Instruction option] /S Subtract the lower limit IN Do not subtract the lower limit (default) [Instruction bit
Pattern and assembler notation] Shown in Figure 66. [Flag change] Shown in FIG. 67. [Explanation] Checking the array index range and loading into the register
Do the following. The address pointed to by bound has an upper limit value and a lower limit value.
The upper limit value, lower limit value and 1ndex
The comparison value operands fetched by are compared. The upper limit value is placed at the effective address of bound.
Yes, (effective address of bound + operand size)
The lower limit value is placed at the address of comparison
is performed as a signed integer. Comparison value is lower than upper limit value
If it is not between the limit values, VJlag is set.
Therefore, by successively executing the TRAP instruction,
, can trigger exception handling. If /S is specified, the comparison value minus the lower limit value is
Loaded into register xreg. If /S is not specified,
If so, the comparison value is loaded as is into register xreg.
. The next step in writing the comparison value into a register is to store it in an array.
This is because it is often used to calculate the address of the index.
Ru. Operation: tip = mem[address-of-boun
d+operancjsize] if (index ≧ mem[address
-of-bound], or, 1ndex < tm
p) hen set 'Jflag; if (A == 1) hen index -tmp ==> xreg1se index ==> xreg However, 'address-of-' is 'mem[,,
]' is the inverse operator of bound and mem[addr
ess-of-bound] has the same meaning. The lower limit is considered in-range if the values match, while the upper limit is considered out-of-range if the values match. For example, the bound memory is (0°100)
, then C) IK is within the range of inde
This is the case where x is O~99. -flag, ZJlag are the lower limit value and index
It is set in the same way as CMP according to the comparison result with
However, -flag=1 when index <lower limit value. In other words, as shown in Fig. 68, ■ Upper limit value (In case of lower limit value, l
Sometimes it becomes. In this case, the flag is calculated based on the calculation result of 1ndex - lower limit value.
will be set. The following three commands are all
The second operand is the first operand (in CHK, the first operand is
LJl when smaller than the lower limit of Pellend bound)
The specification is that ag is set. CMP 5rcl, 5rc2 SLJB src, dest CHK bound, 1ndex, xregCH
The command does not particularly check whether the upper limit value ≧ the lower limit value.
. Regardless of the size of the upper and lower limits,
The operation shall be equivalent to that written in the
. In the addressing mode specified by EaRdR,
Register Direct Rn, ('SP, li!SP+, #
imm-data mode cannot be used. no matter what
If you want to compare with the value in the register, instead of CHK, use
It is sufficient to perform CMP twice. [Program exception] - Reserved instruction exception - When RR = 'll' - When EaR is @-SP - EaRdR is Rn, # i mm -data
, @SP+, @-5P 12-3.
'7+, Δ [Mnemonic] ADD src, dest [Instruction function] dest + src ==> dest addition, sign extension
Expansion and addition [Instruction options] None [Instruction bit pattern and assembler notation] Shown in Figure 69
vinegar. [Flag change] Shown in Figure 70. [Explanation] Adds the source operand to the destination operand.
Calculate. The size of the source operand is the size of the destination operand.
source is sign-extended.
and then added. The destination size is small and the calculation result is
can be expressed as a signed integer of the size of the destination.
If not, VJIag is set. In addition, ADD of L-format: L @SP+, SP
For ADD:G @SP+, same as SP (initSP+4)+@1nitSP==>SP movement.
It is desirable to do some work. However, in implementation,
It is difficult to perform this kind of operation with L-forn+at.
In some cases, ADD:L@SP+, SP
The behavior is implementation dependent. This is S
The same applies to UB:L, CMP:L, and INDEX. More details in the appendix! See 2. (When d≧S) [DO, Dl, , , Dd-s-1, Dd-s, Dd
-s+1. ,,,Dd-2゜Dd-1] + [SO,SO, ,,,,,,,SO,SO,Sl,,
,,5s-2゜5s-1ko ==〉 Sign extension by d-S bits [RO, R1, ,,, Rd-s-1, Rd-s, Rd
-s+1. ,,,Rd-2゜Rd-11 (set at dest)
) (when d<s) [DO, DO, , , , , , , DO, Do, D
l, , , Dd-2゜Dd-1co + s-d bit sign extension ISO, Sl, , , , 5s-d-1, 5s-d, 5
s−d+1,,,. 5s-2゜5s-1 ==〉 [:FO, Fl, ,,,, Fs-d-1, Fs-d, F
s-d+1. ,,,Fs-2゜Fs-1] ==> [: RO,R1,,,,Rd-2゜Rd-1ko(d
est) FO, Fl, , , Fs-d
-1 s-d bit is cut and -flag☆ S[Dl + SOS
0 indicates that the result is negative. (MJlag also indicates the positive or negative of the result, but MJlag is positive
The correct positive and negative values are displayed only when there is no overflow. ) MJIag RO ZJIag [RO~d-1ko = OVjl
ag S [D co + S [S co < -2
-(d-1), or. S[Dl + S[S]≧+2-(d-1)X-fla
g☆ In either case, carry from the size of dest
is set to Xjlag. (When d≧S) U[DO, Dl, , , Dd-s-1, Dd-s. Dd-s+1. ,,,Dd-2,Dd-1] +U[Takuma
, so, , , , , , , so, so. Sl,...,5s-2,5s-1] ≧ +2°dd
- Sign extension by s bits (when d<s) U[DO, Dl, , Dd-2, Dd-1]+U[5
s-d, 5s-d+1,,,. 5s-2, 5s-1 ≧ +2″'dSO,
Sl,,,,,5s-d-1 s-d bit is cut [Program exception] - Reserved instruction exception - When RR = 'll' - When MM = 'll' - εaR, ShRw are @- When 5P - EaM, ShM #imm-data, li! SP+
, @-5P [Mnemonic] ADDU src, dest [Instruction function] dest + src ==> dest zero expansion
and addition [Instruction options] None [Instruction bit pattern and assembler notation] Shown in Figure 71
vinegar. [Flag change] Shown in FIG. 72. [Explanation] Adds the source operand to the destination operand.
Calculate. The size of the source operand is the size of the destination operand.
source is zero-extended.
and then added. The destination size is small and the calculation result is
can be expressed as an unsigned integer of the size of the destination.
If not, VjIag is set. ADDU's L-flag means that the result is positive.
Assume that it is always reset to 0. (When d≧S) [DO, Dl, , , Dd-s-1, Dd-s, Dd
-s+1. ,,,Dd-2゜0d-1ko + [0,O,,,,,,,,0,50,Sl,,,,
5s-2゜5s-1 ko ==> Zero extension by ds bits [RO, R1, , , Rd-s-1, Rd-s, Rd
-s+1. ,,,Rd-2゜Rd-1] (to dest
(set) (when d<s) [0, O, , , , , , , 0, Do, Dl,
,,, Dd-2゜0d-1] + s-d bit 6 naze a extension [:SO, Sl, ,,, 5s-d-1, 5s-d, 5
s-d+1. ,,． 5s-2゜5s-1 ==〉 [FO, Fl, ...,, Fs-d-1, Fs-d, Fs
-d+1. ,, ,Fs-2゜Fs-1ko =:〉 [RO, R1, , , Rd-2゜Rd-1] (Set in dest) FO, Fl, ,
, , Fs-d-1 s-d bits are cut. Ljlag O gate-flag RO ZJIag [RO~d-1co = OV-f
lag U[:Dl + u[sco ≧
+2″dXJIag☆ In either case, the dest
The carry from size is set in XJIag. (When d≧S) U[DO, Dl, , , Dd-s-1, Dd-s, D
d-s+1,,,Dd-2,0d-13+ U[0,Sail,,,,,,,,,O,SO. Sl,,,5s-2,5s-1 ≧ +2″dd-
Same as V-flag of zero-extended ADDU instruction by s bit (when d<s) [DO, Dl , , Dd-2, Dd-1 + U[: 5s-d , 5s-d+ 1, , ,． 5s-2,5s-1]≧+2″dSO,S
l,,,,,5s-d-1 The s-d bit is cut [Program exception] - Reserved instruction exception - When RR = 'll' - When EaR = 'll' - When EaR is @-5P Time・EaMil#imm-data, @SP+, @-SP
When [Mnemonic] ADDX src, dest [Instruction function] dest + src + XJlag ==> de
Addition including st carry [Instruction option] None [Instruction bit pattern and assembler notation] Shown in Figure 73
vinegar. [Flag change] Shown in FIG. 74. [Explanation] Source operand and carry as destination operation
Add to rand. The size of the source operand is the size of the destination operand.
If the size of the source is smaller than the size of the source, the source is sign-extended and then added. ZJlag allows flag values to be accumulated.
Ru. Also, flag changes for ADDX and ADD are sign-extended.
/Almost the same including zero extension. ADD and AD
In DX, only Zjlag has a different flag change.
. Regarding calculations between cumulative sizes of ADDX and 5UBX,
For example, in the 8-byte number dest2~dest1
To add a 4-byte number src, use ADD @src, W, @dest1. WADDX
#0. @dest2. It is sometimes used in the form of W ADDX:E R0.
. (When d≧S) [DO, Dl, , , Dd-s-1, Dd-s, Dd
-s+1. ,,,Dd-2゜0d-1]÷[SO,SO, ,,,,,,,SO,So,
Sl,...,5s-2゜5s-1] + XJIag
==> Sign extension by d-s bits [RO, R1, , , Rd-s-1, Rd-s, Rd
-s+1. ,,,Rd-2゜Rd-1] (to dest
set) (at the time of DOS) [D, DO, , , , , , , DO, DO, Dl, ,,
, Dd-2゜0d-1] + sign extension by s-d bits [SO, Sl, , , 5s-d-1, 5s-d, 5s
-d+1. ,,． 5s-2゜5s-1ko + X-fl
ag ==> [FO, Fl, ,,, Fs-d-1,
Fs-d, Fs-d+1. ,,,Fs-2゜Fs-1]
==> [RO, R1,..., Rd-2°Rd-1] (set to dest) FO, Fl,...
, , Fs-d-t s-d bits are cut. shi-flag☆ S[:Dl + S[:Sl
+ X-flag < 0 Treated as a signed number
Performs an operation using , and the result is negative. In the case of d-I-8, the operand is sign-extended or
are compared. (MJlag also indicates the positive or negative of the result, but if Mjlag is positive
The correct positive and negative values are displayed only when there is no overflow. ) Town flag RO Zjlag [RO~d-1] = O, and,
previousjlag V-flag S[Dl + S[Sl +X-f
lag <-2'''(d-1), or. S[D co + SCS co + XJlag ≧ +2
'(d-1) Indicates that the operation is performed while treating the number as a signed number, and the result overflows. If d≠S, the operand is sign extended. XJlag☆ In either case, from the size of dest
The carry of is set to XJlag. (When d≧S) U[DO, Dl, , , Dd-s-1, 0d-s, D
d-s+1. ,. Dd-2,0d-1] + u[so, so, ,,,,,,,,so, so,
st,,. 5s-2, 5s-1] + X-flag ≧ +2-
Sign extension by dd-s bits In the case of dos, sign extension is performed. This is because the processing is common to the setting of dest and other flags. However, in operations and comparisons after sign extension, the operands are treated as unsigned numbers. (At the time of dos) (ICDo, 01.,,. Dd-2, Dd-1] + U[:5s-d, 5s-d+1, , , . 5s-2, 5s-1] + X-flag≧ +2 -d
SO, Sl,..., 5s-d-1 s-d bit is cut [Program exception] - Reserved instruction exception - When RR = 'll' - When M gate = 'll' - EaR is @ -5P* Ea erection #imm-data, @sP+, @-5P
When [Mnemonic] Sue, src, dest [Instruction function] dest -src ==> dest subtraction, sign extension
and subtraction [Instruction options] None [Instruction bit pattern and assembler notation] Shown in Figure 75
vinegar. [Flag change] Shown in FIG. 76. [Explanation] Source operand from destination operand
reduce The size of the source operand is the size of the destination operand.
source is sign-extended.
is subtracted above. The destination size is small and the operation result is
can be expressed as a signed integer of the size of the destination.
If not, VJlag is set. (When di=s) [DO, Dl, , , Dd-s-1, 0d-s, Dd
-s+1. , , ,Dd-2゜Dd-1] - [SO,SO, ,,,,,,,,SO,SO,Sl,,
,,5s-2゜5s-1] ==> Sign extension by d-s bits [RO, R1, ,,, Rd-s-1, Rd-s, Rd
-s+1. ,, ,Rd-2゜Rd-1 (to dest
(set) (when d<s) [:DO, DO, , , , , , , DO, DO, Dl,
,,, Dd-2゜0d-11- Sign extension by 5-d bits [SQ, Sl, ,,, 5s-d-1, 5s-d, 5s
-d+1. ,,． 5s-2゜5s-1ko :=> (:FO, Fl, ,,, Fs-d-1, Fs-d, F
s, -d+1. ,,, Fs-2゜Fs-1 ==) [RO, R1, ,, Rd-2゜Rd-1 (set to dest) FO, Fl, ,,,, Fs-d-1 The s-d bits are cut. LJIag☆ s[o]-s[s] < 0 result is negative
represents something that will become. (MJIag also indicates the positive or negative of the result, but MJIag is positive
The correct positive and negative values are displayed only when there is no overflow. ) Town flag RO ZJlag [RO~d-1] :OVjlag
S[Dco − S[Sl < −2−(
d-1), Or. S[D co - S[S co ≧ +2-(d-1)Xjl
a,! i☆ In either case, from the size of dest
The undercarriage is set to Xjlag. (When d≧S) U[DO, Dl, , , Dd-s-1, 0d-s, D
d-s+1,,,,Dd-2,0d-1] - U[SO,SO,,,,,,,,,SO,So,
Sl,...,5s-2,5s-1k 0d-s bit
code extension (dose) uc oo, oi , , Dd-2, 0d-1 code - U[:5s-d, 5s-d+1 , , . 5s-2,5s-1k O20,Sl,,
,,,5s-d-1 s-d bit is cut [Program exception] - Reserved instruction exception - When RR = 'll' When φ = 'll' - When EaR and ShRw are @-5P・EaM, ShM are #imm-data, @SP+, @
-5P [Mnemonic] 5UBU src, dest [Instruction function] dest -src ==> dest Zero extension and subtraction [Instruction options] None [Instruction bit pattern and assembler notation] Shown in Figure 77
vinegar. [Flag change] Shown in FIG. 78. [Explanation] Source operand from destination operand
reduce The size of the source operand is the size of the destination operand.
source is zero-extended.
and then subtracted. The destination size is small and the calculation result is
can be expressed as an unsigned integer of the size of the destination.
If not, Vjlag is set. (When d≧S) [DO, Dl, , , , Dd-s-1, Dd-s
, Dd-s+1 , , , Dd-2゜Dd-1
- [0,0,,,,,,,,,O,So,Sl,
,,,5s-2゜5s-11==> Zero extension by d-s bits [RO, R1, ,,, Rd-s-1, Rd-s, Rd
-s+1. ,,,Rd-2゜Rd-11 (set at dest)
(defined) (at the time of dos) [0, 0, , , , , , , O, Do, Dl,
,,, Dd-2゜0d-11- Zero extension by 5-d bits [SO, Sl, ,,, 5s-d-1, 5s-d, 5s
-d+1. ,,． 5s-2゜5s-1] ==> [FO, Fl, ,,, Fs-d-1, Fs-d, Fs
-d+1. ,,,Fs-2°Fs-1] ==> [RO,R1,,,Rd-2°Rd-tl (set to dest) FO,Fl,,
, , Fs-d-1 s-d bits are cut. LJIag☆ U[D] -U[Skoku O-tie
This means that the result is negative. (Lflag also represents the positive or negative result, but Mjlag is positive
The correct positive and negative values are displayed only when there is no overflow. ) Gate-flag RO ZJlag [:RO-d-1] = OVJIa
g U [D - U [S] 0sue
Xjlag same as L-flag of u instruction☆ In either case, from the size of dest
The undercarriage of is set to Xjlag. (When d≧S) U[DO, DI , , , , Dd-s-1, 0d
-s, Dd-s+1, , Dd-2, 0d-1]
- U[0,Sail,,,,,,,,O,So,Sl,
,,5s-2,5s-1 0 d-s bits zero-extended SUB instruction's Xjlag, 5UBU instruction's LJIag
, Same as V-flag (when d<s) U[DO, Dl, , Dd-2,0d-1] -U[
:5s-d, 5s-d+1,,,. 5s-2, 5s-11< O 20, Sl,..., 5s-d-1 s-d bit is cut [Program exception] - Reserved instruction exception - When RR = 'll', φ =' When ll' - When EaR is @-SP - EaM is #imm-data, 1ilsP+, @-5
When P [Mnemonic] 5UBX src, dest [Instruction function] dest -src -XJIag ==> dest
Subtraction including carry [Instruction options] None [Instruction bit pattern and assembler notation] Shown in Figure 79
vinegar. [Flag change] Shown in Figure 80. [Explanation] Source operand and carry as destination operation
Subtract from rand. The size of the source operand is the size of the destination operand.
source is sign-extended.
and then subtracted. ZJIag allows flag values to be accumulated.
. Also, flag changes for 5uBX and SUB are code extension/
They are almost the same, including zero extension. SUB and 5UB
The only difference in flag change in X is Zflag. (When d≧S) [DO, Dl, , , Dd-s-1, 0d-s, Dd
-s+1. ,, ,Dd-2゜0d-1] - [SO,SO, ,,,,,,,SO,So, S
l,,,5S-2゜5s-1] -X-flag =
=> Sign extension by d-s bits [RO, R1, , , Rd-s-1, Rd-s, Rd
-s+1. ,,,Rd-2゜Rd-1] (to dest
set) (when d<s) [DO, DO, , , , , , , DO, DO, Dl, ,
,,Dd-2゜Dd-1] - sign extended ISO by 5-d bits, Sl, , , 5s-d-1, 5s-d, 5s
-d+1. ,,． 5s-2゜5s-1] -X-fla
g ==> [FO, Fl, , , , Fs-d-1, Fs-
d, Fs-d+1 , , , , Fs-2°Fs-1
] ==> [RO, R1,..., Rd-2°Rd-1] (set to dest) FO, Fl,...
, , Fs-d-1 s-d bits are cut. LJIag☆ S[Dl-,5ESE-X-fla
g < 0 Indicates that the operation is performed treating the number as a signed number, and the result is negative. In the case of dos, the operands are sign-extended and then compared. (Mjlag also indicates the positive or negative of the result, but if the town flag is positive
The correct positive and negative values are displayed only when there is no overflow. ) 1-flag RO Zjlag [:RO~d-1] = 0, an
d, previousjlag VJIag S[Dl-5[S-X-
flag <-2-(d-1), or. S[Dl -S[51-X-flag≧+2-(d sign
This indicates that the result will overflow when the operation is performed on the number. If d≠S, the operand is sign extended. Ru. (When d≧S) U[DO, Dl, , , Dd-s-1, 0d-s, D
d-s+1,,,,Dd-2,Dd-1co-υ[SO,SO,,,,,,,,SO,So,
51,,,. 5s-2, 5s-11-XJIag <
Sign extension by 0d-s bits In the case of dos, sign extension is performed. This is because the processing is common to the setting of dest and other flags. However, in operations and comparisons after sign extension, the operands are treated as unsigned numbers. (At the time of dos) U [Do, Dl, , Dd-2, Dd-1
Co-U [5s-d, 5s-d+1 , , . 5s-2, 5s-1] -X-flag <
050.51. ,,,． 5s-d-1 S controller bit is cut [Program exception] - Reserved instruction exception - When RR = 'll' - When MM = 'll' 11 When EaR is @-5P * EaM is # imm-data , @SP+, Ii!
-5P [Mnemonic] MUL src, dest [Instruction function] dest * src ==> dest multiplication [Instruction options] None [Instruction bit pattern and assembler notation] Shown in Figure 81
vinegar. [Flag change] Shown in Figure 82. [Explanation] Multiplies the source operand to the destination operand.
do. Multiplication is signed, and the operands are also signed
Treated as an integer. This instruction works because the size of the multiplicand and the size of the result are equal.
It is suitable for high-level languages. The destination size is small and the calculation result is
can be expressed as a signed integer of the size of the destination.
If not, VJlag is set. overflow
Even if a problem occurs, the data set to dest (correct
The lower bits of the new result are used as the reference for MJIag. ZJlag is set. For example, RO=H' 10
Executed MUL, W It) 1'1oooo, RO at 000
In this case, the product is H' 100000000, so RO
=O (lower bit), V-flag=1. Z-
flag=1. [Program exception] - Reserved instruction exception - When RR = 'll' - When M gate = 'll' - When EaR is @-5P - EaM is #imm-data, @SP+, @-5P
[Mnemonic] MULU src, dest [Instruction function] dest * src ==> dest unsigned multiplication [Instruction options] None [Instruction bit pattern and assembler notation] Shown in Figure 83
vinegar. [Flag change] Shown in Figure 84. [Explanation] Multiplies the source operand to the destination operand.
do. Multiplication is unsigned and the operands are also unsigned
Treated as an integer. The destination size is small and the operation result is
can be expressed as an unsigned integer of the size of the destination.
If not, vf lag is set. [Program exception] - Reserved instruction exception - When RR = 'll' - When open = 'll' - When EaR is @-5P
Time [Mnemonic] MULX src, dest, tmp [Instruction function
] destnesrc ==>reg&dest (do
(Uble 5ize) Extended multiplication, larger size [Instruction options] None [Instruction bit pattern and assembler notation] Shown in Figure 85
vinegar. [Flag change] Shown in Figure 86. [Explanation] Multiplies the source operand to the destination operand.
do. This instruction obtains the product with double length, so src and
In addition to dest, there is a template for storing the high-order bits of the product.
Specify polar register tmp. The size is 32 bits
(select from 32/64). Multiplication is unsigned
The size of the product is twice the size of the multiplicand. [MuLX operation] dest[0:31co X src[o:31co =
=> tmpl[0:63 tmp1[32:63] ==> tmpj:0:3
1 piece tmpl[:O:31 piece ==> dest[:
At 0:31, the result to be obtained is dest,
There are two tmps, so if they overlap (dest
If the same register as tmp is specified in ), the problem is
becomes. Generally, tmp (upper digit of MULX) is
It is often used as a carry to the next digit, so
It may not be used when calculating the final digit. Therefore
If the two overlap, the value to be set to dest
(The lower digits of MULX) shall remain. (Appendix
12) 1'1ULX town flag, Z-fla
The flag change of g is based on dest. set in tmp
The values specified have no effect on these flags. This way
The reason for this specification is as follows.・According to flag change specifications such as ADDX, 5UBX, etc.
It was set. (ADDX, 5UBXte is X-fl
Even if ag is set, if dest is 0, ZJ
Iag is set. )・When considering multiple precision operations
It doesn't matter much if you change the flag only with tmp & dest.
It has no taste. In order to change the flag in its original meaning, it is necessary to judge the entire value, which cannot be done using only individual instructions. Hula on tmp & dest
Even if changes are made, they are only half-hearted. Example: [Before execution R1=H'0OO00000dest=)l'2000
0000src=H'40000000 Gate υLX @src, @dest, R1 [After execution tmp=8' 0800000000000000R
1dest Since the value set to dest is 0, Zjlag is set. In addition, MULX, DIVX, ADOX, 5
(Unlike JBX, Zjlag has cumulative changes.
Do not mean. FJlag allows t+np=00 test
. ! In the case of 20, operation is not guaranteed. What is actually the “device of the present invention”? = 0, the src size is
,! Operand as R (8 bits or 16 bits)
and sign-extend it to 32 bits.
The command is executed. However, dest and tmp are! Always 32 bits regardless of R
treated as a [Program exception] - Reserved instruction exception - When +R = 'll' Note)! When it is 20, it is not detected as a reserved instruction exception.・When EaR is @-5P - EaMR is #imm-data, @SP+, @-5P
[Mnemonic] DIV src, dest [Instruction function] dest / src ==> dest division [Instruction options] None [Instruction bit pattern and assembler notation] Shown in Figure 87
vinegar. [Flag change] Shown in Figure 88. [Explanation] Assign the destination operand to the source operand.
Ru. The division is signed, and the operand is also a signed integer.
considered as a number. This instruction works because the size of the dividend and the size of the result are equal.
It is suitable for high-level languages. The quotient is rounded towards 0, and the sign of the remainder is the same as the dividend.
Ru. Example: 1013 → quotient = 3. Remainder = 1(-
10)/3 → Quotient = (-3), Remainder = (-
1) 10/(-3) → Quotient (-3)t Remainder
=1src=0, divide-by-zero exception (ZDE)
Become. In case of division by zero, VJIag is set and exception handling is performed.
It is activated, but the value of dest does not change. At this time, whether or not to perform write access to dest
, i.e. write the same value or write nothing
shall not be stipulated. Also, flags other than Vjlag do not change. this is,
dest and exception handling program
In order to analyze the cause of the exception, it is necessary to
Preferably the state (including flags) is preserved
It's for a reason. Overflow occurs when DIV is not divided by 0.
Only in the case of (minimal negative number) ÷ (-1). D.I.V.
Unlike the old vx, is a normal operation generated by the compiler.
Since it is an instruction, it should have the same specifications as other arithmetic instructions as much as possible.
It is preferable to do so. So, the flag change in this case is
, Taking advantage of the meaning of each flag, V,, flag=1, L-flag=o, M-fla
g=1. Z-flag=0 (when minimum negative number ÷ (-1)). Overflow is (minimum negative number ÷ (-1)
), the lower bits of the correct result are set to dest.
Even if you think that dest will be changed, dest will not change after all. Positive
Even if you think that it is the lower bit of the new result, it ends up being the same value.
be. Example: 5rc=H'ffff=(-1), dest=)l'3
When executing DIV, H with 000=(-32768) ==>dest=H'8000. V-flag=1d
8'8000 of est is the correct result (H', , 0
It can also be considered as the lower bit of 08000=32768).
It is possible, or it can be considered that dest has not changed. [Program exceptions] - Reserved instruction exception When φRR = 'll' - When EaR = 'll' - When EaR is @-5P - EaM is #imm-data, [i! SP+, @-S
When P / Zero division exception / When 5rc = 00 [Mnemonic] DIVU src, dest [Instruction function] dest / src =:=> dest unsigned division
[Instruction options] None [Instruction bit pattern and assembler notation] Shown in Figure 89
vinegar. [Flag change] Shown in Figure 90. [Explanation] Assign the destination operand to the source operand.
Ru. Division is unsigned, and the operands are also unsigned integers.
considered as a number. If 5rc=:O, a division-by-zero exception (ZDE) occurs.
Ru. In case of division by zero, VJIag is set and exception handling is performed.
It is activated, but dest does not change. At this time, de
Whether or not to perform write access to st, that is, the same
It is not specified whether the same value or nothing is written.
To be. Also, flags other than Vjlag do not change.
. This is because it is adjusted to dest, and exception handling
In order to analyze the cause of an exception in a program, you can
Only those whose previous state (including flags) are saved
This is because it is desirable. In the DIVLI instruction, overflow occurs in cases other than division by 0.
A low will never occur and set VJlag. Therefore, in cases other than division by 0, VJlag is always cleared.
will be ascribed. [Program exception] - Reserved instruction exception - When RR = 911' - When M unit = 'll' - When EaR is @-5P - EaM is #imm-data, @SP+, @-5P
When: Zero division exception φ5rc=o [Mnemonic] DIVX src, dest, tmp [Instruction function
] reg&dest/src ==> dest, r
eg (quotient, reminder) Extended division, reduces size, produces remainder [instruction option
[Instruction bit pattern and assembler notation] Shown in Figure 91
vinegar. [Flag change] Shown in FIG. 92. [Explanation] Assign the destination operand to the source operand.
Ru. This instruction is a primitive for multiple precision division.
, src and dest, as well as tempo for extended operations.
Specifies the register in which to place the value (remainder). Size is 3
Fixed to 2 bits (select from 32/64), division is
It is done unsigned, and the size of the dividend is 2 of the size of the divisor.
Double. [DIVX operation] concatenate(tmp[0:31, des
t[0:31 quo) ==> t+apl[o:63 quo(tmpl[0:63], src[o:311)
==> dest[0:31] rem(tmpl[0:63], src[o:31])
==> tip [0:31] In DIVX, the result to be obtained is dest and tip.
Since there are two, if they overlap (destT:tm
If the same register as p is specified, the problem is how to deal with it.
. Generally, tip (remainder of DIVX) goes to the next digit.
It is often used as a digit decrease, so the last digit
It may not be used in calculations. Therefore, both
If they overlap, the value to be set to dest (DIV
The quotient of X) shall remain. In addition, DIVX is an instruction that can be used when the dividend is multiple precision.
However, if the divisor becomes multiple precision, DIVX
cannot be used, and the program may repeatedly shift or subtract.
You must proceed with the division while returning the numbers. At this time, many
A double-length shift operation is required. Achieves multiple length shifts
In order to do this, the rotate command (St(
XR, 5) IXL) are available. DIVX Mjlag, Z-flag flag change
is based on dest (quotient). set to tmp
The value (remainder) has no effect on these flags. however
, it is possible to test tmp=o using FJlag
. MULX, DIVX and ADDX, 5UBX and
is different, Z-flag does not undergo cumulative changes.
do not have. MOV if the result overflows in DIVX. Overflow and specifications in ADD, SUB, MUL
In the sense that the lower bits of the correct result are
It is desirable to set it to dest. However, ADD,
Like Sue, it's naturally correct even when it overflows.
Unlike the ones where the lower bits of the result are obtained, in the case of division
Since the calculation is performed from the upper bits, the algorithm
It is difficult to get the lower bits of the correct result in a relation. Therefore, in case of overflow of DIVX, d
The specification is such that est is not changed. In DIVX, the quotient does not enter dest and an overflow occurs.
If the flag is generated, flags other than VJlag will not change.
. This is done when an overflow occurs in otvx.
, dest do not change. If 5rc=o, a division-by-zero exception (ZDE) will occur.
. In the case of division by zero, dest and tmp do not change. Konoto
and whether or not to perform write access to dest.
In other words, there is no regulation as to whether the same value or nothing is written.
shall not be done. Also, flags other than VJIag are changed.
It doesn't change. This is because it is aligned with dest, and
To analyze the cause of an exception using an exception handling program
, the previous state (including flags) is preserved as much as possible.
This is because it is more attractive. ! If = 0, operation is not guaranteed. In fact, the device of the present invention! =00, set the src size to
,! Operand as R (8 bits or 16 bits)
and sign-extend it to 32 bits.
The command is executed. However, dest and tmp are! Always 32 bits regardless of R
treated as a [Program exception] - Reserved instruction exception - When IR = 'll' Note)! When = 0, it is not detected as a reserved instruction exception.・When EaR is @-5P ・EaMR is #imm-data, @SP+, @-5P
- Zero division exception - When 5rc = 0 [Mnemonic] REM src, dest [Instruction function] dest X src ==> dest remainder [Instruction options] None [Instruction bit pattern and assembler notation] Shown in Figure 93
vinegar. [Flag change] Shown in FIG. 94. Divide the rand and find the remainder. Division is signed on the line
The operands are also assumed to be signed integers. This instruction works because the size of the dividend and the size of the remainder are equal.
It is suitable for high-level languages. The quotient is rounded towards 0, and the sign of the remainder is the same as the dividend.
Ru. Example: 10/3 → quotient = 3. Remainder = 1(-
10)/3 → Quotient = (-3), Remainder = (-
1) 10/(-3) → quotient = (-3), remainder
When remainder = 1s rc = o, division by zero exception (ZDE
). However, when dividing by 0 with REM, the overload
Clear the flow and trigger exception handling. R
Unlike the DIV instruction, with the EM instruction, even if you divide by 0,
dest (remainder) does not overflow
Therefore, it is more rational to clear VJlag. Also, if you clear VJlag, during exception handling
It is difficult to determine whether the error is due to DIV or REM.
water. In the case of division by 0, dest remains unchanged. against dest
to access the memory (read or the same
read-modify-write), access
How to implement
It is not stipulated because it would be binding. [Program exceptions] - Reserved instruction exception - When RR = 'll', When gate = 'll' - When EaR is @-5P, φEa riset#imm-data, [i! SP+, @-5
When P/Zero division exception @5rC=0 [Mnemonic] REMU src, dest [Instruction function] destχsrc ==> dest Remainder from unsigned division [Instruction options] None [Instruction bit pattern and assembler notation] No. 95 As shown in the figure
vinegar. [Flag change] Shown in Figure 96. [Explanation] Assign the destination operand to the source operand.
and find the remainder. Division is unsigned and the operation
Land is also considered an unsigned integer. src and dest
If the sizes are different, zero extension is performed. This instruction works because the size of the dividend and the size of the remainder are equal.
It is suitable for high-level languages. If 5rc=:O, a division-by-zero exception (ZDE) occurs.
Ru. The handling in the case of division by 0 is the same as in REM. [Program exception] - Reserved instruction exception - When RR = 'll' - When HO = 'll' - When EaR is @-5P - When EaR1#imm-data, @SP+, @-5P
When: Zero division exception When 5rc=0 [Mnemonic] NEG dest [Instruction function] 0- dest ==> dest Complement operation [Instruction options] None [Instruction bit pattern and assembler notation] Shown in Figure 97
vinegar. [Flag change] Shown in Figure 98. [Explanation] Inverts the sign of the operand. When the value of dest after executing the LJIag instruction is negative
, that is, it is set when the initial value of dest is positive. Town flag MSB of dest after command execution is 1
, that is, when the initial value of dest is a positive or minimum negative number. When the value of dest after executing the ZJIag instruction is O
, that is, it is set when the initial value of dest is 0. V,, the initial value of flag dest is the minimum negative number (M
Only SB is set to 1, and only the other bits (allo) are set. [Program exception] - When reserved instruction exception number MM is 111 - EaM is #imm-data, l! SP+, @-5P
When [Mnemonic] INDEX 1ndexsize, 5ubscri
pt, xreg [Instruction function] calculate address of arra
y Multidimensional array address calculation [Instruction options] None [Instruction bit pattern and assembler notation] Shown in Figure 99
vinegar. [Flag change] Shown in Figure 100. [Explanation] Address calculation for expanding a multidimensional array into a one-dimensional array
, scale multiplication and index addition are performed. 5ubscript size is larger than x reg size
If the value is also small, 5ubscript is sign-extended. xreg. 1ndexsize, 5ubscript is signed
are considered integers, and multiplication and addition are performed with signs. Squared
If an overflow is detected during calculation or addition, V
Set JIag. 1ndexsize is a fixed value (immediate)
Although it is often possible to
We are considering creating a general-purpose addressing system. If the INDEX instruction is executed after the CHK instruction,
5ubscript only needs to specify registers. deer
However, depending on the specifications of the high-level language, the range may not be checked (
C) The IK instruction may not be executed), so the
So that the variables can be used as 5ubscript,
5ubscript also uses general-purpose addressing. [INDEX operation code xreg * 1ndexsize + 5ubscr
ipt ==> In the xregINDEX instruction, the opera
ndxreg, 1ndexsize. All 5ubscripts are signed, not pointers.
It is treated as a number. Calculate as is even if it is negative,
No special operations such as EIT are performed. Also, the flag change (
VJIag, L-flag, M-flag, Z-flag
g) is also based on general arithmetic operation instructions. I would like to add some additional information regarding this. The operand handled by INDEX is not a pointer.
It is an index of an array, and INDEX is an index of an array.
The process of expanding the square into one dimension is performed. India
The reason why the box becomes a pointer is due to the scaling of the append mode.
This is after performing (x4) etc. Therefore, IN
Even if you think of the data handled by DEX as signed, there is nothing particularly unnatural about it.
In languages where it is a problem if the index becomes negative,
You can also check it. ! :00, operation is not guaranteed. In fact, the device of the present invention! If = 0, 1ndexsi
ze size! As R (8 bits or 16 bits)
Fetches the operand and encodes it in 32 bits.
The command is executed with the code expanded. However, xreg! R
It is always treated as 32 bits regardless of the [Program exception] - Reserved instruction exception When t* = 'tt' - When ss = 'tt' Note)! When = '0', it is not detected as a reserved instruction exception.
do not have.・When EaR and EaR2 are @-SP, 12-4. Hiroguchi Δ [Mnemonic] AND src, dest [Instruction function] dest, and, src ==> dest logic
Product [Instruction option] None [Instruction bit pattern and assembler notation] Figure 101
show. [Flag change] Shown in FIG. 102. [Explanation] The relationship between source operand and destination operand
Take a logical product. The size of the source operand is the size of the destination operand.
operation between different sizes (AND: G
RR≠Tom, AND: E's ≠00), then life
The order will be executed as is and will not become a reserved order exception, but
The result set to dest cannot be guaranteed (implementation
(depending on the client). Specifications of the device of the present invention
does not specify logical operations between different sizes.
This feature must not be used in software. different
Logical operations between seed sizes are meaningless instructions, but
, the reason why this is not a reserved instruction exception is due to the implementation
This is because the load is large and the execution speed is affected. Town flag RO Zjlag [RO-d-1ko = 0 [Prog
RAM exception] - Reserved instruction exception - When RR = 'll' - When open = 'll' - When EaR is g-sp - EaM is #imm-data, @SP+, @-5P
Time [Mnemonic] ORsrc, dest [Instruction function] dest, or, src =:=> dest logic
Sum [Instruction options] None [Instruction bit pattern and assembler notation] Figure 103
show. [Flag change] Shown in FIG. 104. [Explanation] The relationship between source operand and destination operand
Take the logical sum. The size of the source operand is the size of the destination operand.
operation between different sizes (OR: G's
If RR≠mon, OR:E no ≠00), the command is
It will be executed as is and will not result in a reserved instruction exception, but de
The result set to st cannot be guaranteed (implementation
be dependent upon) Gate-flag RO ZJIag [RQ ~d-1co = 0 [Pro
Program exception] - Reserved instruction exception - When RR = 'll' - When open = 'll' - When EaR is toSP - EaM is #imm-data, @SP+, @-5P
Time [Mnemonic] XORsrc, dest [Operation of command #! ] dest, xor, src =:=> dest exclusion
Alternative OR [Instruction option] None [Instruction bit pattern and assembler notation] Figure 106
show. [Flag change] Shown in FIG. 106. [Explanation] The relationship between source operand and destination operand
Perform exclusive OR. The size of the source operand is the size of the destination operand.
operation between different sizes (XOR: G
(7) RR6MM, XOR:E(7)MM#00)
If the instruction is executed as is, the reserved instruction exception is
However, the result set to dest cannot be guaranteed.
(It is implementation dependent). Gate-flag RO ZJIag [:RO-d-1] = 0 [Prog
RAM exception] - Reserved instruction exception - When RR = 'll' - When EaR = 'll' - When EaR is @-5P - EaM is #imm-data, @SP+, I knee SP
[Mnemonic] NOT dest [Instruction function] dest ==> dest Invert all bits [Instruction options] None [Instruction bit pattern and assembler notation] Figure 107
show. [Flag change] Shown in FIG. 108. [Explanation] Inverts the 1 and O of each bit of the operand. Mjlag MSB of dest after execution of instruction is 1
In other words, when the MSB of the initial value of dest is O, the
will be cut. When the value of dest after executing the ZJIag instruction is 0
, that is, it is set when the initial value of dest is 00. [Program exception] ・Reserved instruction exception ・When time='ll' ・When EaM is #imm-dataJsP+, @-SP
Ki12-5. ingredient . Δ [Mnemonic] SHA count, dest [Instruction function] 5hift arithmetic Arithmetic shift [Instruction option] None [Instruction bit pattern and assembler notation] Figure 109
show. [Flag change] Shown in FIG. 110. [Explanation] The destination operand dest is the source operand.
Arithmetic shift by the specified number of bits
Ru. - In the ship shape command, the shift is determined by the sign of the count.
Specify the direction. Shift left when count is positive, negative
Shift to the right. Since it is an arithmetic shift, the destination is
The MSB (sign bit) of the version does not change and has the same value.
is copied to the right bit. in case of left shift
, an O is placed in the LSB and a 0 is copied to the left bit.
To go. Specifying the shift direction by positive or negative is an emitter of floating point arithmetic.
It may be useful for simulation, etc. In the case of left shift, there is no abbreviation of SHA, but flag change
may be different from SHA, the abbreviated form of SHL 5) I
L: Can be substituted with Q. [In case of left shift (count > O)] In Figure 111
show. [In case of right shift (count < O)] In Fig. 112
show. In addition, if count=00, X-flag=o.
Ru. 5) In the IA instruction, the size of count is 8 bits.
is valid only. Operation is not guaranteed if RR≠00
. The reason why the RR≠00 function cannot be used is mainly due to the
This is due to constraints on the product. In the case of RR≠00, in the "device of the present invention", the size
Fetch the count operand in RR ~co
Only the lower 8 bits of unt are valid and the command is executed as is.
Execute. SHA is an arithmetic operation, so set L-f l ag
However, this reverses the sign (MSB) of the first value of dest.
to project. This is because Ljlag can handle overflows and
Even if there is a low flow, the calculation results will always be correct.
This is because it has the property of reflecting the sign. S
In the case of a ft instruction, if no overflow occurs, d
The sign of est does not change. For right shift, or left
L-fla if the overflow is stopped by the shift
g=gate-flag, but with left shift it overflows
If this occurs, the LJIag and the flag are different.
Sometimes things change. rThe device of the present invention is a big-endian chip.
Therefore, should we consider count in terms of increasing or decreasing bit positions?
, the shift direction is opposite depending on whether you think of it in the sense of a power of 2.
Become. In other words, in the former way of thinking, when count > O, it should be shifted to the right, whereas
, in the latter way of thinking, the l1ttfe-endian case
In the same way as when count>o, it is a left shift. However, shift instructions are more arithmetic than bit-manipulation-related instructions.
Since it is similar to an instruction related to arithmetic operations, rather than thinking of count in terms of increasing or decreasing bit positions,
It is more natural to think of it in terms of a power of 2. therefore,
In the device of the present invention, when count > 0, it is called a left shift.
The specifications are as follows. 5) IL, 5) IA, the absolute value of count is (de
Even if the size of st + 1) is exceeded, the specified number
Continue shifting. As a result, the count
The behavior is the same as when the pair value is (size of dest + 1).
Ru. For example, do the following: SHA #33. dset, W; dest=
XJlag:0 5HL #33. crest, W; dest
=X-f Iag=0 5) IA It-33, dest, ri; des
t=XJ Iag=old dest MSB SHL #-33. dest,%J;de
st=X-flag=0 Note that, excluding X-flag, the absolute value of count is (
The same result is obtained if the size of dest is equal to the size of dest. [Program exception] - When reserved instruction exception ΦRR = 'll' - When M gate = 211ゝ When φEaR is @-5P - EaM, ShM are lt imm-data, @SP+
, when SP [Mnemonic] 5) IL count, dest [Instruction function] 5hift logical Logical shift [Instruction option] None [Instruction bit pattern and assembler notation] In Figure 113
show. [Flag change] Shown in FIG. 114. [Explanation] Copy the destination operand to the source operand
Logically shifts by the number of bits specified by unt. - membrane
In the case of a shape, the shift direction is specified by the sign of count. c.
When ou n t is positive, it shifts to the left, and when it is negative, it shifts to the right.
. In the case of a right shift, a 0 is placed in the MSB, and a 0 is placed in the right bit.
In the case of a left shift,
0 is placed in the LSB and 0 is copied to the left bit.
Ku. [In case of left shift (count > 0)] In Figure 115
show. [In case of right shift (count < O)] In Fig. 116
show. Note that if count=0, X-flag=0.
Ru. 5) In the IL instruction, the countO size is 8 bits.
is valid only. If RR≠00, operation is guaranteed.
do not have. The main reason why the function of RR≠00 cannot be used is
This is due to implementation constraints. RR≠00
In the case of ``the device of the present invention'', the size RR is cou
nt operand and lower order of count
Only 8 bits are valid and the instruction is executed as is. [Program exception] - Reserved instruction exception - When RR = 'll' - When MM = 'll' When φEaR is @-5P EaM, ShM are #imm-data, @SP+, @
-SP [Mnemonic] ROT count, dest [Instruction function] otate Rotate r Instruction option] None [Instruction bit pattern and assembler notation] Figure 117
show. [Flag change] Shown in FIG. 118. [Explanation] Copy the destination operand to the source operand
Rotate by the number of bits specified by unt. That is,
The bits overflowing from the LSB (MSB) are converted to the MSB (LSB).
Shift while filling the space. The rotation direction is specified by the sign of count. count is
When it is positive, it rotates to the left, and when it is negative, it rotates to the right. When rotating, do not pass the flag. [In case of left rotation (count>0)] This is shown in FIG. 119. [In case of clockwise rotation (count < 0)] As shown in Fig. 120.
vinegar. In addition, if count=00, X-flag=o.
Ru. In the ROT instruction, the countO size is 8 bits.
is valid. In the case of RR#OO, operation is not guaranteed.
. The reason why the RR≠00 function cannot be used is mainly due to the
This is due to constraints on the product. When RR≠00
In this case, the device of the present invention has a count value of size RR.
Performs a fetch of Pelland, and fetches the lower 8 bits of count.
Executes the command as is, with only the default enabled. In ROT, the absolute value of count is (size of dest)
Even if it exceeds the limit, it will continue to rotate by the specified number.
Continue. As a result, count (size of dest
) is the same behavior as when the remainder after dividing by is set as count.
Ru. However, count is an integer of (size of dest)
If times (≠0), then X depending on MSB or LSB
-f The point where lag is set is when count=00
It is different from the case. For example, the number of bits is the same as the data size.
When rotated, the data value itself does not change, and de
st has the same value as when count=0. However,
Since the original data SB is copied to the flag,
The lag change will be different from when count=o
. [Program exception] - Reserved instruction exception - When RR = 'll' ◆ When Tomo = 'll' - When EaR is @-5P - EaM is #imm-data, @SP+, @-5P
Time [Mnemonic] 5) IXL dest [Instruction function] 5hift 1eft with extend extension left
Shift [Instruction option] None [Instruction bit pattern and assembler notation] Figure 121
show. [Flag change] Shown in FIG. 122. [Explanation] Shift dest to the left by 1 bit and change the original Xfla and g.
Pack the contents into LSB. Bits overflowing from MSB are X
Enter flag. This instruction writes multiple words of 1-bit data.
Dedicated as a primitive to perform a function
The size of the shift target is fixed at 32 bits.
In some cases, such as points where the
The specifications are quite different from 5) IA, 5) IL, and ROT. DIVX is an instruction that can be used when the dividend is multiple length.
However, if the divisor becomes multiple precision, DIVX is used.
The program cannot repeat shifts and subtractions.
We have to proceed with the division. At that time, multiple length
A shift operation is required. This instruction is used in such cases
This is an instruction intended for use in In Figure 123
This is shown. [Program exception] - Reserved instruction exception - When + = 'O' - When - = 212 - When X = 'l' - EaMX is #imm-data, @SP+, @-SP
When [Mnemonic] 5HXRdest [Instruction function] 5hift right with extend extension
Right shift [Instruction option] None [Instruction bit pattern and assembler notation] Figure 124
show. [Flag change] Shown in FIG. 126. [Explanation] Shift dest one bit to the right and change the original
Pack the contents into MSB. Bits overflowing from LSB are X
Enter flag. This instruction writes multiple words of 1-bit data.
Dedicated as a primitive to perform a function
The size of the shift target is fixed at 32 bits.
In some respects, such as points where the data can be shifted only by 1 bit, etc.
5) Specifications are quite different from IA, SHL, and ROT. DIVX is an instruction that can be used when the dividend is multiple length.
However, if the divisor becomes multiple length, DIVX is used.
The program cannot repeat shifts and subtractions.
We have to proceed with the division. At that time, multiple length
A shift operation is required. This instruction is used in such cases
This is an instruction intended for use in In Figure 126
This is shown. [Program exception] - Reserved instruction exception - When + = '0' - When - = '1' - When x = 't' - EaMX is # imm-data, @SP+, @-5
When P [Mnemonic] RVBV src, dest [Instruction function] reverse byte order Reverse byte order [Instruction options] None [Instruction bit pattern and assembler notation] Figure 127
show. [Flag change] Shown in FIG. 128. [Explanation] Transfer the byte order of src to dest with the byte order reversed.
. If the size of dest is larger than src,
After zero-extending src to the size of dest, de
Reverse the byte order according to the size of st. If the size of dest is smaller than src,
Cut the upper byte of src and make it the size of dest.
After that, the byte order is reversed by the size of dest. (After shifting the address of src, change SrC and dest.
Example: src = I ('1234 RVBY src, H, dest, H ==> des
t =14'3412 RVBY src, H, dest, W ==> de
st =H' 34120000 RVBV src,H,dest,B ==> de
st = H'34 (not H'12) This instruction has no overhead for endian conversion.
This is an instruction aimed at reducing the number of codes. [Program exception] - Reserved instruction exception - When RR = 'll' When φ4 = 'll' When φEaR is @-5P When φEaW is #imm-data, @SP0 [Nemo
Nick] RVBI src, dest However <L2>> [Instruction function] reverse bit order Reverse bit order [Instruction options] None [Instruction bit pattern and assembler notation] See Figure 129
show. [Flag change] Shown in FIG. 130. [Explanation] Transfer the reversed bit order of src to dest
. If the size of dest is larger than src,
After zero-extending src to the size of dest, de
Reverse the bit order according to the size of st. If the size of dest is smaller than src,
Cut the upper byte of SrC and make it the size of dest.
After that, the bit order is reversed by the size of dest. (After shifting the src address, src and dest
Even if the size is the same, the result will be the same) Party B's command is,
Reduce overhead for 6ndian conversion
This is a command aimed at. Consider bitmap processing.
Then, the bit reverse instruction RVB which reverses the order of the bits
It would be better to have +, but it is a byte reverse command RVBY.
It also requires less frequent and no additional hardware.
Because there is a strong possibility that
2>>. [Program exception] - Reserved instruction exception - When RR = 'll' - When 4 = 'll' - When EaR is @-5P - When εaW is #imm-data, @sP+ 12-
6. Beep. Δ In the bit manipulation instruction of the "device of the present invention", base (base address) offset (
bit address)
Specify the bit to be manipulated. bits on register
When operating, in addition to this, also consider the base size.
Affects bit specification. [When operating bits on memory] This is shown in FIG. 131. In the film-type bit manipulation instruction of the device of the present invention, the off
There is no limit to the value of set, and offset crosses a byte boundary.
It is now possible to exceed it. offset is the sign
treated as an integer. In bit manipulation instructions, memory access is performed using the BB field.
It is now possible to specify the range of access. This is B
The range of memory addresses to be read by TST, and
read-mod with BSET, BCLR, BNOT
Memory address to perform i fy-wr ite
It means a range. Memoriad accessed
The range of responses is limited by input/output and when using multiprocessors.
This may cause problems in some cases. But actually, byte-wise access (',B')
Since it is sufficient in most cases if only the
Access in halfword or word units is <<L2>>.
(Excluding bit manipulation instructions for registers)
. Also, access in halfword and word units makes sense.
It has aligned halfwords and words.
halfword
, in order to use the word-by-word access function, b
Be sure to specify an aligned address as ase.
Set limits on what must be done. This is
To facilitate implementation while specifying access ranges,
It's a good thing. Therefore, an aligned half wire
Memory access including the target bit is performed in unit of code.
If you want to
There is a point. Also, in units of aligned words,
, when you want to access memory that includes the target bit.
, it is necessary to specify a multiple of 40 as the base. o
There are no restrictions on the value of ffset. as base
When specifying an unaligned address
Access scope shall be implementation dependent.
. In the device of the present invention, the memory designated as <<L2>>
Implies halfword, word-wise access to
Rement. Also alignment as base
Even if you specify an address that is not
Range is aligned halfword, single word
Access is performed at the location. [Example] BSET, B 1tH'84. @)l'100offs
et 1 B = 4; base + offset
/8 = H'llO, so bit 4 of H'llO
set. read -modif for 1 byte of H'llO
y-write is performed. BSET, B#) l'7c, @H'1O1offse
T! ,,8 = 4; base + offset
/8: Since the access size is byte in H'llO
, BSET, B #H'84. @) Exactly the same as I'100
It does the same thing. BSET, W #)l'84. @H'100offse
t X 8 = 4; base + offset/
8 = H'llO, so set bit 4 of H'llO.
cut. Since base is a multiple of 4, H'100~)
Regarding the aligned 32 bits of l'103
Perform read-modify-write and modify the target bit.
Set the cut. BSET, W #H'7c, @H'101offset
X 8 = 4; base + offset/8
= )I'llO, so similarly H'llO
Set bit4. However, since base is not a multiple of 4, read-
About the access range for modify-write
is implementation dependent. In addition, the size indicated by 8B is "for which range"
Should I perform read-modify-write? j and
This means that the offset range (for example, if zB゜, the offset is less than 8)
(e.g., smaller size, etc.). For bit manipulation instructions to registers, the size of the access is
offset=o(M
Since the bit position of SB) changes, the size of base is
Important *If base is register direct Rn
If so, the base size j and HzJt are also <<Ll>>.
be. For bit manipulation instructions with register Rn@base
, offset is the lower 3 bits when B',', H'
When , the lower 4 bits, when '6%Il', the lower 6 bits, '
, L', only the lower 6 bits are valid, and the upper bits
, is ignored. An error occurs even if the upper bit is not 0.
It is not considered an EIT. From an architectural perspective, the top
Rather than ignoring the bits, just like the width of the BF instruction,
It is better to check the offset range properly.
However, checking increases the instruction execution time, so offset is the number of bits of the access size.
I am planning to use modulo. 8 bit data, 16 bit data, 32 bits on register
If bit data is placed, each piece of data must be the same.
Even if the bits have the same bit position, they actually correspond to different bits, so care must be taken. To avoid complicating the specifications, the assembler defaults to B for both memory targets and register targets. Also, the abbreviated form is also the specification of B.
Ru. Therefore, in registers that can be accessed in short form,
The range is bits 2°0 to 2°7 (see Figure 132).
N). [Example] BSET:Q $1. In rO, BSE
In case of T, the default is B, so ro, bit 1 of B is set. This bit is different from bit 1 of ro, W and corresponds to bit 25 of ro, W. For example, if you intend to access bit 2°17, BTST #14. When written as RO, it is actually BTST, B #14. Since offset ignores the upper bits, the bits 2-1 are the target. Correctly, BTST, Oath #14. It must be written as RO. In such cases, it would be best to issue a warning in the assembler. [Mnemonic] BTST offset, base [Instruction function] -bit -> Z-flag Bit test [Instruction options] None [Instruction bit pattern and assembler notation] Figure 133
show. [Flag change] Shown in FIG. 134. [Explanation] Inverts the value of the specified bit and sets it to Z-flag.
make a copy. Addressing specified by EaRf, 5hRfq
In the mode, immediate mode l$imm-dat
a. @-5P and @SP+ cannot be used. Also, the Rn model
When using a code, the value of the upper bit of offset is
It will be ignored. In assembler notation, the size of memory access is bas
Specify as the size of e. BTST: In Q, memory
The access size is fixed at 8 bits, and the size
can only write ′, B′. [Program exception] - Reserved instruction exception When ΦRR = 'll' - When BB = 'll' When urn EaR is tSP, φEaRf, 5hRfq are #imm-data, @SP
+, @-5P [Mnemonic] BSET offset, base [Instruction function] "bit -> Z-flag, 1-> bit
Set of [Instruction options] None [Instruction bit pattern and assembler notation] Figure 135
show. [Flag change] Shown in FIG. 136. [Explanation] The inverted value of the specified bit is Z-f lag
and then set that bit to 1. Addressing specified by EaMf, ShMfq
In the mode, immediate mode old mmJata. @-5P, @SP+Ha is good to use. Mata, Rn(
If D-E-mode is used, the upper bit of offset is
The value of the cut is ignored. In assembler notation, the size of memory access is bas
Specify as the size of e. BSET: In Q, memory
The access size is fixed at 8 bits, and the size
is 2. Only B' can be written. [Program exception] - Reserved instruction exception - When RR = 'll' - When BB = 'll' - When EaR is @-SP - EaMf and ShMfq are #imm-datas@SP
+, @-SP [Mnemonic] BCLRoffset, base [Instruction function] -bit -> Z-flag, O-> bit
Clear [Instruction option] None [Instruction bit pattern and assembler notation] Figure 137
show. [Flag change] Shown in FIG. 138. [Explanation] Inverts the value of the specified bit and sets it to Z-flag.
Copy and then clear that bit to 0. Addressing mode specified by EaMf, ShMfq
In immediate mode ltimm-data. @-5P and @SP+ cannot be used. Also, the Rn model
When using a code, the value of the upper bit of offset is
It will be ignored. In assembler notation, the size of memory access is bas
Specify as the size of e. BCLR: In Q, memory
The access size is fixed at 8 bits, and the size
Only B′ can be written. [Program exception] - Reserved instruction exception - When RR = 'll' - When BB = 'll' - When EaR is @-5P - EaMf, ShMfq are #imm-data, @SP
+, @-5P [Mnemonic] BNOT offset, base [Instruction function] "-bit -> Z-flag, -bit -> b
Inversion of it bit [Instruction option] None [Instruction bit pattern and assembler notation] Figure 139
show. [Flag change] Shown in FIG. 140. [Explanation] Inverts the value of the specified bit and sets it to 2-flag.
Copy and then flip that bit as well. In the addressing mode specified by EaMf,
Diet mode #imm-data, @-SP,
@SP+ cannot be used. Also, use Rn mode
, the value of the upper bits of offset is ignored.
. In assembler notation, the size of memory access is bas
Specify as the size of e. [Program exception] - Reserved instruction exception When φRR = 'll' - When BB = 'll' - When EaR is @-5P - EaMf is #imm-data, @SP+, @-5P
When [Mnemonic] B5Cl data, offset [Instruction function] find first 'O' or 'l' in
the bitfield
d) Search for 0 or 1 (within 1 word) [Instruction options] Search for 70'0'' (default) Search for 71'1'/F Search in the direction of increasing bit number (default)
) /8 Search in the direction of decreasing bit number <<L2>>
(Supported by M32) [Instruction bit pattern and address
Assembler notation] Shown in FIG. 141. [Flag change] ゛ Shown in Figure 142. [Explanation] Search for bit tO' or 21' in a word.
Ru. Bit number to start search (bit offset)
Set the offset operand and execute this instruction.
Then, after the instruction is executed, the bit number of the search result is off.
It is set in the set operand. offset is read-modify-write
There is a lot of trouble. read-modify-0ffset
The Write format was created by repeatedly searching for bits.
This is because they were expected to do so. The range of bit positions searched is determined by the data operation.
It is limited to land 00 ~ (size of data), and
cannot cross code boundaries. All sizes are available for offset.
However, the upper bits of the initial value of offset are used during the search.
is ignored. This places word boundaries on the upper bits.
The excess bit offset, effective address, etc.
In addition, it is thought that other information is often included.
It is. Also, in order to lighten the specifications of BSCH and speed it up.
It's a good thing. In addition, when /F is used, the number representing the size of data
, /B becomes (-1). "Higher bit" means l
The bits higher than og2 (number of bits of data)
show. If the data is 32 bits, 2"5 to 2-3
The 1 bit is the upper bit. The search is in the direction of larger bit numbers, that is,
In the big-endian device of the present invention, the LSB
The standard specification <<IQ>> is carried out in the direction of
Yes, implemented by the /F option. reverse direction
The CH/B option has the <<L2>> specification. child
This means that searching in the forward direction and searching in the reverse direction are completely different hardware.
This is because software is required. Also, the searched da
Of the size of ta, 8 bits and 16 bits (RR=O
The specification of O101) is <<12>shi. "Book
Inventive Device, the /B option is <<L2>>.
8-bit and 16-bit data size (RR=0
0.01) is also supported. BSC)l is classified in the same category as bit manipulation instructions, but
They have quite different characteristics. Even with the BSCH command,
You can freely set offsets like other bit manipulation instructions.
There is a concept that it is easier to use if the
Since the BVSC) I command is provided separately for the
As a CH, we narrowed down the specifications to the lightest possible, and the offset
The range is limited. The effective range of the offset is
When register direct mode Rn is specified with a cut operation instruction
is within the same range. Also, in general bit manipulation instructions, o
ffset is read-only. base is read-modify-write
On the other hand, in BSCH, o
ffset read-modify-write,
data (base address) is read
-only, so you need to be careful. BSC) The specified bit was not found in l/F.
the last bit searched (word boundary)
) is set, and the offset of the next bit of V,,fl
ag=1. EIT will not start even if the search fails.
stomach. As a result, it is turned off for the number of bits searched.
The sets are added. [Example @meml = )l'oooooooo, ROe O
, big-endian BSC) I10/F @meml , W, RO
Execute ==> RO=0 (7), V-flag is 0@
meml = H'ffff7fff, RO = O,b
BSC in ig-endian) I10/F @meml, W, RO
Execute ==>RO=16, V-flag is 0@m
eml = )I'ffffffff, RO = 0. b
BSC in ig-endian) I10/F @meml, W, RO
Execute ==>RO=32, V-flag is 1BS
C) When the specified bit is not found in I/B
, offset is set to (-1). In this case as well, VJIag is set, but EIT is activated.
Not done. In the BSCH instruction, the upper bit of the initial value of offset
is ignored, but offset is set after the instruction completes.
Regarding the t value (search result), the meaning up to the upper bits is
It has the value that it has. In other words, the upper bits of offset
In addition, bit offsets and effective
Even if other information such as an address is included, the BSC
) After executing the l instruction, the upper bit of 0ffset is also rewritten.
This means that you will be given a refund. Offs when search is successful
et takes a value from 0 to 31 (if data is 32 pits)
Therefore, the upper bits of both /F and /B are always 0. Also, if the search fails with /F, set offset=32.
Therefore, the upper bit is 00. ,,． 001, lower bit
The cut becomes ooooo. /B if the search fails, o
Since ffset=('1), the upper bits are 11.
,,． 111, and the lower bit becomes 11111. [Example @meml 2H'00000000. RO=H'0
OOOO020TEBSCH10/F @III
Execute eml, W, RO, W ==>RO: )l'0
It becomes 0000000. (RO= )l'00000020) phase
eml = H'ffff7fff, RO = H'00
000020i? BSCH10/F @mem
Execute l, W, RO, W ==>RO= )l'ooo
It becomes ooo10. (RO= not H'0OOOO030) @meml
20'ffffffff, RO=)l'123456
BS at 78 (J110/F @meml, W
, RO, W executed ==> Because of search failure, RO=H
'00000020°VJIa9g=1. @meml =H'ffffffff, RO:H'0O
BSC in 000020) I10/F @mem
Execute l, enemy, RO, W ==> Due to search failure, V
JIag=1. RO remains H' 00000020. RO = H'0OO00040 (carry propagation to higher order)
There isn't. [Program exception] - Reserved instruction exception - When RR = 'll' When φMM = 'll' - When EaR is @-5P - EaM is #imm-data, @SP+, @-5P
Time 12-7. Bill... -le' mouth Δ
BitField, which is one data type of the “device of the present invention”
field is the position of the MSB in the bit field, and
Specified by the bit field length (width)
Ru. The MSB position of the bit field is base and o.
It is shown as a pair with ffset. Notes indicated by base
MSB (0th bit) of ri becomes offset=o
. The meaning of offset is the same as for bit manipulation instructions.
It is. Bitfield and tlaSe-offset
, and the relationship with width is shown in the figure below. [When operating a bit field on memory] As shown in Figure 143, the target bit field is inside the thick line.
It is. Fixed-length bit field manipulation instructions (BFEXT, BFEXTU, BFCMP, BFCMP
U, BFINS. BFINSU) is a tag processing application for A1 (tag ratio
This is particularly effective for comparison and tag extraction). There are two formats for fixed-length bit field instructions:
There is a cut.・Offset is set to 8-bit single-ship addressing mode.
In this format, the width is specified by a register. child
This is called the '20' format. '=G' format
In this case, add the value of offset/8 to base.
determines the memory address to be actually accessed. Bitflow of 28 bits or more
It is also possible to handle bit fields spanning 5 bytes. Specify +1offSet as an 8-bit immediate value
In this format, 1dth is specified as a literal. This is 9:
It is called E' format. In the ′:E′ format,
In order to increase speed by targeting only bit fields that do not cross word boundaries, bits that protrude from one word of base
The operation of the fields is not guaranteed. E even if width + offset≧5ize
IT does not start, but the value does not change when reading or writing.
Becomes indeterminate. Even if only one word of base is accessed,
Since it is possible to realize the order specifications, the operation response can be determined by looking only at the base, regardless of the offset.
It is possible to determine the memory address of the bit field of interest. Therefore, depending on the implementation, it is possible to speed up instruction execution. Addressing allowed in base of 8F:E and BF:G
mode is exactly the same. BFINS, BFINSU, BFCMP, BFCMPU
Now, for each of :G and :E formats,
There are two other formats:・2R former that specifies the src operand with a register
Specify the cut/src operand as immediate: 1
The format widthO value is 1 to 32 ((<LX>> is 1
~64), and O<widt before executing the instruction.
A check is made for h≦32 (64). The case of width-0 is also an error. In case of violation
results in an illegal operand exception (lOE). all
For the command, offset. ν1dth is also treated as a signed number. However, width is originally a value of 1 to 32 (64).
is not allowed, so it can be considered signed or unsigned.
What you think about it does not affect the actual operation, but rather questions about writing specifications.
It has become a problem. Also, :E format command of
fset is also treated as signed, in this case offs
It will represent a number from -128 to +127 as et.
. (However, as described later, in :E format
is one word of the address of base base ~ base
Regarding the bit field that extends from +3,
The operation of the parts that have been added is not guaranteed. ) OF instruction
The non-cut field operand is a plain integer and
be treated as such. Therefore, for example, in the case of 8FEXT, the extracted
The white field is set to the SB side of the register and sign-extended in the MSB direction.
It will be done. bit position = O (MSB)
It's not about setting a field. When targeting a register as base, bit
A field is limited to one register. cash register
Fixed-length bit field instructions for
” to support you. However, this is ((L2〉〉)
There is. This is a bit field intended for registers.
In the case of operation, at this stage, the shift command is preferable to the BF:E command.
It may be faster to execute by combining the command and AND command.
This is because of their gender. Bit field for register
The command (<<L2>>) will be described next in 2G.
: Same as E, extract from l word (register)
Regarding the bit field, the movement related to the protruding part
We do not guarantee the quality of the work. BFEXT, BFEXT
An indefinite value is obtained for Ut', and in BFINS and BFINSU
is ignored. offset + width≧5ize
EIT will not start in this case either. :In E format, the target bit field
Parts with bit offsets exceeding 5ize
Operation is not guaranteed only for Similarly, negative bits
Operation is not guaranteed for parts with offsets.
stomach. In either case, the specified bit field is
By the way, the part included in one word indicated by the base address
It runs correctly. [Example] address N-I N
data B'abcdefgh 8'ij
k1mnopN+1 B'qrstuvwx (a-x: O or 1), BFEXT: E, W #3. Jt9. Liii! N.R.O.
==> RO= B'1mnopqrst and
Become. BFEXT: E, W #-5. #9. @N, RO::>
RQ = 13'77?77ij) (l and
Become. (? is an undefined value) Size specification of width, src, and dest registers
is commonly performed by the X field. size finger
The constant field X supports 32-bit operations and 64-bit operations (
<<LX>>), but the specific
Basically, it has three meanings: ■5rc (dest) register size specification (:R format)
-mat) ■Width register size specification (:G format
) ■ Specifying the width range When X=O Q<width≦32 When X=1(7) Q<width≦64:E:1
In the case of Matsuto, ■■ has no meaning, but the distinction between ■ is fj
To do this, we still use the X field. That is,
The X field increases 32-bit and 64-bit compatibility.
It can be said that it is a bit for holding. =1 format instruction and when SS≠00, #iS
Field 8 is not used. At this time, if #iS8
Even if the field is not zero, it is simply ignored. However, in the manual, the #IS8 field is 0.
Make sure to include the . Format of bit field instructions and their corresponding
If we enumerate the sizes that can be used, they will be as shown in Figure 144.
Ru. Bit field instructions are also the same as bit manipulation instructions.
Similarly, the problem is the range of memory to be accessed.
, there is a strong dependence on the implementation, so it is difficult to establish strong regulations.
I can't. [Detailed specifications are currently being adjusted] [Mnemonic] BFEXT offset, width, base
, dest [Instruction function] extract bit field (signed)
Bit field extraction (signed) [Instruction options] None [Instruction bit pattern and assembler notation] See Figure 145
show. [Flag change] Shown in FIG. 146. [Explanation] Extracts a bit field and sets the result to the destination.
transfer to the Destination than 1dth of bit field
When the size of the data is larger, the data is sign-extended.
. Also, the offset of BFEXT:G is also sign extended.
Ru. In EaRbf addressing mode, @-SP, @
SP+ and #imm-data modes cannot be used. The register direct mode Rn of base is <<L2>>.
However, it is supported by the “device of the present invention”. [Operation] Set the initial value of dest to [DO, Dl, , , Dd-
2,0d-1]d=32.64 The value set to dest is [RO,R1,...,Rd-
2, Rd-1] d=32.84 Offset:: O, Width: W. Offset and width are treated as signed. (An error occurs when dth≦0.width>d) At this time, changes in the bit field and flag of the extracted portion are as follows. (When d≧W) bitO of base ↓ [,,,BO,B1. , , Bo-2, Bo-1, Bo
, Bo+1. ,,,Bo+w-2,Bo+w-1,Bo
+w, Bo+w+1. ,,] sign-extend this part and d
Set to est [Bo, Bo+1. ,,,B
o + enemy - 2, BO + sea 11 ==> [Bo, Bo,,
,,,,,Bo, Bo, Bo+1. ,,,Bo
+w-2゜Bo+w-1 =:> Sign extended by d-w bits [RO, R1, , Rd-1, Rd-shi, Rd-en
+1. ．． ．． ．． ．． ．． Rd-2゜Rd-1] (to dest
(set) (when d<enemy) rThis is a case that cannot occur in the device of the present invention. base bit. ↓ [,,,BO,B1. , , , Bo-1, Bo, Bo+
1. ,,,Bo+w-d-1゜Bo+w-d, ,
, ,Bo+w-2,Bo+w-1,Bo+w, ,
, ] This part will be cut Set this part to dest
Set [Bo, Bo+1, , , . 8o+w-d-1.8
o+w-d, , , , Bo+w-2゜Bo+enemy-
1] ==> [Bo+w-d,,,,Bo+w-2゜BO+Oath-1 Ko
==> This part is cut E RO, , , , Rd-2, Rd-1] (d
, est) MJIag RO or (when d≧W) B. (When d<enemy) Bo+enemy-d ZJlag [RO~d-1co = 0 or (
When d≧W) [Bo~o+w-1] = 0 (When d<w) [Bo+w-d~ o+w-1] = 0 V-f lag☆ S[8o~o+w-1] < -2
-(d-1), or. S[Bo~o+w-1] ≧ +2-(d-1) or
(When d≧-) 0 (When d<w) Clear when Bo=Bo+1= ,,,=Bo+w-d-1=Bo+w-cl
, otherwise set. If it is "device of the present invention" 32, it is always cleared. [Program exception] - Reserved instruction exception ◆ When RR = 'll' - +: When 'θ' When X = 'l' When proboscis EaR is @-5P - EaRbf is #imm-data, @SP+ , @-5
When P: Invalid operand exception ◆Invalid dth≦0. When enemy1dth>32 [Nimoni
] 8FEXTLI offset, width, ba
se, dest [Instruction function] extract bit field (unsigned
d) Bit field extraction (unsigned) [Instruction options] None [Instruction bit pattern and assembler notation] See Figure 147
show. [Flag change] Shown in FIG. 148. [Explanation] Extracts a bit field and sets the result to the destination.
transfer to the Destination than width of bit field
When the size of the file is larger, the data is zero-extended.
. However, the offset of BFEXTU:G is sign extended.
be done. In EaRbf addressing mode, @-5P. The O5P side m-data mode cannot be used. The register direct mode Rn of base is <<L2>>.
However, it is supported by the “device of the present invention”. [Initial value of operation code dest [:DO,Dl,...,Dd
-2,0d-1]d=32.64 dest is set to [RO,R1,...,Rd-
2, Rd-1]d=32.64, offset=o, width=w. o
ffset and %didth are treated as signed. (An error occurs when 1dth≦O, width >d.) At this time, changes in the bit field and flag of the extracted portion are as follows. (When d≧enemy) Base bit. ↓ 1,,,BO,B1. , , Bo-2, Bo-1, Bo
, Bo+1. ,,, Bo+v-2 Zero extend this part, Bo+w-1, Bo+w, Bo+w+1 ,,,]
and set it to dest [Bo, Bo+1. ,,,Bo+w-2,8o
+w-1] ==> [1 - 22 workers, 0. Bo,
Bo+1. ,,,Bo+! -2゜Bo+B-11=
=> Zero-extended by d-w bits [RO, R1, , Rd-en-1, Rd-en, Rd-en
+1. ．． ．． ．． ．． ．． Rd-2゜Rd-1 (set at dest)
(When d<v) This is a case that cannot occur. base bit. ↓ [,,,BO,B1. , , , Bo-1, Bo, o+
1. ,,, Bo+w-d-1° This part is cut [Bo, Bo+1. ,,． 8o+w-d-1. Bo+w
-d,,,,Bo+w-2゜Bo+w-1] ==> [Bo+w-d,,,,Bo+w-2゜Bo+B-1]
==> This part is cut [ RO, , , , Rd-2, Rd-11 (de
town flag RO or (when dew) 0 (when d=w) B. (When d<w) Bo+! -d Zjlag [RO-d-1ko = 0
is (when d≧enemy) [BO~0+defense-1ko = 0 (when dew) [Bo+v-d~ o+w-1ko: O VJIag☆ U[Bo ~o+w-1ko ≧
+2″d or (when d≧enemy) 0 (when d<w) Bo=Bo+1= , , , =Boenemy−d−1=O, clear, otherwise
Set if outside. If it is "device of the present invention" 32, it is always cleared. [Program exceptions] - Reserved instruction exception - When RR = 'll' - When + = '0' - When -X = '1' - When EaR is @-5P - EaRbf is old mm-data, @SP+ , @-5P
When ・Illegal operand exception・When 1dth≦O, width>32 [Nimoni
] BFINS src, offset, width,
base [Instruction function] 1nsert bit field Insert bit field (signed) [Instruction options] None [Instruction bit pattern and assembler notation] Figure 149
show. [Flag change] Shown in FIG. 150. [Explanation] Inserts the source value into a bit field. The width of the bit field is smaller than the source size.
When the value is larger, the data is sign-extended. Also, BF
The offset of INS:G is also sign extended. In EaRbf addressing mode, I knee SP. @SP+ and #imm-data modes cannot be used.
. The base register direct mode Rn is <<L2>>
However, it is supported by the "device of the present invention". [Set the initial value of operation code src to ISO, Sl, , , ,
5s-2, 5s-118 = 8.16, 32.64 (:I
) s=32.64(:R) offset=o, width=w. o
Both ffset and width are treated as signed. (An error occurs when width≦0.1dth>d) At this time, changes in the bit field and flag of the inserted portion are as follows. (When B≧S) Bit field change base bit. ↓ [,,,BO,B1. , , Bo-1, Bo, Bo+1
．． ,,,Bo+enemy-8-1゜Bo+w-s, Bo+w-
s+1 ,,, ,Bo+w-1,Bo+w, ,]]
==> [,,,BO,B1. ,,,Bo-1,50,SO,,
,,,,,,,5O0So, Sl,,,,,
, 5s-1, Bo + enemy src is sign expanded by W-S bits.
It is stretched. ,,]] (when w<s) Bit field change base bitO ↓ [,,,BO,B1. , , Bo-2, Bo-1, Bo
, Bo+1. ,,. Bo+Ero-1, BO+ν01. ]ko ==> [:,,,,
BO, B1. , , Bo-2, Bo-1, Ss-shi, 5
5-w+1. ．． ．． ．． ．． . 5s-1, Bo+w,,,ko] src's C5O, Sl,..., 55-w-11 is cut
be done. Town flag MSB (B
Based on the change in o). Or (when enemy≧S) 5O (when -kuS) Ss-ZJIag Target bit field [Bo~o+
w-1] is the standard. Or (when enemy ≧ S) [SO~ s-1 co = src = 0 (when w<s) [Ss- enemy ~ s-1 co = O V-flag☆ S [SO ~ s-1 co: :
SrC<-2-(enemy-1), or. S[SO~s-1] = src ≧ +2″′(%
, 1-1) or (when w≧S) 0 (when -xs) 5O=S 1=, , , =Ss-enemy-1 knee 1=SS-Surya,
Set otherwise. [Program exception] - Reserved instruction exception When RR = 'll' - When + = '0ゝ - When X = 'l' - When SS = 'll' When fist EaR is @-5P, φEaMbf #imm-data, @SP+, @-5
When P/Illegal operand exception contention width≦0, width>32 [Nemo
Nick] BFINSU src, offset, width
, base [Instruction function] 1nsert bit field Insert bit field (unsigned) [Instruction options] None [Instruction bit pattern and assembler notation] Figure 151
show. [Flag change] Shown in FIG. 152. [Explanation] Inserts the source value into a bit field. The width of the bit field is smaller than the source size.
If the value is larger, the data is zero-extended. On the other hand, BF
The INSU:G offset is sign extended. In EaRbf addressing mode, @-5P. @SP 10 m-data mode cannot be used. The register direct mode Rn of base is <<L2>>.
However, it is supported by the “device of the present invention”. [Operation] Set the initial value of src to [SO, Sl,..., 5s-2
, 5s-11s=8.16,32.64(:1) s=32.64(:R) offset=o, width=w. o
Both ffset and width are treated as signed. (An error occurs when 1dth≦0.1dth>d) At this time, changes in the bit field and flag of the inserted portion are as follows. (When enemy≧S) Bit field change base bit. ↓ [,,,BO,B1. , , Bo-14o, Bo+1.
,,,Bo+enemy-5-1゜Bo+w-s, Bo+w-s
+1. , , Bo+w-1, Bo+w00. ko]==
> [,,,BO,B1. ,,,Bo-1,0,0,,,,
,,,,,,0゜So, Sl,,,,,,5
s-1, Bo+νSrC is sign extended by W-S bits.
]] (When w<s) Bit field change base bitO ↓ [:,,,BO,B1. , , Bo-2, Bo-1, B
o, Bo+1. ,,,B. +-11. Bo+w,,, here ==> [:,,,BO
, B1. ,,,Bo-2,Bo-1,55-w,55-
w+1. ,,,,. 5s-1, Bo+w,,, here src's [SO, Sl,..., 55-w-1] is cut
be done. MJIag MSB (Bo
) is the standard. Or (when WaS) 0 (when w=s) SO (when -S) Ss-w ZJlag Target bit field [Bo~o+w
-1] is the standard. Or (when W≧S) [50~s-1] = src = 0 (when S is hostile) [5s- W-%-5-1] = O V-flag☆ U[SO~s-1 ] = src≧
Cleared when +2″w or (when W≧S) 0 (when WaS) 5O=51= ,,, =Ss-!-, and set otherwise. [Program exception] - Reserved When instruction exception number RR='ll' When +='0' When x='t' When φSS='ll' When EaR is @-5P When EaMbf is #imm-data, @ SP÷, @-5
When P/Illegal operand exception/When width≦0, width>32 [Nimoni
]゛BFCMP src, offset, width,
base [Instruction function] compare bit field (signed)
Comparison of bit fields (signed) [Instruction options] None [Instruction bit pattern and assembler notation] See Figure 153
show. [Flag change] Shown in FIG. 154. [Explanation] Compare the source 5rcO value and the bit field value. Source size and bitfield width. If the values are different, the data with the smaller size is
Sign-extended before comparison. Also, the offset of BFCMP:G is also sign extended.
. In EaRbf addressing mode, @-5P. @SP+ and #imm-data modes cannot be used.
. The register direct mode Rn of base is <<L2>>.
However, it is supported by the “device of the present invention”. [Operation] Set the initial value of src to ISO, Sl,..., 5s-2
, 5s-1 s = 8.16, 32.64 (: I) S = 32.64 (: R) Offset = o, width = w. o
Both ffset and width are treated as signed. (An error occurs when 1dth≦0.1dth>d) At this time, changes in the bit field and flag of the compared portion are as follows. (When S≧enemy) Base bit. ↓ [,,,BO,B1. , , Bo-2, Bo-1, Bo
, Bo+1. ,,,Bo+w-2,Bo+w-1,Bo
+w, Bo+w+1. ,,] sign-extend this part to s
Compare with rc (when 9<enemy) bitO of base ↓ [:,, ,BO,B1. , , ,Bo-1,Bo,
Bo+1, , Bo+w-s-1. Bo+w-s, , Bo+w-2, Bo+w-1, B
o+w, , sign-extend src and compare it with this part.
LJIag S[:Bo ~o+v-1ko
- S[5O-s-1k0 Set by comparison result. ZJlag S[Bo-o+w-1]-5[SO
~5-11=0 Set by comparison result. [Program exception] - When reserved instruction exception number RR = 'll' - When + = 90' - When - = '1' - When SS = 'll' ◆ When EaR is @-SP, φEaRbf is # imm-dataJSP+, [i! −
5P Nodoki/Illegal Operand Exception/Enemy1dth≦0. When enemy1dth>32 [Nimoni
] BFCMPU src, offset, width
, base [Instruction function] compare bit field (unsigned
d) Comparison of bit fields (unsigned) [Instruction options] None [Instruction bit pattern and assembler notation] See Figure 155
show. [Flag change] Shown in FIG. 156. [Description] Compare the value of the source src and the value of the bit field. The source size and bit field width value are
If they are different, the data with the smaller size will be zero.
Expanded and then compared. On the other hand, the offset of BFCMPU:G is sign-extended.
Ru. In EaRbf addressing mode, @-SP. @5P+ and $limm-data modes cannot be used.
stomach. The register direct mode Rn of base is <<L2>>.
However, it is supported by the “device of the present invention”. [Initial value of operation code src [SO, Sl, , 5s-2]
, Ssi s = 8.16, 32.64 (: I) s = 32.64 (: R) offset = o, width =: w. Both offset and width are treated as signed.
. (An error occurs when width≦O, width>d.) At this time, changes in the cut field and flag of the portion to be compared are as follows. (When S≧luxury) Base bit. ↓ [,,,80,81,,,,Bo-2,Bo-1,Bo
, 8o+1. ,,,Bo+v-2,Bo+w-1,Bo
+w, Bo+w+1t+t Expand this part by zero and s
Compare with rc (when s<-) Base bit. ↓ [,,,BO,B1. , , , Bo-1, Bo, Bo+
1. ,,,Zero-extend Bo+w-s-1,8src
L-flag tJ[8o
~o+w-1]-U[SO~s-1koku0 Set by the comparison result. Zjlag U[Bo~o+w-1] -U[
SO~s-1]=0 Set by the comparison result. [Program exception] - Reserved instruction exception - When RR = 'll' - When +: '0' - When - = 'l' - When SS = 'l!' - When EaR is @-5P - EaRbf is #imm-data, @SP+, @-5
When P・Illegal operand exception・When width≦O, width>32 2-8.
Bit file of arbitrary length
Field operation commands include the following. General operations and transfers BVMAP transfers evcp repeat pattern
Turn calculation and transfer BVPAT O or 1 search BVSCBVMAP
, BVPAT, BVCPY are bitmap
Mainly window operations on the display (bitblt)
This is a command with a purpose. For explanation, about the attributes of bitmap display.
Define terms. (color 5cale, color offset
and bit-dat polarity)*color 5cale: How many consecutive bits represent 1 dot? Example: <color 5cale == 1>1 bi
t is 1dat, 8 consecutive dots in 1 byte. Black and white bitmap display. Or, each bit making up cofor is made into a bank.
Bitmap display. <color 5cale = 4> 1 dat in 4 adjacent bits, 2 consecutive bytes
dat. Bit map display with 16 colors.・bit-dat polarity This is the combination of bitmap display and processor.
This is a concept that arises for combinations. small address
A general bitmap day where the side is displayed on the left side
In the spray, dots corresponding to small bit numbers
If it also appears on the left side, then the bitmap day like this
The spray is said to have positive bit-dat polarity. Also, the opposite is said to have negative bit-dot polarity.
. In other words, in a big-endian processor, M
Positive bit if S8 bit is displayed on the left
It will have dat polarity.・color offset 1 Number of bits among the multiple bits that make up the dot
The question is whether to operate the . 0≦cofor offset <color 5c
The relationship ale holds true. This is an attribute of bitmap display hardware.
rather than the bitmap display operating parameters.
It is ta. From the dot corresponding to base address, horizontally
A dot displaced by X (dat offset) in the direction
When operating, the bit offset on that memory is
It is calculated as follows. (dat offset is the concept of a point on the screen, bit
Offset is a concept of bits on memory. ) When positive bit-dat polarity bit offset = X color 5 cal
e + coloroffset When negative bit-dat polarity bit offset = (X color 5ca
le + coloroffset), xor, 7 By the way, the actual BVMAP of the device J of the present invention. For BVCPY and BVPAT instructions, the implementation
Consider the following restrictions and use only in the following cases.
It is now possible to do so.・Bit-dat polarity is positive ・Color 5cale is 1 Therefore, the bitmap display hardware is
It is unavoidable to stipulate it to some extent. The specific restrictions are
It will look like this:・Because the bit-dat polarity is positive,
When set to big-endian, the small address
The lower bit number (MSB) is on the left side of the screen.
must be displayed.・Color 5cale = 1 only, so col
or 5cale≠1 bitmap display
There are the following restrictions: Bit map display with color 5cale≠1
In this case, the type of operation can be changed for each color offset.
You will not be able to grow. Change color 5cale with BVMAP command
Since it is not possible to use the bitmap display co.
When lor 5cale is not ■, the internal representation is also the same
If you do not set the color to 5cale, the BVMAP command will not work.
,Not available. In that case, the internal representation of the screen image is
other hardware.
When transferring data between
is required. Arbitrary length bit field manipulation instructions have many operands,
The execution time is also long. Therefore, interrupt reception during execution is
There is a need for a mechanism for attaching and re-execution after processing an interrupt.
be. rThis invention device" specifies operands and performs calculations.
uses a fixed number of registers to represent the progress of
ing. Therefore, while executing an arbitrary length bit field instruction
Even if an interrupt occurs, the interrupt handler
If registers are saved and restored correctly, the
The bit field instruction is restarted from the middle after the
Can be opened. Saving the state or switching the context after execution is interrupted
or switch to another program after a context switch.
Execute the same bitmap instruction in the process and return to the previous context again.
Assuming you return to the text and resume the previous bitmap instruction.
It must also work without problems. Also, according to the BTRON specifications, ordinary
Characters and figures are also drawn to the main memory.
Sometimes. Therefore, an arbitrary length bit field
Page faults may occur even when the
Similar to programming instructions, execution can be interrupted due to page faults.
must also be able to deal with it. In the BVMAP and BVCPY instructions, insert
Thinking about moving the shape horizontally using a bit machine etc.
Overlap of source and destination
It is also possible to respond. Specifically, the string
As with programming instructions, the direction of the operation is determined by the option in the instruction.
/F, /B. by software
Determine the appropriate direction and make sure the destination breaks the source.
Proceed with the calculation so as not to destroy it. However, the implementation
Option/B that specifies processing in the opposite direction considering the burden on
is <<L2>>. In order to speed up the operation of BTRON in the "device of the present invention"
It also supports backward processing. If src and dest overlap, sr
baS of dest than base ~ offset of c
If e~offset is smaller, then offset is smaller.
dest destroys src by processing from the
You can proceed with the process without damaging it. for this purpose
Use the /F option. Pairing screen and bitmap
In response, the one with the smaller offset (address) is usually on the left.
Become. Therefore, the base of dest than SrC
~offset is smaller because of deletion of characters.
When trying to move bitmap data to the left by
It is. Also, dest from base~offset of src
If base~offset of is larger, then offset
By processing from the larger et, des-t becomes
Processing can proceed without destroying src. Use the /B option for this purpose. d than src
est's base -offset is larger.
moves the bitmap data to the right by inserting characters, etc.
It was time to move. If there is a possibility that src and dest overlap,
If so, the software determines the correct option.
and proceed with the operation so that dest does not destroy src.
It is necessary to However, the /B option is <<L2>
>, so if /B cannot be used, s
Copy rc to another location and then calculate with dest
must be carried out. If there is no overlap, select either option.
No matter how you use it, the result remains the same. Here, the problem is base -offset of dest
If you use the /B option even though d is smaller, or
est's base~offset is larger/F
What happens when you use options
That's what it means. Basically, the part where the calculation has already been completed
The dest of src is the unreferenced part of src.
Since it becomes destructive, correct results cannot be obtained. deer
However, at this time, the instruction is interrupted midway due to the algorithm.
The results may change if you try again.
Ru. Because it does not guarantee correct results in the first place.
, it doesn't matter if the result changes due to execution interruption.
However, if there was no interruption in execution, the correct result would be obtained.
It is easy to introduce bugs that cannot be reproduced.
It becomes a situation. However, if you do not perform this error check properly,
This increases overhead and reduces execution time.
Therefore, no error checking is performed. Notes on the user's side
It requires a lot of will. Arbitrary-length bit field instructions use bits on a register.
offset, bit width
, as the size of pattern data pattern, 3
Only 2 bits or 64 bits <<L×>> can be used.
Ru. 8 and 16 bits are not specified. The selection of 32-bit and 64-bit register size is
Commonly done by field. dest side of BVMAP, BVCPY, BVPAT instructions
For memory access methods, write or r
Especially since it is ead-modify-write.
Not specified. If width≦0 in the BV command, - means execute without doing anything.
The order will be terminated and will not be considered an EIT. At this time, BVSCII
The instruction uses VJlag (search
(same as failure) is set. This is an eV command or a strike command.
In the case of high-function instructions such as ring instructions,
Furthermore, highly functional subroutines are often created, and check
I think that if it is necessary, it can be done in that subroutine.
This is because For example, if it is BVMAP, then
Create a BitBlt function by repeating as many times as the number of lines.
There are many cases, and in that case all wickjth will be common.
, there is no need to check the width every time. On the other hand, B
The compiler may directly generate instructions such as the F instruction.
It is necessary to check the code as strictly as possible.
be. Therefore, the width of the BF instruction is detected by exception.
I try to do that. offset+widt with arbitrary length bit field instruction
If h overflows, the instruction by interrupt
offs on the register when execution is interrupted and when the instruction ends
ET value becomes a strange value and normal command execution is not possible.
It becomes. In this case, operation is not guaranteed. a
Architecturally, this is detected at the start of instruction execution and an error occurs.
It is preferable to use positive operand exception (IOE), but check
The execution time will increase due to checking, so please do not check.
shall be carried out. (In addition, in the case of string instructions,
, offset is not an integer but a pointer.
Since it is a dress, it is not treated as an overflow.
Instead, the address simply wraps around. ) [Mnemonic] VSCH [Instruction function] find first 'O' or '1' in
the bitfield (variable len
gth) Search for 0 or 1 (arbitrary length bit field) [Instruction
Options] 10 Search for '0'(default)/1'
Search for 1' /F Search in the direction of increasing bit number (default) /B Search in the direction of decrease in bit number <<L2>>
(Supported by the device of the present invention) [Instruction bit pattern and assembler notation] Figure 157
show. [Flag change] Shown in FIG. 158. [Explanation] +0' or +1 in a bit field of arbitrary length
′ bit. Bit number to start search (bit offset)
Set this command to the offset operand (R1).
When the instruction is executed, the bit number of the search result is displayed after the instruction is executed.
is set in the offset operand (R1)
. In other words, offset is read-nodify-
Write and write. This repeats the search for bits.
This is because we assumed that we would do it again. offset is treated as a signed integer, and its value can be arbitrary.
I mean it. If the search fails as a result of executing BVSC)I,
sets Vjlag, offset then searches
Indicates the bit to be done. EIT does not start. BVSC) How to change the I instruction offset and V-flag
The law is in accordance with the BSCH Order. The backward search by 7B has the <<L2>> specification.
However, the device of the present invention supports this. This instruction is used to search for free blocks on disk or memory.
It is intended for use in Note that arbitrary length bit field instructions and string instructions
Detailed specifications of which high-function instructions and register values after instruction completion
Please refer to Appendix 11 for details. [Program exception] - Reserved instruction exception - When + = '0' - When x = 't' - When P = 'l' [Mnemonic] VMAP [Instruction function] Bit operation (one 1ine Bi
tBIt) Bitmap operation [Instruction option] /F Process from the smaller offset (default)
default) /B Process from the one with the largest offset<<L
2>> (Supported by the device of the present invention) [Instruction bit pattern and assembler notation] In Fig. 159
show. [Flag change] Shown in FIG. 160. [Explanation] To perform bitmap operations on the screen, select
Various bit fields src and dest of length
This is an instruction that performs logical operations. The type of operation is the lower 4 of R5
It is specified in bits, and the following 16 types are available. T True ==> destF
False O==> destND
NotDest -dest ==>dest D Dest dest ==>des
t NS NotSrc ”'src ==>d
est S Src src ==
>dest A And dest, an
d. src ==> dest OOr dest , Or. src ==> dest
xor. SrC==> dest NA NotAnd -dest, and
. src ==> dest NONotOr - dest, or. src ==> dest AN AndNot dest, a
nd. src ==:> dest ON 0rNot dest, or
. -5rc ==> dest NAN NotAndNot -dest, an
d. ”'src ==> dest NON NotOrNot -dest,or
. -5rc ==> dest NX NotXor -dest, xor
. src ==> dest Among these, the operation mode of D (Dest) is due to symmetry.
It is set in. Mnemonic and actual bit pattern
Please refer to the appendix for correspondence. If the upper bit of register R5 that specifies the operation is not 0,
In this case, no particular check shall be performed. however
, even if no check is performed, the upper bits are
Instruct them in the manual etc. to insert the
It is necessary to Do not mark it as an illegal operand exception (IOE)
is a heavy implementation burden and affects execution speed.
This is because /F and /B options start with the smaller offset.
processing, or processing from the side with the larger offset.
specify. This means that the bitmap's src and dest are
Clarify the direction of processing when there is overlap.
Otherwise, dest will destroy src and the result will be correct.
This is because it cannot be obtained. If SrC and dest overlap, sr
base of dest than base~offset of c
~If offset is smaller, then offset is smaller.
By processing from the beginning! 3t src
Processing can proceed without destruction. this purpose
Use the /F option. between screen and bitmap
Correspondence is usually that the smaller offset (address) is on the left side.
become. Therefore, base of dest than src
-offset is smaller due to deletion of characters, etc.
When trying to move the bitmap data to the left by
be. Also, des from base ~ offset of SrC
If base~offset of t is larger, off
By processing from the larger set, dest becomes
Processing can proceed without destroying src. Use the /B option for this purpose. d than src
The base ~ offset of est is larger.
The bitmap data is moved to the right by inserting characters, etc.
It was time to move. Note that base to offset of dest is smaller.
If you use the 7B option, or if the dest's ba
Even though se~offset is larger, use the /F option.
If used, the result (dest) is not guaranteed.
shall be. In particular, in such cases, interrupts may occur during instruction execution.
An instruction re-execution occurs due to an error such as an error or a page fault.
However, the results may vary. If there is a possibility that src and dest overlap,
If so, the software will use its judgment to select the correct option.
and proceed with the operation so that dest does not destroy src.
It is necessary to However, the /B option is <<L2>
>, so if /B cannot be used, S
Copy rC to another location and then calculate with dest
must be carried out. rThe device of the present invention"/B
Options are supported. If there is no overlap, select either option.
No matter how you use it, the result remains the same. +base-offset is small base ~
The offset is large → [no overlap] as shown in FIG. 161. [With overlap - base of dest ~off
set is small] shown in FIG. 162. [With overlap-dest base-offs
et is shown in Figure 163. [Program exception] - Reserved instruction exception - When Q = 'l' - When x = 't' - When P = 'l' [Mnemonic] VCPY [Instruction function] bit transfer Bit map transfer [Instruction option] / Process from the smaller F offset (default)
default) /B Process from the one with the largest offset<<L
2>> (Supported by the device of the present invention) [Instruction bit pattern and assembler notation] In Fig. 164
show. [Flag change] Shown in FIG. 165. [Explanation] To perform bitmap operations on the screen, select
All transfers between long bit fields src and dest are
This is a command to This instruction performs an operation from the eVMAP instruction.
Even if you remove the function and limit it to transfer only, you can improve the speed.
It is. /F and /B options have the same meaning as BVMAP.
be. Bitmap src and dest overlap
If not, neither option will change the result.
However, if SrC and dest overlap
The software will use the correct option at its discretion.
and proceed with the calculation so that dest does not destroy SrC.
It is necessary to /B option, offset to be put in R1, R4
The value is the maximum bit field to be transferred.
Specify an offset value of +1. This corresponds to the specifications of 5M0V/B and SCMP/B.
I thought about it. The /B option is <<L2>>.
However, the device of the present invention is supported. [Program exception] - Reserved instruction exception ◆ When Q = 'l' - When X = 'l' - When P = 'l' [Mnemonic] VPAT [Instruction function] Cyclic bit operation pattern and
Bitmap operation [Instruction options] None [Instruction bit pattern and assembler notation] Figure 166
show. [Flag change] Shown in FIG. 167. [Explanation] Filling the bitmap on the screen with a certain pattern
, calculates a bitmap on the screen and a certain pattern.
This is a command to be used when you want to do something. pattern
is generated repeatedly, and the logical operation with the bit field is performed.
Do calculations. If the upper bit of the operation specification (R5) is not O, it is simply ignored.
shall be monitored and no particular checks shall be performed. However, even if the check is not performed, future expansion
Therefore, be sure to put 0′ in the upper bit.
It is necessary to provide guidance through manuals, etc. rogue operan
Not making it a code exception (IOC) is a burden on the implementation.
This is because the processing speed is large and the execution speed is affected. This instruction, unlike BVMAP and BVCPY,
Do not shift when loading. Specifying offset
simply clips the pattern. (
On the other hand, in the BVMAP instruction, src and dest
If the offset of
[Program exception] ・Reserved instruction exception Red When +=20' When ΦX='l' ・When P='l' 12 9, 10"a" For decimal operations, ED is added to unsigned PAC. Format (B
Addition and subtraction of 1 word of lO base number of CD) and /UN to PAC
Processing to PAC with the <(Ll>> specifications of the main processor)
and supports signed PACKED format decimal numbers.
Addition and subtraction of one word is supported as (<L2>> specification).
Ru. Additionally, addition, subtraction, multiplication, and division of multi-digit decimal numbers can be done using a coprocessor.
Let's do it. Among these, in this chapter, we will use unsigned PACKED format lO base number.
Explain the addition/subtraction and PACK/UNPACK processing.
17 Now. Supports EO format decimal numbers for signed PACs
(The <L2>> command will be explained in a later chapter.)
The addressing mode for decimal operations is general.
It is the same as the command. The device of the present invention supports the four types of decimal operation instructions described in this section.
No port. [Mnemonic] ADDDX src, dest (with the device of this invention)
(Not supported) [Instruction function] dest + src + X-flag ==> d
est BCDB Addition of BCD [Instruction options] None [Instruction bit pattern and assembler notation] In Figure 168
show. [Flag change] Shown in FIG. 169. [Explanation] Adds the backed up BCD. 8 bits (2 digits), 16 bits (4 digits), 32 bits (
8 digits) and 64 bits (16 digits) BCD data.
I can do it. However, 64 bit is <<LX>> specification.
be. The size of the source operand is the size of the destination operand.
source is zero-extended.
and then added. Sign extension is meaningless for BCD numbers, so basically the sign
Considering the number of none, the flag change of ADDDX becomes ADDU.
The same shall apply. Vj when the result is not in dest
lag is set, and when DOS, dest support is set.
The carry from is is set to X-flag,
etc. are similar to ADDU. However, unlike ADDU, Z-f lag is ADD
It changes cumulatively like X, 5UBX. Each digit of src and dest contained a number other than 0 to 9.
In other words, the operands of ADDDX and 5UBDX are B
If a CD fails, it will not be an EIT, but it will be de
The results set in st and flags cannot be guaranteed (imp.
). It is the implementation that does not mark it as an illegal operand exception (IOC).
This is because the burden on management is large and execution speed is affected.
Ru. [Program exception] - Reserved instruction exception - When RR = 'll' - When MM = 'll' - When EaR is @-5P - EaM is #imm-data, @SP+, @-5P
When: <<l l>>Functional exception: The correct bit pattern of ADDDX is decoded.
Time [mnemonic] 5UBDX src, dest (with the device of the present invention)
is not supported) [Instruction function] dest -' src -XJIag ==> de
st BCDlO decimal BCD subtraction [Instruction options] None [Instruction bit pattern and assembler notation] Figure 170
show. [Flag change] Shown in FIG. 171. [Explanation] Performs subtraction of packed BCD. 8 bits (2 digits), 16 bits (4 digits), 32 bits (
8 digits) and 64 bits (16 digits) eco data.
I can do it. However, 64 bit is <<L×>> specification.
be. The size of the source operand is the size of the destination operand.
source is zero-extended.
and then added. Sign extension is meaningless for BCD numbers, so basically the sign
Considering the number of none, the flag change of 5UBDX becomes 5UBU
The same shall apply. When the result is negative, VJlag
be set, from the size of dest when dos
It is also 5u that the lower digit is set to XJlag, etc.
Same as eu. However, unlike 5UBU, Z-
The flag changes cumulatively like ADDX, 5UBXO)
Ru. If the result is negative in 5UBDX, dest is
It is not a logarithmic representation but a complement representation (10's complement). did
Therefore, if dest is carried down from the upper digit,
It has the same value as the Example = When executing 5UBDX with 16 bits dest
5rc 0123-0456 = (-0333) dest is (
-333) = 9667. Each digit of src and dest contained a number other than θ~9
If A[1()[IX, 5tJBOX's O
If Pelland was not BCD, it would not be EIT.
However, the results set in dest and flags cannot be guaranteed.
(It is implementation dependent). It is not an illegal operand exception (IOE) because the implementation
This is because the burden on management is large and execution speed is affected.
It is. [Program exceptions] - Reserved instruction exception - When RR = 'll' - When MM = 'll' - When EaR is dead SP - EaM is #imm-data, fi! SP+, @-5
When P・<<Ll>>Functional exception・Correct bit pattern of 5uaox was decoded
When [mnemonic] ss src, dest to PAC (this invention device
) [Instruction function] pack string 1nto BCDB To BCD
Pack [Instruction options] None [Instruction bit pattern and assembler notation] For the 172nd country
show. [Flag change] Shown in FIG. 173. [Explanation] Convert SrC to BCD (Binary Coded Deci)
mal) and transfer it to dest. in fact,
SS contains the letters B, H, W, or L, as shown below.
Una mnemonic and operation. IIB src[, lIco, dest[,
B] RR=01. 4=OOsrc[04:07]==>
dest[:00:03]. src[12:15 ==> dest[04:07] PAC Hsrc[,W], dest[,H]
<<L2>>RR=10. 4=01 sr
c[04:07ko ==> dest[00:03]. src[12:15] ==> dest[04:07] src[20:23] ==> dest[08:11]. src[28:311 ==> dest[12:15 PACKWB src[:,W], dest[,B
CoRR=10. WW=OOsrc[12:15ko==>
dest[oO:03]. src[28:31 ko==> dest[04:07] PACKLW src[,L], dest[,enco
<(LX>>PACKLII src[,L]
, dest[, H co <<LX>>In addition, PACKs
s, UNPKss, due to the difference in size Nemo
The reason why even the nicks are changed is due to the difference in size.
This is because the meaning itself is thought to change considerably. One
However, in general instructions, zero expansion is required due to the difference in size.
However, PACKss, U
In NPKss, the instruction operation itself is quite different.
ing. PACK, UNPK, unreasonable not included in the above explanation
Operation is guaranteed if you specify an introduction of a certain size.
No (implementation-dependent value is set to dest)
shall be). Architecturally reserved instruction exception
(RIE), but the two operands
Reserved instruction exception (RIE) can be generated depending on the size combination.
Detection is a heavy burden on the implementation, so it is reserved.
It is not treated as an instruction exception (RIE). This is between different sizes
The same applies to the logical operation of . Fields in src that do not affect dest
For bits 2-7 to 2″4 of PACK118)
does not check whether it is 0 or not, and even if it is not 0,
ignore. Consider the case where the character code is packed as is.
However, it is more likely that it is not 0. [Program exception] - Reserved instruction exception - When RR = 'll' - When enemy = 'll' - When EaR is @-5P - When EaW is #imm-data, @SP 0 - <<
l l>>Functional exception/PACKss correct bit pattern is decoded
When [Mnemonic] UNPKss src, dest, adj (book
(Not supported by the invention device) [Instruction function] unpack BCD Unpack from BCD [Instruction option] None Shown in FIG. 174. [Flag change] Shown in FIG. 175. [Explanation] BCD (Binary Coded Decimal)
src is unpacked and the unpacked value is supplemented.
A positive value adj is added and transferred to dest. Correction value adj
is added directly to UNP by command.
This is because it is generated by . Addition of adj is not BCD.
This is binary addition. The size of adj is dest
It is specified by four fields in common with the size. Actually, SS has the letters B, II, W, or L.
The mnemonic and operation are as follows. Shown in FIG. 171. Non-compliance with PAC and UNP that is not included in the above explanation.
If you specify a reasonable size combination, the operation will be maintained.
(implementation-dependent value may be set in dest)
shall be determined). Architecturally reserved instruction example
(RIE), but two operands
Reserved Instruction Exception (RIE) depending on the size combination of
Since detecting the
It is not considered a Recommended Instruction Exception (RIE). Overflow due to addition of adj is ignored. [Program exception] - Reserved instruction exception - When RR = 'll' - When enemy = 'll' - When EaR is @-5P When φEaIIJ is #imm-data, @SP0 -
<<l l>>Functional exception/UNPKss correct bit pattern is decoded
12-10. 1' Association Δ "String" means 8 bits, 16 bits, 32 bits.
continuous bits or 64-bit data for any length.
It is a data type arranged by (5SC) Only for l commands, they fly not continuously but at regular intervals.
It also supports aggregation of data at discrete addresses.
Ru. ) The meaning of each piece of data is not determined in particular;
code, integers, floating point numbers.
There are cases where This is for the user to interpret. There are two ways to indicate the range of a string: ・Specifying the length of the string (number of data) ・Specifying the character (terminator) that indicates the end of the string
There are two ways to do this, and you can choose the most appropriate one depending on the purpose of use and language.
You need to choose. In the string instruction of the device of the present invention,
The number of data in the string is a parameter, but
gives a terminator in the form of an optional exit condition to
Both specification methods are supported. One of the features of the string instruction of the device of the present invention is that the point
One of the advantages is that you can freely set the increase or decrease of data.
Ru. Therefore, the string search instruction (SSCH instruction)
You can also use it to search tables and scan multidimensional arrays.
can become. Furthermore, in the device of the present invention, the string command is 5M0V. SCMP, 5SCH termination conditions include size comparison and two
You can specify a wide range of conditions including value comparison, which is another great feature.
It becomes. Among the string instructions, the string server
The 5SCH command for
Therefore, the command has meaning only in the termination condition.
Ru. Inventor! Conditions that can be specified with the string command (e
eee), see the appendix. With the device of the present invention
is the <<L2>> specification, the termination condition 0UTU-
ZE is not supported. The use of string instructions is literally 8716 bits.
In addition to those that process strings of
search for blocks, transfer blocks of memory, assign structures,
It has applications such as clearing memory areas. String instructions are the same as arbitrary length bit field instructions.
Since data of undefined length is handled, interrupt reception and execution during execution are
Line restart functionality is essential. On the other hand, the string instruction itself
The body is almost always code generated by the compiler.
instead, they are provided as subroutines written in assembler.
Often. Therefore, symmetry and addressing
Restrictions on the code are less of a problem. Therefore
Therefore, in the string instruction of the device of the present invention, operands and actual
Fixed number registers (RO~
R4) is now used. How to use main registers
becomes as follows. RO: Start address of source string R1: Start address of destination string
Dress R2: String length, number of data R3:
Comparison value of end condition (1) R4: Comparison value of end condition (2) Of these, R2, which represents the length of the string, is the element
It's a number, not a number of bytes. R2 is an unsigned number
If R2:0, it is treated as an instruction based on the number of elements.
Termination is interpreted to mean no termination. In other words,
If you want to avoid termination due to the number of elements, set R2=0.
All you have to do is execute the command. implement
Above, the execution pattern of the string instruction is as follows
is common. do (R2-1==>R2;check-interrupt;'1 while (R2!=O); However, when R2=0, the number of elements is H'
Think 100000000 or infinity (number of elements
It is up to the implementation
Depends on. In other words, H'l00000000 times
If the instruction is not completed even after performing the ment operation,
The subsequent operation is implementation dependent. However, if the instruction is terminated due to factors other than the number of elements.
In this case (which usually happens when R2=O), the instruction ends.
The following R2 value (see Appendix 11) is set correctly.
There must be. Actually, R5=0 with 5SCH/R
+1 ' 10 except for special cases such as specifying
0000000 element operations
bus conversion exception (ATRE) and bus access exception (BAE)
This usually causes the command to be interrupted. String instructions terminate due to various reasons, so
A flag is used to distinguish between them. each flag
The meaning of is as follows. Vjlag Depends on number of elements (string length)
Termination Fjlag Termination according to termination condition (eeee)
Mjlag is used to distinguish between multiple termination conditions. Please refer to the appendix for changes in ``1a8.'' For SCMP, 5SC) I, where there is no other termination factor,
The changes in VJlag and F-flag are complementary. S.C.
In the case of MP, in addition to this, due to discrepancies in comparison data,
may terminate the instruction. [Mnemonic] NOV [Instruction function] copy string Copy string [Instruction options] /F Process in increasing address /B Address
Process in the direction of decreasing the number of errors/various termination conditions (eeee)
(The device of the present invention does not support 0UTU-ZE, which is <<L2>>.) [Instruction bit pattern and assembler notation] Fig. 177
show. [Flag change] Shown in FIG. 178. [Explanation] Transfers a string. In the string instruction 5NOV/B that operates in the decreasing direction,
, the address first specified by RO, R1 is the target of the operation.
The maximum address occupied by the string +1
Proceed with the operation while pointing and decrementing RO and R1.
Melt. At 5M0V, SrC and dest overlapped.
Sometimes, specify the incorrect option /F or /B.
The behavior when specified is the same as BVCPY and BVMAP.
shall not be guaranteed. In other words, the implementation
It may differ depending on whether or not instruction execution is interrupted. This is a Vibrine-like system that takes advantage of the features of high-performance instructions.
When accessing memory, the order of memory access is
may change, and the writing of the previous element is not necessarily
There is no guarantee that the next element will be read after completion.
That's because there isn't. Note that the backward processing option /B is specified by this instruction 5M0.
For V/B only, use <<S1>> instead of <<L2>>.
ing. High-level operations such as arbitrary-length bit field instructions and string instructions
Detailed specifications of functional instructions and register values after instruction completion
Please refer to Appendix 11 for details. [Program exception] - Reserved instruction exception - When ss = 'tt' When p = 't' - When Q = 'l' - When eeee = '0111' to '1lll' [Nemo
Nick] CMP [Instruction function] compare string Compare strings [Instruction options] /F Process in the direction of increasing address /B Address
<<L2>> (with the device of the present invention)
is supported)/various termination conditions (eeee) (this
The invention device does not support 0tJTU-ZE, which is <<L2>>. ) [Instruction bit pattern and assembler notation] In Figure 179
show. [Flag change] Shown in FIG. 180. [Explanation] Strings 5rcl, 5rc2. Let's compare. Continue comparing as long as the two strings match, and then
If a character that does not match is found, the comparison ends. SCMP command
Now, similar to the CMP instruction, the result of 5rc2-5rcl
Set flags based on . For example, LJIag
It is said that S'C2 is smaller than 5rcl.
Show that. Based on the results of 5rcl-5rc2,
It does not set the lag. As an application of SCMP commands with termination conditions, text
Compare line by line (set line feed character code in R3)
(and run SCMP/EQ), compare only while the numbers continue.
, compare only while full-width characters continue, and so on.
be. In SCMP, there are three factors that cause an instruction to terminate:
, they can be distinguished by flag changes. 1. Termination VJIag according to the number of elements (data) (R2) = 1 2. Termination FJIag according to termination conditions = 1. Town flag depending on termination factor
changes 3, termination due to data mismatch during comparison Z-flag
= 0. Depending on the comparison result, L-f lag, X-f
lag changes and -flag compares the last data as signed.
The comparison result when comparing Xjlag is the comparison result when the last data is considered as unsigned. Of the factors 1 to 3, check 2 and 3 at the same time.
It is possible, but checking the factors of 2 and 3
is done in a separate phase. Therefore, 2 and 3 are the same
Although sometimes it holds true, l and 2 or 1 and 3 hold true at the same time.
It never stands up. I, 2. at least one of 3
The SCMP instruction ends when the termination factor is satisfied. While the data to be compared match, its value (srcl
= src2) is the target of the end condition test, but the data
If there is a mismatch, the 5rc indicated by RO
l is the end condition test target. However, the mismatch
When the SCMP instruction is terminated, the termination condition is met.
In many cases, information on whether or not the
This is just a promise. Also, MJI has no meaning unless the termination conditions are met.
Regarding ag, if it terminates due to another termination factor,
The meaning becomes unclear. The flag change in such a case is
Decide that it will be 0. Regarding ZJIag, L-flag, and X-flag
, the comparison result of the last data is always performed regardless of whether it matches or does not match.
reflect the results. Therefore, 3. Terminated due to reasons other than
(if the data match), Zj
lag=1. L-flag=0. X-flag=0
Ru. Note that SCMP supports unsigned data and signed data.
Sign the element in LJlag to handle both data.
The comparison result is entered when considering the data as
Contains the comparison result when elements are considered as unsigned data.
It looks like this. [The character code of 1TRON is a sign.
If you are dealing with general integers,
It is also necessary to handle signed data. The SCMP flag changes are summarized as shown in Figure 181.
Become. 0 indicates that the termination factor is satisfied, × indicates that the termination factor is satisfied.
Indicates that you are not satisfied. +-1-flag This is not the original meaning, but as a promise.
) Which of the termination conditions does A---5rcl=src2 correspond to?
Which of the termination conditions does 0---5rcl correspond to?
Depending on C---5rcl < 5rc2 or 5rc2 < 5
The /B option according to rcJ is <<L2>>, but in the device of the present invention,
to support. [Program exception] - Reserved instruction exception When SS = 'll' - When P = 'l' - When Q = 'l' - When eeee = 'o111' to '1111'
Monic] 5SCI+ [Instruction function] find a character in a str
ing string search [instruction option] /F Process in the direction of increasing address (pointer value
(Increase by element size) /The increase value of the R pointer is specified by R5 / Various termination conditions
(eeee) (In the H position of the present invention, it becomes <<L2>>.
0UTU-ZE is not supported. ) [Instruction bit pattern and assembler notation] Figure 182
show. [Flag change] Shown in FIG. 183. [Explanation] Search a string and find an element that matches the condition.
put out. In the case of '/R' option, regardless of whether R5 is positive or negative,
RO is always updated after comparing elements (post-in
(crement or bost decrement). The size of R5 in 5SCII/R is the pointer size of RO.
is equal to In other words, the device 32 of the present invention uses 32 bits.
is fixed, and in the device 64 of the present invention, the P bit or mode
specified by. SS (R3゜R4, Element
size). [Program exception] - Reserved instruction exception - When SS = 'll' - When P = 'l' - When eeee = 'o111' ~ '1111'
[Mnemonic] STR [Instruction function] 5tore characters Repeatedly write the same data (string fill) [Instruction options] None [Instruction bit pattern and assembler notation] See Figure 184
show. [Flag change] Shown in FIG. 185. [Explanation] Specified by the start address (R1) and length (R2)
Repeatedly write the value of R3 to the memory area. In the 5STR instruction, the termination condition has no meaning, so the termination
No conditions are specified. In addition, if the string instruction is R2 = 0, the number of elements is
t], but in the case of a 5STR instruction, an error occurs.
The termination due to the number of elements is the only termination factor, and R2=
Specifying 0 will create an infinite loop. this
Regarding this issue, there is no need to deal with it in particular in the hardware, but in the program.
I will ask the team to pay attention to this. However, during the execution
Since it is possible to accept requests and re-execute them, this command will prevent mistakes.
Even if the task or process goes into an infinite loop,
It does not affect scheduling etc. Usually multiple instructions
The infinite loop formed by
I think he was just stopped. Example of invalid operand: R2=0
The reason why it is not set to 10E is due to specifications with other string instructions.
This is because we considered unification, implementation burden, and speedup.
be. In addition, parameters can be set using the 5SCII and QSCI+ instructions.
An infinite loop can be created with a single instruction depending on the data and termination conditions specified.
may form. [Program exception] ,・Reserved instruction exception When φSS='ll' When φp='t' 12-1. Knee order Δ In the device of the present invention, Q
INS (insert entry), QDEL (insert entry)
(Delete), QSC++ (Entry search)
A decree is prepared. Keys supported by the device of this invention
The queue is the first @ and second @ from the beginning of each queue entry.
The data is a link pointer with an absolute address, dub
This is a link cue. at the beginning of the queue entry
The data becomes a pointer to the next queue entry and
-The data in the second entry is the previous queue entry
It is a pointer to . The queue instruction specification specifies that the queue header is the queue instruction's operation.
The following policy is in place so that it can be directly specified as a land.
It is determined by 1. In QDEL, it is not the specified entry but the immediately following entry.
Entry is deleted. If QUEUE IIEAD is specified as an operand,
If so, the first entry will be deleted. The entry found in QSCII/B
Indirect reference is required when deleting or deleting the last entry in the queue, but the digit entry found in QSCH/F
This is thought to occur less frequently than when deleting a file or deleting an entry at the head of a queue. 2. In QINS, a new entry is added just before the specified entry.
Entry is inserted. QtJELIE HEAD was specified as an operand
In this case, the entry will be inserted at the end of the queue. There are two ways of thinking about this. Considering the symmetry with the QDEL instruction, QINS specifies
Immediately after the entry (or QUEUE HEAD)
It is preferable to insert an entry in This is QINS
In order to delete the entry inserted with QDEL, use the same
This is because operands can be specified. Also, the queue can be used like a stack (LIFO).
This type of specification is also better when On the other hand, when using a FIFO queue, QINS is used to
Insert the entry at the end of the queue, and in QDEL insert the entry at the end of the queue.
The first entry is often deleted. This is the original way to use queues, and lTR0N also uses it like that.
There is an example. Therefore, we will use the latter specification. 3. In QSCH, the immediately following entry is used instead of the current entry.
Start your search from the entry. QUEUE) If IEAD is specified as an operand,
In this case, the search will start from the head of the queue. Further, in order to perform the next search when the search is successful, it is sufficient to simply execute the QSCH again. This idea is different from other high-performance instructions (string, arbitrary length bit field manipulation).
It is. That is, in a string instruction, the search starts from the data that the pointer is currently pointing to, and if a continuous search is to be performed, it is necessary to update the pointer with a separate instruction. This is a different behavior than a queue command. However, in the case of queues, the headers are different, and the handling is different, so we decided that it would be okay to use a different specification. 4. Determine empty queues using flags. If you insert data into an empty queue with QINS, QDE
If the queue becomes empty as a result of deleting an entry with L,
, set Zjlag. You can also use QDEL to create an empty queue.
If you try to delete an entry from
No, but set VJIag at this time. [Mnemonic] QINS entry, queue [Instruction function] 1nsert a new entry 1nto a
queue Insert into double link queue [Instruction options] None [Instruction bit pattern and assembler notation] Figure 186
show. [Flag change] Shown in FIG. 187. ]Explanation] The new queue entry specified by entry is q
Inserted immediately before the queue entry indicated by ueue
. The queue entry specified by queue is the queue header.
If it is, this instruction will be sent to the end of the queue.
A new entry will be inserted. Z depends on whether Kine was empty before the instruction was executed.
Jlag is set. [Operation of QINS instruction when processing in 32 bits]
] Shown in FIG. 188. [Before execution] Shown in FIG. 189. [After execution is shown in FIG. 190.] Addressing specified by EaMqP and EaMaP2
In the register direct RnS@-5P, @SP+,
#i open-data mode cannot be used. Note that in QINS, information that is not directly required for instruction execution is
Check the data structure of the missing part (before and after the queue)
(link relationships between queue entries, etc.) are not particularly performed. Perform the actions described in the operation. [Program exception] - Reserved instruction exception - When +='09 When Φ-=21' - EaMqP is Rn, #imm-data, l:SI'
+J-5P, ΦEaMqP2 is Rn, #imm-data, @SP+
, @-5P [Mnemonic] QDEL queue, dest [Instruction function] remove a entry from a que
Delete ue double link queue entry [Instruction option] None [Instruction bit pattern and assembler notation] See Figure 191
show. [Flag change] Shown in FIG. 192. [Explanation] The next entry after the queue entry specified by queue.
and set the address of the deleted entry to dest
set. dest the address of the deleted entry
Setting it to ``does not work with the deleted entry after that''.
This is because there are many cases where If you specify a queue header as queue, the key
The first entry in the queue will be deleted. If the queue specified by queue is an empty queue,
In this case, the command cannot be executed. At this time, start the EIT.
First, only set the V-flag and Z-flag.
to end the command. dest remains unchanged. dest/Easu! In S, @-5P mode is prohibited.
ing. This means that the queue is empty and the VJIag is set.
, if dest cannot be transferred, e-5 is sent to dest.
If P is specified, the command operation will be difficult to confuse.
It is. [Operation of QDEL instruction when processing in 32 bits]
The ratio is shown in Figure 193. [Before execution] Shown in FIG. 194. [After execution] Shown in FIG. 195. In the addressing mode specified by EaRqP, the record
JISTA Direct, @-5P, @SP+, ltimm-dat
Mode a cannot be used. Note that in QDEL, checks other than determining empty queues are possible.
, parts of the data structure that are not directly necessary for instruction execution.
Check the structure (refresh the queue entries before and after the queue)
(link-related, etc.) are not particularly performed. write to operation
Perform the actions as indicated. [Program exception] - Reserved instruction exception - When + = '0' - When W = 'l' - EaRqP is Rn, #imm-data, @SP+,
@-5P・EaW! S is old mm-data, @SP+, (i!-
When 5P [Mnemonic] QSCI ([Instruction function] 5search queue entries Queue support
[Instruction option] /NM R6 without mask/MRR6 with mask <<12>> (device of the present invention
) /F Search in the forward direction of the queue /B Search in the backward direction of the queue <<L2>> (This invention
(Supported by the device) /Various termination conditions (eeee) (Supported by the device of the present invention)
0UTU-ZE with L2>> is not supported) [Instruction bit pattern and assembler notation] See Figure 196.
show. The required set is RO, R2, R3 (optional)
), R4 (optional), R5, R6 (optional)
), and the result is stored in RO. It is R1. You can continue with the next search. [Flag change] Shown in FIG. 197. [Explanation] Search queue entries and find one that matches the conditions.
Let's go. Reverse search function/B and mask function/
MR is <<L2>>. The device of the present invention supports backward search function/B.
. Mask function/MR is not supported. The amount of processing for this instruction depends on the queue length, so
Consideration for interruptions during execution as with string instructions
is necessary. Therefore, operands and intermediate execution states
The status is placed in a fixed number register. Search conditions include mask (extraction of specific bits) and comparison.
A comparison is provided. The mask is used to search for flags,
Comparison is used for priority processing, etc. To specify comparison conditions,
This is the same as specifying the termination condition for a string instruction. To determine the end of the queue, enter the queue entry address.
Compare the reply and queue end address R2, and
If the command is completed, the command is terminated. By comparison with R2
If you finish the instruction, i.e. the search condition
If there is nothing that satisfies the search and the search fails, V
Set JIag and end the instruction. EIT does not start. Depending on the condition specification of the QSCH command,
It may go into an infinite loop. For this, the hard
The software does not take any particular action, and the program has to be careful.
I decided to do that. However, it is possible to accept interrupts during execution and re-execute, so the user
Suppose you accidentally enter an infinite loop in your program.
However, it does not affect the scheduling of tasks and processes.
do not. Infinite loops usually consist of multiple instructions.
I think it just happened to be combined into a - command. When the search is finished, the RO will search for engines that match the specified conditions.
R1 indicates the entry just before it. R1
removes an entry when in a single-linked queue
can be used for. In addition, QDEL specifies
The entry following the entry entered is deleted, so the QSC
If you want to delete the entry itself found on I/F, Q
After SCHSC, use @R1 instead of @RO as a parameter.
Then execute QDEL. Generally, the address of QUEUE HEAD is set to RO, R2.
By setting and executing the QSC11 instruction, the key is
Search the entire queue, even when the queue is empty.
I can do it. QSCH has single link queue and double link queue.
This command is intended to be shared by multiple users. [QSCH operation diagram is shown in FIG. Among these, chec3interrupt is
Check to see if there is an interrupt, and
If so, interrupt QSCH execution and handle the interrupt.
The idea is to start. QS after interrupt processing
C) Execute the remainder of the l instruction. [Before execution is shown in Figure 199.] [After execution] Shown in FIG. 200. [Program exception] - Reserved instruction exception - When SS = 'll' - When eeee = 'o111' ~ '1111' -
When m = '1', 12-'' w, v maji ≦ Otsukume now [Mnemonic] BRA newpc [Instruction function] branch always jump (PC relative) [Instruction options] None [Instruction bit pattern and assembler notation] No. 201 In the figure
show. [Flag change] Shown in FIG. 202. [Explanation] The 13RA instruction supports only PC-relative addressing.
This is a jump instruction to start. of displacement
As for the size, BRA:D is 8 bits, BRA:G is 8 bits.
So, 8 bit, 16 bit, 32 bit, 64 bit
Available. The instructions of the device of the present invention always start from an even address.
In the shortened BRA:D instruction, #d8 is set to 2.
Double and use. That is, PC+ #d8ne2 ==> PC. If you specify 5s=oo in BRA:G,
#Use dS as is without doubling it. If BRA:G and newpc are 16 bits, JMP
@(#dS:16, PC), instruction function, code size
Both are the same, but the number of execution cycles can be shortened.
Due to gender, there are separate orders. BRA:G, if neWpc is an odd number,
Since the jump destination is an odd address, the odd address
This results in a dump exception (OAJE). This is Bcc:G,B
The same applies to the SR:G, JMP, and JSR instructions. BRA:
D*Bc c: D*BSR: In D,
Since the operand is doubled, 0AJE does not occur.
do not have. BRA:G, Bcc:G, BSR:G
If 5s=oo, the operand size is 8 bits.
However, the #dS field is 16 bits. At this time,#
The dS field uses only the lower 8 bits and the upper 8 bits.
You must always enter 0 in ``Tsuto''. top 8
If the bit is not O, the data represented by this
Assume that the data is an implementation-dependent undefined value. One
In other words, in the case of the BRA:G instruction, the jump destination is undefined.
Ru. It will not be an EIT. In the device of the present invention, dynamic branch prediction processing is performed for this instruction.
do. [Program exceptions] - Reserved instruction exception - When ss = 'tt' - When p = 'i' - Odd address jump exception - When jumping to an odd address [Mnemonic] Bcc newpc [Instruction function] branch conditionally conditional jump
(PC relative) [Instruction options] None [Instruction bit pattern and assembler notation] Figure 203
show. [Flag change] Shown in FIG. 204. [Explanation] The 13cc instruction supports only PC-relative addressing.
This is a conditional jump instruction. displacement men
Bee: D is 8 bits, B is 8 bits.
cc: G: 8 bits, 16 bits, 32 bits, 64
Bits are available. The command of the device of the present invention is always an even number address.
Since it starts from the response, in the Bcc:D instruction, #d8 is set to 2.
Double and use. That is, 1f(cccc) PC+jc! 8 * 2 ==> PC. Bc
If 5s=oo is specified for c:G, double #dS.
Use it as is. Details and instructions for the condition specification part (1009 part) of Bcc
For the bit pattern of cccc and cccc, see the appendix.
About Teru. If you specify an undefined condition in Bcc,
This results in a reserved instruction exception (RIE). When Bcc:G does not jump because the conditions do not match
, in the device of the present invention, the odd number address error exception (OAJE)
) may or may not occur. In the device of the present invention, dynamic branch prediction processing is performed for this instruction.
do. [Program exception] - Reserved instruction exception - When SS = 'll' - When P = 'l' - When cccc = '1110' to '1111'
- Odd address jump exception - When jumping to an odd address [Mnemonic] BSRnewpc [Instruction function] jump to 5ubroutine subroutine
Jump (PC relative) [Instruction options] None [Instruction bit pattern and assembler notation] See Figure 205
show. [Flag change] Shown in FIG. 206. [Explanation] The BSR instruction supports only PC-relative addressing.
This is a subroutine jump instruction. The PC value is saved to the stack. As the displacement size, in BSR:D
8 bits is 8 bits, 16 bits, 3 bits in BSR:G.
2 bit and 64 bit are available. Instructions for the device of the present invention
always starts from an even address, so with the BSR:D instruction
, double #d8 and use it. That is, PC+ #d8ne2 ==> PC. [If 5s=oo is specified in lSR:G,
, #dS is used as is without doubling it. The PC value saved to the stack with the BSR and JSR instructions
Then, use the start address of the next instruction. this
refer to the PC for calculating the effective address for
Cases (including cases where the PC is implicitly referenced by BSR etc.)
is the starting address of that instruction (not the next instruction).
Since it is used as a PC value, care must be taken. In BSR and JSR, the old PC is saved on the stack.
However, there is no particular check regarding SP alignment.
. Even if SP is not a multiple of 4, it will be executed as is.
. In the device of the present invention, dynamic branch prediction processing is performed for this instruction.
do. [Program exceptions] - Reserved instruction exception - When SS = 'll' When φP = 'l' - When Q = 'l' - Odd address jump exception - When jumping to an odd address [Mnemonic] JMP neenpc [Instruction function] address of src ==> PC jump [Instruction options] None [Instruction bit pattern and assembler notation] See Figure 207
show. [Flag change] Shown in FIG. 208. [Explanation] Jump to the effective address of neWpC. general ad
This is a jump instruction that can be used in lessing mode. When executing a case statement, use a jump table.
The jump destination address may be determined by reference. this
is an index address by JMP command and append mode.
This is achieved by combining with [Program exception] - Reserved instruction exception - EaA is Rn, #imm-data,! i! SP+,
[In the case of j-5P / Odd address jump exception / When jumping to an odd address [Mnemonic] JSRnewpc [Instruction function] jump to 5ubroutine subroutine
Jump [Instruction option] None [Instruction bit pattern and assembler notation] Figure 209
show. [Flag change] Shown in FIG. 210. [Explanation] Subroutine jump to effective address of neWpC
. The PC value is saved to the stack. The PC value saved to the stack by BSR and JSR instructions is
If so, use the start address of the next instruction. to this
On the other hand, when referring to the PC for calculating the effective address,
(including cases where the PC is implicitly referenced by BSR etc.)
indicates the start address of that instruction (not the next instruction) as P
Since it is used as a C value, care must be taken. [Program exception] - Reserved instruction exception - When P = 'l' - EaA is Rn, #imm-data, @SP+J-5
When P/Odd address jump exception/When jumping to an odd address [Mnemonic] Ace 5tep, xreg, 11m1t, new
pc [Instruction functions] add, compare and branch
Loop instruction to increase index value [Instruction option] None [Instruction bit pattern and assembler notation] Figure 211
show. [Flag change] Shown in FIG. 212. [Explanation] This is a compound instruction that combines addition, comparison, and conditional jump into one instruction.
and use it as a loop primitive. 5tep, xreg, 11m1t are signed integers.
are calculated and compared. 5tep must be a positive value.
There is no point in jumping the item (xreg is opposite to the end value)
(will change in the direction), positive and negative checks of 5 steps
Do not perform any
Do the work as it is. The ACB instruction can be executed at high speed as a loop instruction.
To check for overflow during 5-step addition, go to
No rope. Overflow occurs as a result of adding 5 tep.
However, if the sign is reversed, the correct
The low value is directly compared with 11m1t. However, comparison
Subtraction of 11m1t-xreg for overflow
Even if -, the comparison of xreg < 11m1t is correct.
It will be done with certainty. In AcB and SCB, jumps are performed relative to the PC. 5
When S=00 and displacement is 8 bits
Also, as in the case of SS≠00, #dS8 is not multiplied by 2.
Use as is. If SS≠00, the flag of #dS8
The field is not used (set to 0), and the sample specified by SS is used.
The data of size (16, 32, 64 bits) is #dS8.
Follows immediately after. For example, ACB:Q old, RO+#4+
1abel, I abe I and ACB:Q instruction
If the difference in dress is H'1234, Fig. 213
The bit pattern will be as shown in . This is a fixed length pitstop.
The same is true for the :1 format of field instructions. [ACB operation] xreg + 5tep =:=> xreg/*o
In case of barflow, only the lower bit is valid */ if (xreg < 11m1t) then PC
+ #dS8 ==>PCendif If neWpC is an odd number, the jump destination is an odd number.
Odd address jump exception (OA)
JE). In the device of the present invention, in order to satisfy the termination condition,
An odd address jump exception (O
AJE) is generated. [During detailed specification adjustment When SS≠00 in ACB and SCB commands, #dS8
Fields are not used. At this time, if #dS8 fi
Even if the field is not zero, it is simply ignored. just
However, in the manual, the #dS8 field is always 0.
Make sure to include the . The device of the present invention performs dynamic branch prediction processing for this instruction.
make sense. [Program exception] - Reserved instruction exception - When RR = 'll' - When XX = 'll' - When SS = 'll' - When P = 'l' - When EaR is @-5P - EaRX When is @-5P - Odd address jump exception - When jumping to an odd address [Mnemonic] SCB 5tep, xre3. Ii + nit, ne
wpc [Instruction function] 5ubtract, compare and bra
Loop instruction to decrease the nch index value [Instruction options] None [Instruction bit pattern and assembler notation] Figure 214
show. [Flag change] Shown in FIG. 215. [Explanation] This is a compound instruction that combines subtraction, comparison, and conditional jump into one instruction.
and use it as a loop primitive. 5tep, xreg, I 1m1t, etc. are signed.
are compared as large integers. 5tep is not always a positive value
There is no meaning in conditional jump, but (xreg is the end value
(will change in the opposite direction). Sign of steρ
is written in the operation without checking
Just do what you're supposed to do. The SCB instruction can be executed at high speed as a loop instruction.
To check for overflow when subtracting 5 steps, go to
No rope. Overflow occurs as a result of reducing 5 tep.
However, if the sign is reversed, the correct
The low value is directly compared with 11m1t. However, comparison
Subtraction of 11m1t-xreg for overflow
Even if -, the comparison of xreg < 11m1t is correct.
It will be done with certainty. In ACB and SCB, jumps are performed relative to the PC. If the displacement is 8 bits when 5S=00
In this case, #dS8 is not doubled as in the case of SS≠00.
Use as is. If SS≠00, #dS8
The field is not used (set to 0) and is specified by SS.
Data of size (16, 32, 64 bits) is #dS8
immediately follows. [SCB operation] xreg -5tep ==> xreg/*over
In case of flow, only the lower bit is valid./if (xreg≧11m1t) then PC+
#dS8 ==>PCendif If newpc is an odd number, the jump destination is an odd number
Odd address jump exception (OA)
JE). In the device of the present invention, in order to satisfy the termination condition,
An odd address jump exception (O
AJE) is generated. [Currently adjusting detailed specifications] When SS≠00 in Ace, SCB command, #dS8
Fields are not used. At this time, if #dS8 fi
Even if the field is not zero, it is simply ignored. just
However, in the manual, the #dS8 field is always 0.
Make sure to include the . The device of the present invention engraves this instruction to perform dynamic branch prediction processing.
make sense. [Program exceptions] - Reserved instruction exception - When RR = 'll' - When XX = 'll' When φSS = 'll' - When P = 'l' - When EaR is @-5P - When EaRx is @-5P / Odd address jump exception / Jump to odd address [Mnemonic] ENTER1ocal, reglist [Instruction function] create new 5tack frame stack
Formation of frame, subroutine jump for high-level language [Instruction option] None [Instruction bit pattern and assembler notation] Figure 216
show. [Flag change] Shown in FIG. 217. [Explanation] Create a stack frame 11 for a high-level language. ENTER's I oca I is treated as signed,
If the size of I ocal is small, I oca
The value of I is sign extended. I oca If I is negative, then
A meaningless stack frame is formed, especially when
Do not do any tsuku, just follow the instructions as written in the operation.
Perform the action. This point is the 5 step of AcB and SCB.
is the same as Operation: FP -> ↓TO5 SP -> FP SP -1ocal -> SP registers (mask) -> ↓TO5 high
For more information on stack frames for class languages, see the appendix.
and. The bitmap designation LnXL of the register to be saved is the second
Proceed as shown in Figure 18. LnXL is placed after the extension of EaR. bitO, bitl(S
P, FP), the specification is simply ignored.
shall be provided. bito and bitl are “1”
Also, SP and FP are not transferred. This is a fraudulent opera
The exception (10E) is the negative exception of the implementation.
This is because the load is large and the effective speed is affected. however
, even if the check is not performed, the bits of FP and SP are
Please be sure to enter '0' in the manual, etc.
It is necessary to instruct. Don't particularly check the alignment of FP and SP.
stomach. Even if FP and SP are not multiples of 4, the operation
Execution is performed as written in the section. ENTER: G's 1local operand is in memory.
and it is the string formed upon execution of the ENTER instruction.
If it overlaps with the tack frame area, the instruction will be re-executed.
Lines become extremely difficult. So, ENTER: G, J
RNG:G, and from symmetry EXIT[1:G command
In this section, addressing modes involving memory access,
Addresses other than register direct Rn and immediate
All single modes are prohibited. The operation of this command
If you want to set a dynamic value as a land, use Temporary.
Prepare one re-register and set the register direct Rn mode.
It means using it. Operation when FP and SP are specified as I oca I
is implementation dependent. [Program exception] - Reserved instruction exception - When X = 'l' - When + = 90' - When - = '1' - When p = 't' When SS = 'll' - EaRlM is # imm-data, other than Rn [
Mnemonic] EXITD reglist, adjsp [instruction
Function] exit and deallocate param
eters subroutine returns and parameters for high-level languages
[Instruction option] None [Instruction bit pattern and assembler notation] Figure 219
show. [Flag change] Shown in FIG. 220. [Explanation] Freeing stack frame and restoring registers for high-level languages
and return from the subroutine. Then add adjsp to SP and leave it on the stack.
Discard the subroutine parameters. adjsp in EXITD is treated as signed, ad
If the size of adjsp is small, the value of adjsp
The number is expanded. Meaningless operation if adjsp is negative
However, it does not perform any particular checks, and does not perform any particular checks.
Execute as written. In this point, Ace
, is the same as SCB's 5tep. Operation: adjsp ==) trrIp ↑TO5==> re8isters(+nask)F
P ==> SP ↑TO5==> FP ↑TO5==> Pc 5p + acljsp ==> SP high-level language script
See the appendix for details on tuck frames. The bitmap designation LxXL of the register to be restored is the second
Proceed as shown in Figure 21. LxXL is placed after the extension of EaR. Bit 14 in the EX I TD reglist. bit
15 (SP, FP), simply specify the
shall be ignored. bit14. bit15 is”
1”, SP and FP are not transferred.
It is the implementation that does not treat it as an positive operand exception (IOE).
This is because it puts a heavy burden on the client and affects the effective speed.
. However, even if the check is not performed, FP, SP
Please make sure to put '0' in the bit of the manual.
It is necessary to provide guidance through Al, etc. Don't particularly check the alignment of FP and SP.
stomach. Even if FP and SP are not multiples of 4, the operation
Execution is performed as written in the section. Return address returned from the stack by EXITD
If the address is an odd number, the jump destination is an odd address.
Therefore, odd address jump exception (OAJE)
Become. In the EXITD operand adjsp/EaR1M,
Addressing mode that involves memory access, i.e.
Addressing other than register direct Rn and immediate
All modes are prohibited. If you want to set a dynamic value as an operand of this instruction
To do this, prepare one temporary register and access the register directly.
This means that the Rn mode will be used. Use register direct Rn mode for adjsp, re
If glist contains the same register Rn,
, adjsp, the values before register restoration are used. In other words, the EX I TO instruction that was saved in the stack
Not the register value after executing the instruction, but before executing the EXITD instruction.
The register value becomes adjsp. The operation when specifying FP and SP as adjsp is as follows.
Implementation dependent. [Program exception] - Reserved instruction exception - When X = 'l' - When + = '0' - When - = 91' - When P = 'l' When SS = 'll' φEaR1M is #imm -When other than data and Rn [
Mnemonic] RTS [Instruction function] return from 5ubroutine suble
Return from the program [Instruction options] None [Instruction bit pattern and assembler notation] Figure 222
show. [Flag change] Shown in FIG. 223. [Explanation] Performs a return from a subroutine. Operation: ↑TO5-> PC RTS, the return address returned from the stack is
If it is an odd number, the jump destination will be an odd address.
Therefore, odd address jump exception (OAJE)
Become. [Program exceptions] - Reserved instruction exception - When p = 't' - Odd address jump exception - When the return address is an odd number [Mnemonic] CIP [Instruction function] no operation No operation [Instruction option] None [Instruction] Bit pattern and assembler notation] Figure 224
show. [Flag change] Shown in FIG. 225. [Explanation] Do nothing. [Program exception] - Reserved instruction exception - When -='1' [Mnemonic] [Instruction function] purge 1nstruction buffer instruction
Ensure consistency of instruction cache and vibe line [Instruction option] None [Instruction bit pattern and assembler notation] Figure 226
show. [Flag change] Shown in FIG. 227. [Explanation] Instruction pipeline, instruction queue, instruction cache, etc.
Purge all buffers to speed up instruction execution.
, the instruction sequence placed in memory and the internal state of the processor.
ensure the integrity of This command should now be executed
If the instruction code is from the previous (at reset or previous PIB)
This means that it may have been changed since the time the instruction was executed.
and is used to notify the processor. In the device of the present invention, the pipeline, instruction queue, and instruction cache are
To simplify the control of the
Modification of the code is not allowed. In other words, you can use the instruction code that you have changed by yourself.
Even if you try to run it as is, operation is not guaranteed. Toko
However, if you look at the processing performed by O5 from a macroscopic perspective, the program
There is a flow of loading a program and then executing it. In other words, from a broader perspective, instructions are given by the O5 program.
You will be rewriting the code. For special purposes, instructions generated by a program may also be used.
It may also execute a sequence of commands. The purpose of this command is to ensure correct execution of the command in such cases.
The goal is to be able to do this. In other words, before entering the instruction code that has been rewritten, this
If you execute the instruction, the new instruction code will execute correctly.
guaranteed. In terms of implementation, this life
Instruction pipeline, instruction queue, instruction cache
will be purged. However, the vibration line and cache mechanism are
It has a bus monitoring mechanism for rewriting the memory.
memory consistency is always guaranteed in hardware.
If there is, it is not necessarily necessary to purge with the PIB command.
stomach. In this case, the PIB instruction is executed as a NOP instruction. In any case, after executing this instruction, the pipeline
The consistency of the instruction cache and memory is guaranteed.
That's fine. When realizing multiple logical space using MMU,
Only the logical space where the PIB instruction was executed was rewritten.
Execution of instruction code is guaranteed. For example, if you rewrite the instruction code of context-A, TCTX LDCTX, context-jB, rewrite the instruction code of context-jB, and execute the instruction sequence IB, in context-jB,
Operation is guaranteed even if the modified instruction code is executed.
, then even after running LDCTX contexjA
, for execution of the modified instruction code of contextJ.
operation is not guaranteed. instruction execution of context A
In order to guarantee the row, the context of contextjA
It is necessary to execute the PIB instruction again in the
. This is the case when LSID is introduced in the instruction cache.
In the PIB instruction, the instruction cache with matching LSID
This is because you want to just purge the client entries. For commands other than PIB commands, any jump command or O
5 related instructions (LDCTX, REIT, RRNG, TRA
Even after executing (P, EIT startup, etc.), the instruction code
The operation of the replaced part of the program is not guaranteed. This is done to reduce instruction cache purges as much as possible.
It's a good thing. Therefore, the program loaded by the O5
The first time you run it, it enters a new context and
(for example, between LDCTX and RE IT (7)),
First, it is necessary to execute PIB. This instruction's mnemonic PIB (Purge 1nstr
ucti. n Buffer) 'Buffer' is the cache
Used in a general sense including pipelines, pipelines, etc.
It's PTLB's jB? Same example for Buffer of
There is. The mnemonic PIB is also associated with PTLB.
It is made from. This command is not a privileged command. From the user program
Can be used.゛[About Instruction Code Consistency]In order to accurately explain the operation of the PIB instruction,
The state of ``code consistency'' is defined as follows. "Instruction code integrity" refers to each logical address in each logical space.
This is a state that is defined separately for responses. for example,
In logical space A, H' 00000000 ~ H'0OOf
"Instruction code consistency" is guaranteed for ffff,
In logical space B, lI'ooo10000 to H'0003
"Instruction code integrity" is guaranteed for ffff.
It is used as "there is". "Operation code integrity"
Correct operation occurs only when executing an instruction in an area where
execute a new instruction (execute access right)
(including checks). In general, "life"
The area where instruction code consistency is guaranteed is the instruction code.
area, and in the data area, "instruction code integrity" is
Not guaranteed.・“Instruction code consistency” is guaranteed when
, in the following case. At the time of one reset, "instruction code consistency" is maintained in all areas of the physical space (= logical space).
You can obtain "sexuality". - When executing a PiB instruction, the entire area of the logical space where the PIB instruction is executed is
"Consistency" is obtained. If AT=00, reset
As with time, "instruction commands" are used in all areas of physical space (= logical space).
This results in "code integrity".・“Instruction code integrity” is lost because
In the following case. - When rewriting memory If the memory contents are rewritten, the “instruction” in the rewritten area
Code integrity is lost. This is a logical address
Memory access by physical address is also
The same applies to reaccess (AT=OO, LDP command, etc.)
It's like that. -When updating the ATE If the ATE is updated, the address is converted by that ATE.
The "instruction code consistency" of the area where the instruction is executed is lost. did
Therefore, for example, if you use LDATE to set the protection bits in ATE,
Even if changes are made, the PIB command must be executed afterwards.
In this case, the protection information will not be checked correctly. (This takes time to check the instruction cache and protection information.)
(This may be effective for lightening the implementation.) For general instruction execution that does not fall under the above points, BRA, JM
P, JRNG, RRNG, TRAP, REIT, LDC
Including TX, EIT startup, etc., "instruction code consistency"
'state' does not change. 12-13. Mar ° Rose...'s Δ [Nimoni]
BSETI offset, base [Instruction function
] -bit ->Z-fla3.1-> bit (i
Set the interlocked bit (lock the bus)
) [Instruction options] None [Instruction bit pattern and assembler notation] Figure 228
show. [Flag change] Shown in FIG. 229. [Explanation] Copies the inverted value of the specified bit to jflag.
then set that bit to 1. These two
The operation is performed with the bus locked and is an inseparable operation.
Ru. Therefore, to synchronize multiple processors
This command can be used in Addressing specified by ShMfqi, EaMfi
In the register direct mode Rn, @-5P, f
AsP+ and #imm-data modes cannot be used.
. In assembler notation, the size of memory access is bas
Specify as eO size. In BSETI:Q,
The memory access size is fixed at 8 bits, and the
Is can only write 'Bゝ. Also, BSET
I:G, BSETI:E access size (ba
se size), H, and W are specified as BSET, BC
Same as LR (<<L2>>. Specify access size, +1., W in <<L2>> specification.
However, the base is not aligned.
If the memory access range is
It depends on the rement. This is similar to a bit manipulation instruction.
be. At this time, the alignment
If an incorrect word or halfword is accessed,
If the bus is locked, you can use multiple bus sites with the bus locked.
Execute the kuru. This is similar to the C5I instruction. In the device of the present invention, a half word that is <L2,
Implements word-by-word access. Also
Use unaligned address as base
Aligned halfwords also if specified
, access is performed in word units. [Program exception] - Reserved instruction exception - When RR = 'll' - When BB = 'll' - When EaR is @-5P - EaMfi, ShMfqi are Rn, #imm-dat
When a, @SP+, @-5P [Mnemonic] BCLRI offset, base [Instruction function
] -bit ->Z-fla3.0-> bit (i
clearing the interlocked bit (locking the bus)
) [Instruction options] None [Instruction bit pattern and assembler notation] See Figure 230
show. [Flag change] Shown in FIG. 231. [Explanation] Copies the inverted value of the specified bit to jflag.
then set the bit to 0. These two
The operation is performed with the bus locked and is an inseparable operation.
Ru. Therefore, to synchronize multiple processors
This command can be used in In the addressing mode specified by EaMfi, the record
Register direct mode Rn, @-5P, @SP+, #im
m-data mode cannot be used. In assembler notation, the size of memory access is bas
Specify as eO size. BCLRI:G. BCLRI: Access size in E (base size
), ■9. The - specification is the same as BSET and BCLR (
<<L2>>. <<L2>>Specification access size, 11. , specify W
However, the base is not aligned.
If the memory access range is
It depends on the rement. This is similar to a bit manipulation instruction.
be. At this time, the alignment
If an incorrect word or halfword is accessed,
If the bus is locked, you can use multiple bus sites with the bus locked.
Execute the kuru. This is similar to the C5I instruction. In the device of the present invention, a half word that is <<L2>>
, implements word-by-word access. Ma
unaligned address as base
Even if you specify
Access is performed in units of codes and words. [Program exception] - Reserved instruction exception - When RR = 'll' - When BB = 'll' ◆ When EaR is @-5P - EaMfi is Rn, #imm-data, @SP+,
@-5P [Mnemonic] C5I comp, update, dest [instruction
Function] compare and 5tore (interl
(locked) Compare and store (lock bus) [Instruction options] None [Instruction bit pattern and assembler notation] See Figure 232
show. [Flag change] Shown in FIG. 233. [Explanation] The value of dest is the same as the previous value (specified by comp)
If so, it is a command to update the contents. This instruction allows data with a simple structure to be processed by a multiprocessor.
It can be used when updating from As a result of executing the C51 instruction, the value of dest is the previous value.
If it is found to be different, it may be
This means that the server has rewritten the data contents. did
Therefore, the discrepancy in the value of dest can be corrected by the C5I instruction.
The discovered processor uses the new dest value as
the data contents must be updated again.
. By adopting this method, multiprocessor
Data consistency can be maintained under CCS+ operation] update ==> tmp /Operations below zero are performed by locking the bus */ if (dest = camp) hen tmp ==> dest 1 ”:> ZJ!ag 1se dest ==> comp O ”> Zjlag Due to bit pattern constraints, comparison is successful in CSI.
Even if you do not do this, the update will be read. Also
, the access right of dest in the C5I instruction is always rea.
It is assumed that both d and write are necessary. In other words, the comparison fails with the C51 instruction, and for dest
Even if no writes occur, the serial
Address translation exception (ATRE) if there is no te access right
become. RMC, EaM i RO size is specified by RR. In the addressing mode specified by EaM t R
, e-SP, @SP+, Rn, # imm-data
Mode cannot be used. Use the C5I command to specify size, H, and W, and perform alignment.
If the operand is an address that does not have a
, perform multiple bus cycles while keeping the bus locked
. In this case, read. Each write is divided into two memory accesses.
Therefore, the entire instruction is to lock the bus and re
4 notes: ad, read, write, write
You will have to re-access it. In addition, general instructions other than C5I may cause misalignment.
If a memory access is made to an address that does not exist
The bus is not locked. So, for example, varl EQU H'00000006;
In the case of an unspecified address, NOV, W #tl' 12345678. from processor A. @var
Executes MOV from processor B, W #lI'87654321. @varl
When executed, depending on the timing of memory writing,
, H' 00000006~? =)I'8765H'
00000008~9=H'5678,
Even if Processor A's MOV instruction is executed first, the
This is different from the case where the NOV instruction of processor B is executed first.
This may result in For variables shared between multiple processors, normal data
Not only write but also data update (read-mod
ify-write), so it is inevitable that
The C5I instruction will be used for this, and the above problems will not occur.
Not alive. However, from multiprocessor to non-C5I
Accessing unaligned variables in instructions
In some cases, the above problems may occur,
You need to be careful. [Program exception] - Reserved instruction exception - When RR = 'll' - When EaR is @-5P - EaMiR is Rn, limm-data, @SI'+
, 12-14 when @-5P. j no ′t
l. of . ΔInvention
In the device, the control registers of the main processor are
Processor control registers and high-speed memory on chip bus
You can create one address space with
This is called the control space. Control space considerations
The method of
High-speed memory for saving text will be used in the main processor in the future.
This idea is especially effective when it is built into the system. system
Control register manipulation instructions access the control space.
It is a command to become. In addition, general-purpose control space operation commands such as LDC and STC
is a privileged instruction, so the user cannot access part of the control space.
To operate the PSB, PSM, l, DP
SB, 5TPSB, LDPSM, STI'
Use SM command. The device of the present invention does not have an address translation mechanism. Therefore, the logical space address and physical space address are always
Because they are equal, the function of the physical space manipulation command is to manipulate the logical space.
It will be absorbed by other commands. However, address translation
This invention has a mechanism and handles logical space and physical space differently.
With emphasis on software compatibility with the device, the device of the present invention
Supports physical space manipulation instructions. [Mnemonic] LDCsrc, dest [Instruction function] 1oad control 5pace or reg
Loading into the ister control space [Instruction options] None [Instruction bit pattern and assembler notation] In Figure 234
show. [Flag change] Shown in FIG. 235. [Description] Transfers the value of src to dest in the control space. 5rcO
When the size is smaller than dest, it is sign extended. In dest/EaWχ, register direct mode Rn
@-5P cannot be specified. This command is a privileged command. r i ngO
If this occurs, a privileged instruction violation exception (RIVE) will occur.
Ru. In the device of the present invention, the control space is controlled. B, +1 access
This feature does not support support functions. The control space is inside the CPU.
Implement only control registers. Also, since UATB and 5ATB are not implemented, LDC
Therefore, UATB and 5ATB cannot be changed. DATE, 5TATE, LDP, STP
, special space in LDC, STC, MOVPA instructions
In operands that refer to
When an indirect reference of a directory occurs, it is not the special space.
Refer to the logical space (LS). Also, the stack point
If there is a reference to InterSP, instead of PRNG,
The current ring RNG stack is referenced. The meaning of an address in a special space is based on the final result.
only the effective address given. to the control space. There is no access function for B,,H
In a processor, the control space operand size and
If you specify B, , H, reserved instruction exception (R
IE). Unimplemented control register or address with no control register
If the response is specified by LDC, reservation function exception (RF
E). The same applies to the area of <<shiv>>.
. A program with some restrictions on the addresses that can be used in the control space.
In case of processor, reservation function exception if violated.
(RFC). For example, set the address of the control register to
This includes restrictions such as being limited to multiples of 4. Conte
A processor with a built-in high-speed memory for text saving
For example, only the address of the control register part is limited to a multiple of 4.
In this case, the address of the high-speed memory part becomes free.
However, in this case as well, if there is a violation, the reservation machine
This results in a performance exception (RFE). Also, some addresses
In a processor where B, , )l can be specified only when
1, B, , H specified an address that cannot be accessed.
In this case, the reserved function example instead of the reserved instruction exception (RIE)
outside (RFE). This is the instruction bit pattern (support
Reserve items that can be determined as errors only by the size specification (including size specification)
This is an instruction exception (RIE) and is
An example of a reservation function that changes the status of whether it is an error or not
It is based on the idea that
Ru. The control space address is off-chip and the coprocessor address is
(e.g.), and due to implementation constraints,
Example of reservation function even when the area is no longer accessible
outside (RFE) occurs. In LDC and STC, control space
If the address between becomes the address of the coprocessor
Also, no coprocessor instruction exception (CIE) occurs. Ko
A processor instruction exception (CIE) occurs when
Only when executing processor instructions. LDC, control register 2-1. expressed as '+9
Attempting to write a different value to a reserved bit
reserved for a certain field.
If you try to write a value, a reserved function exception (RFC
)become. '001 in the SMRNG field of ps-
This also applies when you write a reserved value such as '.
Included in this. On the other hand, I=t, r expressed as 41
If a different value is written to the bit of ese rved
is simply ignored. However, the manual for users
In this case, be sure to write ``θ'' for ``2''.
You must be careful. Also, expressed as ``*''
Anything you write to the bits that are marked will simply be ignored.
. This bit differs from t=j%IF, and the specifications will be expanded in the future.
Bits guaranteed not to be used even if stretched
It is. Therefore, before running LDC, set this bit.
There is no need to mask the gate to 10'. If CTXBB is changed in LDC, C
Aligning the contents of TXBB with the actual in-chip context
However, it is the programmer's responsibility to handle this.
do. In terms of hardware, just change CTXBB.
Do this. Change CTXBB and load context
If you want to do both, you can use DCTX. UATB and 5ATB are changed by the DC command.
purge the TLB and logical cache accordingly.
(processing equivalent to PSTLB/AT) is automatically performed.
It will be done. For processors that implement LSID,
The logical space specified by the 0 control register is the purge pair.
Become an elephant. In this case, the LDC instruction includes the PSTLB instruction.
/SS and /AS options such as /SS are not provided.
However, this is not possible due to the following reasons. PTL8, PSTLB command to purge TLB
In this case, unlike the case of LDCI and UATB, other
In order to purge the physical space cache and TLB,
The parameters corresponding to the functions of Slo are stored in another register (
R1). In this case, the SID control
Control registers are not used. Therefore, its parameters
To distinguish whether to use /SS, /
It is necessary to switch the As option. However,
For LDC* and UATB, eliminate data inconsistencies
cache and TLB for the space currently in use.
Since the purpose of purging is to purge the LSIC control register
Ta works in its original meaning. That is, general memory access
Similarly, the logic specified by the LSID control register
The physical space is subject to purge. Process without LSID implementation
In the server, the entire logical space (but only one) is
Targeted. [Program exception] - Reserved instruction exception - When RR = 'li' - When other than 4:210' - When EaR is @-5P - EaW$ is Rn, #imm-data, @SP+, @
-5P - Privileged instruction exception - When executed from other than ringo - Reserved function exception - When accessing an unimplemented control register - Reser r for a specific field of the control register
When trying to write the value of ved (excluding =, #, and
) - Ensure word alignment of the address of EaW2:
[Mnemonic] STCsrc, chest [Instruction function] 5tore control 5pace or re
Store from gister control space [Instruction options] None [Instruction bit pattern and assembler notation] Figure 236
show. [Flag change] Shown in FIG. 237. [Explanation] Transfers the value of src in the control space to dest. ST
In C, the sizes of src and dest are specified in common.
Therefore, transfer between different sizes is not performed. This command is a privileged command. Real from other than r i ngo
If executed, it becomes a privileged instruction exception (PIVE).
Ru. In src/EaRχ, register direct mode Rn is specified.
, Immediate) #imm-data specification, eSP
+ cannot be specified. In the device of the present invention, for the control space. B., 11 actions
Access functions are not supported. For control space, CPU
Implements only the control registers within. LDATE, 5TATE, LDP, STP
, special space in LDC, STC, MOVPA instructions
In operands that refer to
When an indirect reference of a directory occurs, it is not the special space.
Refer to the logical space (LS). Also, the stack point
If there is a reference to InterSP, instead of PRNG,
The current ring RNG stack is referenced. The meaning of an address in a special space is based on the final result.
only the effective address given. to the control space. There is no access function for B,,H
In a processor, the control space operand size and
, and specify B, , 11, reserved instruction exception (
RYE). Unimplemented control register or address with no control register
If the response is specified by STC, reservation function exception (RF
E). The same applies to the <<LV>> area.
. A program with some restrictions on the addresses that can be used in the control space.
In case of processor, reservation function exception if violated.
(RFE). For example, set the address of the control register to
This includes restrictions such as being limited to multiples of 4. Conte
A processor with a built-in high-speed memory for text saving
For example, only the address of the control register part is limited to a multiple of 4.
In this case, the address of the high-speed memory part becomes free.
However, in this case as well, if there is a violation, the reservation machine
This results in a performance exception (RFE). Also, some addresses
For processors that can only specify B, , )I,
1, B, , 1 (specify the address that cannot be accessed.
Even if the reserved function is not reserved instruction exception (RIE)
This will result in an exception (RFE). This is the instruction bit pattern (
Predict what can be determined as an error only by specifying the size (including size specification).
About instruction exception (RIE), and address or operand value
Therefore, if the status changes whether it is an error or not, it is a reservation function.
It is based on the idea that it is an exception (RFE).
be. Control space address is off-chip (coprocessor address)
(e.g.,
Example of reservation function even when the area is no longer accessible
outside (RFE) occurs. In LDC and STC, control space
If the address between becomes the address of the coprocessor
Also, no coprocessor instruction exception (CIE) occurs. Ko
A processor instruction exception (CIE) occurs when
Only when executing processor instructions. In the STC, the bit represented by '-2 of the control register
When reading the bit, ′θ′ reads the bit of ′+1.
If it protrudes, sit is read out. Also, try to read the bits of p=t, e#e, tc.
The value obtained in this case is indeterminate. to implement
Therefore, in the case of 90' fixed, in the case of sV fixed, the previously written
The written value may be read out as is. Future
For expansion, the values of the bits of '2t, jilt, j02 are
Users are advised not to program using
This must be clearly stated in the relevant manual. [Program exception] - Reserved instruction exception - When 4 = 10' other than φEaRX is Rn, #imm-data, @SP+, @
-5P time EaW is #imm-data, @SP ten
- Privileged instruction violation exception - When executed from other than r i ngO - Reserved function example
When accessing an external/unimplemented control register ◆The word alignment of the EaRX address is not correct.
When not available [Mnemonic] LDPSB src [Instruction function] 1oad PSB Load to PSB [Instruction options] None [Instruction bit pattern and assembler notation] Figure 238
show. [Flag change] Shown in FIG. 239. [Explanation] Transfer src to PSB. Individual PSB, r'sH, etc.
When saving or restoring is performed regardless of the meaning of the bits,
In PSM and PSB, some fields are
There are many cases where people want to rewrite the original text. Therefore, L
The src operand of DPSB and LDPSM instructions is 16 bits.
The upper byte is masked (EaRh).
(the bit to be changed is 0), the lower byte is the changed data.
It is designed to represent data. In other words, src
src = [SO, Sl, , S7. S8. S9. ,
, S15], then [LDPSB operation] ([:SO,Sl, , ,57], and, PSB)
,or,(−[SO,Sl,, ,S7],and,
[S8. S9. ,,S15])==>PSB However'-
9 is a bit negation. For example, setting XJIag at position 2"4
The instruction to read is LSPSB #H'eflO. In the upper byte, set bits to be changed to 0 and bits not to be changed.
The reason why we set this as 1 is because the one that is changed is considered the default.
This is because we decided that it would be more natural to do so. Change all 8 bits
When changing, set all upper bytes to 10 and use simple
Just write byte data. Changing all 8 bits is
As mentioned at the beginning, PSB on the user side. This is necessary when saving and restoring PSM. LDPSB, LDPSMte, PSB, PSMノ
If you try to set the value of an unused field to "!"
, a reservation function exception (RFE) occurs. [Program exception] - Reserved instruction exception When EaRh is @-5P [Mnemonic] LDPSM src [Instruction function] 1 oad PSM Load to PSM [Instruction option] None [Instruction bit pattern and assembler notation] In Figure 240
show. [Flag change] Shown in FIG. 241. [Explanation] Transfer src to PSM. Individual PSB, PSH in user's corchin etc.
When saving or restoring is performed regardless of the meaning of the bits,
In PSM and PSB, some fields are
There are many cases where people want to rewrite the original text. Therefore, L
The src operand of DPSB and LDPSM instructions is 1
It is 6 bits (EaRh), and the upper byte is the master.
(the changed bit is set to 0), the lower byte is changed.
It is designed to represent updated data. In other words, s
rc as SrC=[SO,S,1. ,,S7. S8. S9. ,．
515], then [LDPSM operation] ([50,51,,,S7],and,PSM),or
, (-[50,Sl , ,S7],and,[S8
．． S9. ,． 515])-=>PSM However, '-9 is
The bit is negated. LDPSB, LDPSM, PSB, PSM
If you try to set the value of an unused field to "1",
, a reservation function exception (RFE) occurs. [Program exception] - Reserved instruction exception - When EaRh is @-5P [Mnemonic] 5TPSB dest [Instruction function] 5tore PSB Store from PSB [Instruction options] None [Instruction bit pattern and assembler notation] See Figure 242
show. [Flag change] Shown in FIG. 243. [Explanation] Transfer PSB to dest. The upper 8 bits are always O
Become. dest is 16 bits instead of 8 bits,
The reason why the upper 8 bits always return O is because
DPSM, LDPSB, PSM, PSB as it is
This is because consideration was given to making it possible for him to return. [Program exception] - When reserved instruction exception φEach is #imm-data, @SP+ [Ni
Monic] STPSM dest [Instruction function] 5tore PSM Store from PSM [Instruction options] None [Instruction bit pattern and assembler notation] Figure 244
show. [Flag change] Shown in FIG. 245. [Explanation] Transfer PSM to dest. The upper 8 bits are always 0.
Become. dest is 16 bits instead of 8 bits,
The reason why the upper 8 bits always return O is because
Restoring PSM and PSB directly using DPSM and LDf'SB
This is because consideration was given to making it possible to return home. [Program exception] - Reserved instruction exception fist Ea%Ilh is ltimm-data, @SP ten
[Mnemonic] LDP src, dest [Instruction function] 1oad physical 5pace physical space physics
[Instruction option] None [Instruction bit pattern and assembler notation] Figure 246
show. [Flag change] Shown in FIG. 247. [Description] Transfers the value of src to dest in physical space. 5rcO
When the size is smaller than dest, it is sign extended. Since the device of the present invention does not have an address conversion mechanism, the logical space
The address and the physical space address are always equal and this instruction
This function is absorbed into the MOV command. However, the ad
It has a response conversion mechanism and handles logical space and physical space separately.
This instruction is used to ensure software compatibility with the device of the present invention.
support. This command is a privileged command. In dest/EaWχ, register direct mode Rn
@-5P cannot be specified. LDATE, 5TATE, LOP, STP
, special space in LDC, STC, MOVPA instructions
In operands that refer to
When an indirect reference of a directory occurs, it is not the special space.
Refer to the logical space (LS). Also, the stack point
If there is a reference to InterSP, instead of PRNG,
The current ring RNG stack is referenced. The meaning of an address in a special space is based on the final result.
only the effective address given. [Program exception] - Reserved instruction exception - When RR = 'll' - When WW = 'll' When red EaR is @-5P - EaW$ is Rn, ltimm-data, @SP+,
@-5P / Privileged instruction violation exception / When executed from other than r i n8o [Mnemonic
] STP src, dest [Instruction function] 5tore physical 5pace physical space?
[Instruction option] None [Instruction bit pattern and assembler notation] Figure 248
show. [Flag change] Shown in FIG. 249. [Explanation] Transfers the value of src in physical space to dest. In STP, the size of src and dest are specified in common.
Therefore, transfer between different sizes is not performed. Since the device of the present invention does not have an address conversion mechanism, the logical space
The address and the physical space address are always equal and this instruction
This function is absorbed into the MOV command. However, the ad
It has a response conversion mechanism and handles logical space and physical space separately.
This instruction is used to ensure software compatibility with the device of the present invention.
Sabo F. This command is a privileged command. In src/EaRχ, register direct mode Rn is specified.
, immediate #imm-data specification, @sp
+ cannot be specified. LDATE, 5TATE, LDP, STP
, special space in LDC, STC, MOVPA instructions
In operands that refer to
When an indirect reference of a directory occurs, it is not the special space.
Refer to the logical space (LS). Also, the stack point
If there is a reference to InterSP, instead of PRNG,
The current ring RNG stack is referenced. The meaning of an address in a special space is based on the final result.
only the effective address given. [Program exception] - Reserved instruction exception - When enemy = 'll' - εaRX is Rn, #imm-data, @SP+, @
-When 5P・EaW is #imrn-data, @SP
+ - Privileged instruction violation exception - When executed from other than r i ngO 12-5
．． O3'f combination [mnemonic] JRNG vector (rIn the device of the present invention)
Not supported) [Instruction function] Jump to new ring Inter-ring call [Instruction options] None [Instruction bit pattern and assembler notation] Figure 250
show. [Flag change] Shown in FIG. 251. [Explanation] Perform transitions and jumps between rings (inter-ring calls)
. This instruction is executed at a ring level that is inner than the current ring.
Invoking a system call that calls a program in
(including To protect the inner ring from the outer ring, JRN
The jump destination in G is limited to a specific address. The table containing this address is the inter-ring transition table.
JRNGVT (JRNGVector table)
It is called. In the J RNG instruction, the vector operand
is the index for JRNGVT. JRNGV
One entry of T is called JRNGVTE. JRNGVT has 65 entries for vector
It is a table with 535 tables, and its base logical address is
is indicated by JRNGVB. vector's service
The size is 16 bits. JRNGVB is a control level.
It is one of the registers and has the following structure.
. -JRNGVB JRNGVB is the second JRNG command as shown in Figure 252.
Indicates the logical address of the beginning of the vector table. Tae
The lower three bits of the bull's base address are fixed to O for alignment. When E is 0, execution of JRNG is prohibited and JRNG is not executed.
Otherwise, a ring transition violation exception (RTVE) will occur. this
JRNGVB has no meaning at this time, so O5 uses this file.
Feel free to use the fields. You must put '02 in the 2=2 bit.
stomach. However, even if this bit is not 0, it is simply ignored. J RNGVTE is 8 bytes, as shown in Figure 253.
It is structured like this. This is to enter the inner ring
It has the meaning of a gate.・The AR function is the entry indicated by the vector.
interring calls can be issued from at least one ring.
It shows whether there is. than the ring shown in AR
If the current ring is on the outer side, an interring call (
system calls) are considered disallowed and
A ring transition violation exception (RTVE) will occur. AR is that
Considering the meaning, the frame corresponding to the position of PRNG of PSν is
Use fields. This is JRNGVT, EITV
Each entry in T is basically a subset of PSV+PC.
This is based on the idea that the shape of the
.・vx function is 32 times between O5 and user program.
/Effective when the 64-bit mode is different.
.・Unused field of JRNGVTE (indicated by 1=t)
), and the 'vx' bit should be set to '0'.
There must be. However, in reality, these bits
Even if jlj, it is simply ignored.
. The reason why this is not a reserved function exception (RFE) is because the imp.
This is because we considered the burden on customers. [Detailed specifications are being adjusted
]・Also, the vPC field of JRNGVTE is an even number.
Must. In other words, L of the vPC field
SB must be 10'. In case of violation,
Odd address jump exception (OAJE) when executing JRNG
) occurs. [Detailed specifications are being adjusted JRNGVB is M
UATB when SB=0(7), 5 when MSB=1(7)
Address translation is performed using ATB. JRNGVI3
The advantages of using the address as a logical address are as follows.
This is because there is. ■It is possible to have a table for each context.■Tables can be virtualized. In other words, the table itself can be page-faulted. ■The difference in personality with TRAPA, which is an EIT, is more
Kiss. By considering JRNGVB as a logical address, the table
Virtualization of virtual data becomes possible. In the device of the present invention, vector
16 bits (65536 entries, 512
B table size), and
There is no register to specify the upper limit of the vector. However, since JRNGVB is a logical address,
, can be combined with the MMU function, and does not necessarily require a tape
There is no longer a need for the burden of physical memory for the same amount of memory. Make STE and PTE of JRNGVT part unused area
If you do this, 16 bits = 65536 entries in the table.
It is not necessary to prepare all the data in physical memory. JRNGVTE can be read using logical addresses.
It is performed in the same way as general memory access. Therefore, JRNGVTE executed JRNG
Read with the ring access rights of the product. J of the specified vector from the ring that executed JRNG
If you do not have the right to read RNGVTE, the address
A ring protection violation error occurs for the conversion exception (ATRE).
. Also, JRNGVTE of the specified vector is an unused area.
address translation exception (ATRE).
) will result in an unused area reference error. Viewed from the user's perspective
and these errors are ring transition violation exceptions (RTVE)
Although it would be preferable to be treated in the same way as
Due to implementation reasons, the specifications shown above may vary.
ing. When reading JRNGVTE, please
or page out exception (POE) or bus access exception (BA).
E) etc. may occur. With the introduction of JRNG functionality, logic for JRNGVT
It will definitely consume 512B space. Also, unfair
To prevent false inter-ring calls, write your user program to
Before execution, O5 must check the STE, P in the area of JRNGVT.
It is necessary to set the TE in advance. Therefore, Rin
This process is performed when you do not use the inter-group call function.
Disable the entire ring-to-ring call feature so that it is completely unnecessary.
It can now be disabled. this
For specification, use the E bit of the LSB of JRNGVB. J
If the E bit of RNGVB is O, the ring-to-ring call machine
function will no longer be available and will not be available if you run JRNG.
The condition is a ring transition violation exception (RTVE). In the end, for JRNG to succeed, the following conditions must be met:
Must be. - If E=1゜E=O of JRNGVB, JRIIIGVT is not prepared.
This means that it is called a ring transition violation exception (RTVE).
Become. JRNGVTE for the specified vector is J
Possible to read from ring before RNG execution/Example of missing page
If this happens, try again after page-in.
Become. Address translation exception (ATRE) unused area reference error
If this occurs, there are no tables available at that point.
This means that the error occurs in the user program.
It is normal to return . If you do not have read access rights, for protection
This means that RNG execution is prohibited, so
normally returns an error to the user program.
. This has the same meaning as the VA field, but the 512 base
This is the specification of a vector phrase. --One current ring≧VR is established. − Cannot go to outer ring. In case of violation, ring transition
A violation exception (RTVE) will occur. --One current ring≦AR holds true. Check if the ring can be attached. Ring in case of violation
This results in a transition violation exception (RTVE). In addition, AR is JRN
GVTEc7) AR7E4D. [JRNG operation] if JRNGVB E bit = Othen ring transition
Violation exception (RTVE) Logical address mem[vectorX 8+JRNGV
B], select VR, AR, VPC if old RNG > AR, or, old RNG < VRt
hen ring transition violation exception (RTVE) old SP ==> TO5↓ (new star indicated by VR)
Old PC ==> TOS↓ For the old PC, the start address of the instruction following the JRNG instruction is pushed onto the stack. This is the same as the JSR instruction. Old PSW, and, [? '0ff10000-00
000000-11211111jllllllll =
=> TO5↓old PSυ is a file that has meaning in RRNG.
field, i.e. RNG, XA, PS) I(,?, 1 frame)
Only the field is pushed to the stack as is, other fields (7) SM, AT, IM^5K (7) are 0.
is masked and then pushed onto the stack. This is to prevent the outer ring program from reading information (such as group ASK) that only the OS should know. Old RNG ==>New PRNG VR==>New RNG VPC==>New PC The stack frame formed by the JRNG instruction is
It will look like the 264 diagram. Here, I loaded the old ring's SP onto the new ring's stack.
is the stack pointer SP from the new ring to the old ring.
This is to access the stack. Studs for each ring
The register is accessible as a control register;
For this purpose, privileged instructions (5TC) must be used.
do not have. So for example from ringl to r + ng
If you want to see the parameters on the stack of 3.
requires this functionality. In J RNG, only part of PSS and PRNG of PSM
is updated and the PSB is not updated. Also, inter-ring
Unlike EIT, the functions of the tool are stack format
tsu!・There is only one type, so FORMAT(EITI
NF) cannot be detected by the stack. For JRNG:E, vector is zero-extended
. If AT=00 (no address translation), JRN
GVB represents a physical address. Ring transition violation exception (RTVE) occurs when executing J RNG.
If an instruction re-execution type EIT such as JRNG
Stack frame for interring calls, a unique feature
is not formed, and the stacked flake 1 for EIT processing is not formed.
Only 1 is formed. For example, the state SMRNG=OOO
Execute BNG in state and try to jump to RNG=OO
However, if EIT occurs due to some error,
, resulting in a stack frame as shown in Figure 255. 25th
It's not Figure 6. Specifications like (A) are used after EIT occurs.
This is because we are thinking about re-executing the instruction. In other words, E
This is because, before entering the IT processing handler, it is attempted to return the state of the processor to the state before instruction execution as much as possible. The stack used in EIT and the stack used in JRNG
If the stacks are different, only the stack used by the EIT will change when the EIT occurs.
, the SP of the stack used in JRNG does not change. JRNG jumps to the same ring as the current ring.
It is also possible. In this case, stack switching does not occur in JRNG.
. The value pushed onto the stack as SP is the value of SP before the instruction is executed. This is the PU at the beginning of the JRNG instruction.
This is the same operation as executing SIISF'. This situation
is shown in FIG. 257. When jumping to the same ring as the current ring in JRNG
In this case, the Vector operand of JRNG:G is stored in memory.
There is 1. This is the stack frame formed when the JRNG instruction is executed.
If the area overlaps with the system area, re-execution of the instruction becomes extremely difficult. Therefore, with the JRNG:G instruction, memory access is
All addressing modes involving registers, ie, register direct Rn and immediate, are prohibited. If it is desired to set a dynamic value as an operand of this instruction, it is necessary to prepare one temporary register and use the register direct Rn mode. Inter-ring call functionality is not included in the EIT. TRAPA and JRNG are both O5 system code
This is a command whose purpose is to call a file. In general, there are many system calls like BT RON, and there are multiple links.
O5 uses JRNG and uses system calls like lTR0N.
For O5s where the number of rings is not so large and two rings are sufficient, TRAPA will be used.
Ru. In TRAl'A, go to ringl, rin32
Since this is not possible, the outer core is placed in rin and gl using BTRON.
If this is the case, of course it is necessary to use JRNG. In addition, if the O5 is extended by the user, an outbound inter-ring call may be required, and nTR0N also does not support such an example.
There is. However, for several reasons, such as it is not very common, it is inconsistent with the purpose of ring protection, and in order to provide complete protection, it is necessary to provide a separate return stack, which increases the burden of implementation. , does not support outgoing interring calls at the instruction set level. [Program exception] - Reserved instruction exception - When P = 'l' - EaRh! When M is other than Rn, #imm-data - <<11>> Functional exception - When the correct bit pattern of J RNG is decoded [Mnemonic] RRNG (r Not supported by the device of the present invention) [Instruction function] return from previous ring
Inter-ring return [Instruction option] None [Instruction bit pattern and assembler notation] Figure 268
[Flag change] Shown in Figure 269 [Explanation] Performs a return for an inter-ring call. [RRNG operation] ↑TO5==> templ ↑TO5==> temp2 ↑TO5==> SP of tempt<RN
G>if RNG>templ<RNG> the
n-ring transition violation exception (RTVE) activation/templ<RNG> treats templ as PSν.
represents the part corresponding to the RNG field when - Without this check, it is possible to illegally enter the inner ring using the RRNG command. tempt<PS)l>==> PSfl (PRN
G) templ<RNG>==> RNG
templ<XA>==> XA temp2 ==> In addition to P, the DCE EIT is activated when the RRNG instruction is executed.
It is necessary to check for this. See Appendix 9 for details. In this step, I'RNG's old stack pointer is transferred to RNG's old stack pointer.
Pop off the stack and return to the PRNG stack point
What is set as the printer is the one loaded on the PRNG stack.
By popping the parameters of the system call, etc.
, update the user's stack pointer from the O5 side
This is because we assumed that If you try to enter the inner ring with RRMG, the ring
A transition violation exception (RTVE) will occur. Also, is it a stack?
If the PC that was popped is an odd number, the odd number address is
A response jump exception (OAJE) will occur. The current PSW SM is 0 and is popped by the RRNG command.
RNG in the stack (during the above operation)
temp<RNG>) is not O, the RRNG instruction
By executing the command, the combination of SM and RNG in PSW
is a reserved pattern. In this case,
This results in a reservation function exception (RFE). RTVE, which is an instruction re-execution type exception in the RRNG instruction,
If an RFE occurs, the command will be empty after the RRNG instruction is executed.
Stack frame for an interring call that was scheduled to be
But it remains as it is. Therefore, EIT and inter-ring code
If the same stack was used in the previous file, the stack
Stack frame 24 of the EIT in the form of being added to the frame.
is formed. Also, EIT and interring calls are different.
If the stack is used up, it will be used for ring-to-ring calls.
The stack contents and stack pointer that were previously used will not change.
stomach. This point is different from starting DCE with RRNG.
It has become. For DCE, the previous interring call
Clear the stack frame and then use the new stack frame in DCE.
Configure the tuck frame. <<Example of stack when RFE occurs - same stack in EIT
In contrast, 0^JE is expected to be an instruction completion type EIT as shown in Figure 260.
It is fixed. [Detailed specifications are being adjusted. In that case, the speed of inter-ring calls will be changed as in DCE.]
Clear the tack frame and then clear the EIT stack frame.
This means that a system is generated. 0A with RRNG command
The stack movement when JE occurs is as follows.
Ru. <(Example of stack when OAJE occurs - same stack in EIT)
When using the stack>> (Before executing RRNG) As shown in Figure 261 (After executing RRNG and starting 0AJE) As shown in Figure 262, the PSW (top) popped from the stack by the RRNG instruction
templ) other than PSII, RNG, and XA
fields are ignored. However, programming
The above shows the start time between the JRNG instruction and the RRNG instruction.
I'SH, RNG of PSW evacuated during backup. Do not change any fields other than XA. When returning to the same ring with the RRNG instruction (32 bits),
The final value of SP is mem[1nitSP + 8] ==> SP (just
And +8 is pc, psw). This is done after PC and PSW processing.
This is the same operation as executing . The E bit of JRNGVB is not related to the operation of the RRNG instruction.
Not related. Even if the E bit is 00, the RRNG instruction cannot be executed.
The line is done. [Program exceptions] - Reserved instruction exception - When P = 'l' - <<l l>> function exception - When the correct bit pattern of RRNG is decoded
[Hiramonic] TRAPA vector [Instruction function] TRAP always Software interrupt, trap [Instruction options] None [Instruction bit pattern and assembler notation] Figure 263
[Flag change] Shown in Figure 264 [Explanation] Generates an internal interrupt (trap). This command is used when calling O5 from a user process, etc.
Make use of it. Since the EIT is activated by the TRAPA instruction,
, will definitely enter ring O. In TRAP and TRAPA, other EIT processing and
Similarly, only part of PSS and PRNG of PSM are updated.
be renewed. Fields other than PRNG of PSH (including PSB) are
Not updated. [Program exception] - Reserved instruction exception - When P = 'l' - Unconditional trap instruction [Mnemonic] TRAP [Instruction function] TRAP conditionally
Software interrupts, traps [Instruction options] / Various condition specifications (cccc) [Instruction bit pattern and assembler notation] Figure 265
[Flag change] Shown in Figure 266 [Explanation] If the specified conditions are met, an internal interrupt (
trap). The TRAP instruction activates the EIT, so the ring
It will enter 0. The method of specifying the condition is with the Bcc command.
It's the same. In TRAP and TRAPA, other BIT processing and
Similarly, only part of pss and PRNG of PSH are updated.
be renewed. Fields other than PRNG of PSH (including PSB) are
Not updated. If an undefined condition is specified in TRAP, a reserved instruction is
This will result in an exception (RIE). [Program exceptions] - Reserved instruction exception - When P = 'l' - When cccc = '1llo, 1111' - Conditional exception
UP instruction [Mnemonic] EIT [Instruction function] return from EIT Return from EIT processing (interrupt, exception handling) [Instruction options] None [Instruction bit pattern and assembler notation] See Figure 267
[Flag changes] Shown in Fig. 268 [Explanation] In the "apparatus of the present invention", exceptions, external interrupts, internal interrupts
These are collectively called EIT (Exception, Interrupt, Trap). REIT instruction
is the return from EIT, i.e. the return from O5.
Used to return from a call or interrupt processing.
This is an order to do so. This command is a privileged command. [REIT operation] ↑TO5==>PSW;↑TO5==>FORMAT/VECTOR; ↑TO
5==>PC; In addition, depending on the type of EIT, it may be added to the stack.
Information may be loaded. Pop it and return to the state before the EIT occurred.
vinegar. Use FORMAT/VECTOR (EITINF) to determine the presence or absence of additional information.
to be determined. Also, when executing the REIT instruction, Dl, DC
EIT may be activated, so check it.
I need to do it now. See Appendix 9 for details. Not supported as FORMAT/VECTOR
Reserved if stack format was specified.
This results in a stack format exception (RSFE). In this case, the incorrectly formatted stack frame
The system is left as is because it is not possible to determine whether additional information exists.
and the RSFE is added to its stack frame.
A stack frame is formed. This point is true for REITs.
This is different from the old case of starting DCE. DI,
In case of DCE, click the previous EIT's stack frame.
After rearranging, DI, DCE's new stack frame 1
1. << RSFE processing - Using the same stack for RSFE
If the PC popped from the stack is an odd number with the REIT instruction shown in Figure 269
, an odd address jump exception (OAJ
E). Also, the PSW popped from the stack
Therefore, the bit of reservedC-') in PS-
(including the XA bit) to 11'
If so, write the reserved value as SMRNG.
If an attempt is made, a Reservation Function Exception (RFE) will result. There is no particular check for changes in 5M bits. E.I.
As long as you use the REIT instruction to return from T, the RεI command
The button should not change from 1 to 0 depending on the entire command line.
It is. However, this should be addressed as an operational issue.
Then, in the REIT instruction, check whether SM has changed from 1 to 0.
No checks will be performed. [Program exceptions] - Reserved instruction exception - When P = 'l' - Privileged instruction violation exception - When executed from other than r i ngO - Reserved instruction exception
Unsupported format exception when returning from EIT
- When the stack format is specified - Odd address jump exception - When the PC popped from the stack is an odd number - Reservation function example - exception
When attempting to write the reserved value in [Mnemonic] νAIT imask [Instruction function] set IMAsK and wait stop, interrupt
Waiting [Instruction option] None [Instruction bit pattern and assembler notation] Figure 270
[Flag change] Shown in Figure 271 [Explanation] Set the group ASK field of PSW and change the program.
Stop execution. Executed by external interrupt or reset
Resume line. This command is a privileged command. imask is interpreted as an unsigned number. If imask≧16, Reservation Function Exception (RFE)
occurs. In the case of an external interrupt, it cannot be determined until the interrupt occurs.
No information (SPI/SPO stack selection, vector
number). Therefore, in the WAIT instruction, the external
After the input occurs, the information is saved to the stack. [%IIAIT operation] imask ==> IMAsK wait for 1ninterrupt (=: External interrupt
Inclusion [Program exception] - Reserved instruction exception - When -='1ゝ - Privileged instruction violation exception - When executed from r t ngo [Mnemonic] LDCTX ctxaddr [Instruction function] 1 oad context from CTXB context
Load text [Instruction option] /LS Load CTXB from logical space /C5 control empty
Load CTXB from between <<L2>> [instruction bit
[Pattern and assembler notation] Shown in Figure 272 [Flag change] Shown in Figure 273 [Explanation] Set the effective address indicated by ctxaddr to the CTXBB register.
the task or process context block.
Loads the contents of the lock (CTXB) to the processor register.
code. The register to be loaded is
It varies depending on the contents of nothing and CTXBFM, but SPO ~
SP3. Includes UATB, C5W, etc. LDCTX
See Appendix 8 for details of registers transferred in
About. If the /LS option is specified, ctxaddr
means an address in logical space. In this case, the logic
This means that CTXB is placed in space. Also,/
If the CS option is specified, ctxaddr is
It means the address of the control space. This option is
In the future, high-speed memory for saving context will be built into the chip.
It is intended to be used in cases where <
<L2>>. These options
Fastest speed for chip and chip bus implementations
Place CTXBft to perform a context switch
It was created for the purpose of giving space a degree of freedom.
be. rThe device of the present invention does not support the /CS option.
. In the processor with a built-in standard MMU of the "device of the present invention"
, LDCTX commands change the UATB. In this case, if the processor does not implement LSID,
Purge TLB and cache due to UATB change (
Processing equivalent to PSTLB/AT) is automatically performed.
Ru. The LDCTX instruction switches the logical space.
To ensure that the LDCTX/LS performs meaningful operation.
, ctxaddr must point to SR. L
DCTX/LST! ctxaddr pointed to UR
Operation is not guaranteed in this case. rThis invention device J (7) With LDCTX and 5TCTX commands
does not transfer general-purpose registers RO to R14.
. This is due to the following reasons. One general-purpose register is transferred using the LDM and 57M instructions.
If it is LDM or STM, it is possible to
It is also possible to specify. of the actual context switch
During processing, the working register is
Since you often need registers for
It may be better not to forward the data. therefore,
Use more generic instructions like LDM, STM
is more appropriate. Currently, there is still memory for saving context on the chip.
It is technically difficult to incorporate it, and it is difficult to save the context.
must use external memory. - In that case, L.D.
Even if the CTX transfers the general-purpose register, the general-purpose register
Even if you use a separate instruction (LDM) to transfer the
There is no difference. - In the future, build all CTX B into chips to increase speed.
In this case, l, DCTX reserved
Expand specifications using options and CTXBFM functions
Just do it. Also, in the LDCTX and 5TCTX instructions, PC, P
SS/(7) No transfer is performed. This is as follows
Due to reasons. - In general, it is necessary to switch by context switch.
What is important is not the O5 PC or PSv, but the user platform.
Logera 11 PC and PSW. However, the user
The program's PC and PSW are normally used when O5 is called.
It has been saved in the stack. Therefore, we recommend using the SPO stack to save PC and PSW.
If you set it to , you can switch SPO with context switch.
By downloading the PC. PSW is also switched indirectly. Take advantage of this proactively.
and is indirectly referenced from SPO as the structure of CTXB.
so that the PC and LPSW are placed in the part (stack) that
If you think about it, the basket context switch life
In the order, PC, PSW. Perform operation (copy between stack and CTXB) No need to self-reflect. - End of external interrupt processing handler using 5PI
What if you want to do a direct context switch with
Even if the PC and l'S are connected between the SPI stack and CTXB,
Transfer of W is required. But in this case, the external interrupt
Delay context switches and interrupt external interrupts
When exiting from a scene, use DCE or Dl to create a context
If you do the switch, by specifying SPO in DCE or old
, the above data structure can be realized naturally. The second command is a privileged command. , PSv reset set by DCTX
ved pit C-9), CTX
Bb) If you try to load 5'1', the reservation machine
An upper exception (RFC) occurs. In addition, regulations such as UATB
Reserved bit of W register (displayed as 1=1)
), CTXB to 11? Let's load
If so, it will simply be ignored. This depends on the LDC.
This is the same as when trying to set a control register.
Ru. For chips with <<Ll>> specifications, AT=OO (address
UATB transfer is also performed in the case of (no conversion). This temporarily halts address translation within O5 only.
This is because such a case is possible. However, AT=
00, ctxaddr is invalid even if /LS is specified.
treated as a physical address. To specify not to transfer UATB in LDCTX
, using CTXBFM. However, the current specifications of DCTX do not allow general-purpose register transfers.
is not. However, if the specifications are expanded in the future,
If memory for saving text is built into the chip
To load multiple general-purpose registers with the LDCTX instruction,
There are plans to do so. In that case, ctxaddt/Ea
A! If additional mode is allowed in A, similar to LDM,
If an instruction is interrupted midway through, it becomes difficult to re-execute the instruction. Therefore, ctxaddr/EaA of LDCTX! A
In this case, additional mode is prohibited. Definitely additional mode
If you want to use the function of MOVA, use MOVA @(@(@(,,,))):A,RO
Equivalent functionality can be achieved by using LDCTX @RO. [Program exception] - Reserved instruction exception - When XX = '01' to '11' (7) - EaA is R
n, #imm-data, [i! SP+, @-5P, included
When in addition mode - Privileged instruction violation exception - When executed from other than r i ngo - Example of reserved function
When writing the outside/PS and reserved values, [N]
Monic] TCTX [Instruction function] 5tore context to CTXB context
Store [Instruction option] /LS Store CTXB in logical space /C5 control empty
Store cTXB in between <<Ll>> (under consideration) [Instruction bit pattern and assembler notation] See Figure 274
[Flag change] Shown in Figure 276 [Explanation] The contents of the current context in the processor are
It is saved to the area (CTXB) indicated by the B register. Retirement
The registers to be avoided depend on the presence or absence of MMu and CTXBF.
Although it varies depending on the contents of M, SPO to SP3. U.A.T.
B, C5W, etc. are included. 5TCTX teletransferred record
See Appendix 8 for details on registers. 5TCTX, like LDCTX, has general-purpose registers and
Transfer of pc and psw is not performed. The space pointed to by CTXBB is 8S, /C5 option
Specify with. However, 1. , /CS option will be available in the future
When memory for context saving is built into the chip
It has meaning for the first time, and becomes <<Ll>>.
There is. rThis invention device does not support the /CS option.
stomach. rThis invention device"In a processor with a built-in standard MMU,
, 5TCTX command saves tJATB. In this case, 5TCTX/LS performs meaningful operation.
, CTXBB must point to SR, but C
Especially check whether TXBB refers to SR or UR.
Don't do it. This command is a privileged command. Control register re saved to CTXB at 5TCTX
Among the served bits, l −1, 94t bits
For
Rel, Mata, *=1. ′＠Z′＊＃Nobitnitsuite is
, CTxB The value to be reset is undefined and depends on the implementation.
It depends on the client. These are similar to STC instructions. (For chips with <Ll>> specifications, AT=OO(address
tJATB is also transferred in the case of (no conversion). This temporarily halts address translation within O5 only.
This is because such a case is possible. However, AT=
In the case of OO, CTXBB is a physical address even if /LS is specified.
treated as a dress. To specify not to transfer UATB with 5TCTX
, using CTXBFM. [Program exceptions] - Reserved instruction exception When φxx = other than 'oo' - When P = 'l' - Privileged instruction violation exception - When executed from a ring other than ring 0 12-16- MMU, j! ! it command [mnemonic] AC5chkaddr [instruction function] test access rights
[Instruction option] None [Instruction bit pattern and assembler notation] Figure 276
[Flag change] Shown in Figure 277 [Explanation] AT of the page that includes the address specified by chkaddr
Check E, chkaddr is accessible from PRNG
Check whether The file will be displayed depending on the check result.
Set the rug. Readable ==> Mjlagwrite possible
Noh ==> ZJIage execute possible =
=> L-flag This instruction is not a privileged instruction and is
It is also possible for the user to use For example r i ng3
Check access rights for PRNG=ring3 from
You can also do that. Therefore, O5 such as page out
Information that should be managed is hidden from view as much as possible.
. Sections required for running AC5
able and Page table are paged out.
If there is a page fault example, just like a normal instruction,
Execute the instruction again as an outside (POE). In addition, while referencing ATE with AC5 instruction, address
Conversion exception (ATRE), bus access exception (BAE)
This may occur. The size of the operand tested with the ACS instruction is bytes.
I think so. In other words, 1 byte of the address indicated by EaA
Indicates whether the target is accessible from the PRNG. multiple
When checking an area that spans bytes, use the software
Please deal with this issue using software. AC5 handles the processing request from the previous ring.
When checking access rights, the PRNG is
Available. However, for example, from r i ng3 to rin
Request processing to g2, and further ringl from ring2
If you want to call , use ringl to call r i ng3
You may want to check access rights from. At this time
, PRNG is ring2, so leave it as is.
It is not possible to use AC5 instructions and r i n
It is necessary to rewrite it to g3 and then execute AC5. In order to respond to such requests, PRNG receives requests from users.
It is also placed in an operable PSM. PRNG is AC5
A field that has the meaning of a parameter for an instruction
It is. However, if this continues, r i ng3 to rt
You will even be able to see the NGO's protected information. Therefore, PR
When NG < RNG, leave it unconditional - flag = gate
-flag = ZJla3 = 0
This prevents protected information from being visible. In AC5, chkaddr is an unused area (page
If it is invalid (outside the range), R is not allowed, V is not allowed, and E is not allowed.
Similarly, MJlag=O,Z-flag=O,L-
f I, ag=0 Normally terminates the instruction with no access rights
It shall be. It is not an IEIT. Also, if AT=OO (no address translation), link
There is no check for protection on all addresses, so all
Assume that you have access rights to the in fact
, the access is interrupted due to a bus access exception (BAE).
There are some areas that cannot be checked, but please check them.
do not have. This is an access error caused by the system bus.
There are different levels of access errors caused by erroneous protection.
AC5 only checks the latter.
This is to think. Therefore, if AT=OO,
No exception occurs after chkaddr is obtained.
, LJlag=town flag=ZJIag=1 (access
The order shall be terminated as follows: AC5 instruction is an instruction emulation program.
Accurately emulates ring protection level checks
This command can be used if you want to. emulation
The program is usually placed in ringO, so you can emulate it.
The instructions being rated are executed in a different ring than the instructions being rated.
It's normal. So in terms of the level of ring protection,
emulated programs, and
program has a different environment. Therefore, emulator
A before accessing the operands of the rated instruction.
The operand is emulated by the C5 instruction.
Can it be accessed from the same ring (PRNG) as the instruction to be used?
If you check the
This makes it possible to carry out the process properly. In AC5 chkadd r effective address calculation
, if the stack pointer SP is referenced, PR
The current ring RNG stack is referenced instead of NG.
. [Program exception] - Reserved instruction exception - EaA is Rn, #imm-data, @SP+, @-
At the time of 5P [Mnemonic] MOVPA 5rcaddr, dest (r book
[Instruction function] move physical address physical address
Transfer of responses [Instruction options] None [Instruction bit pattern and assembler notation] Figure 278
[Flag change] Shown in Figure 279 [Explanation] The effective address of the operand specified by 5rcaddr (
logical address) and convert it to a physical address.
and then transfer it to dest. Obtained by 5 rcaddr
The method of address conversion for effective addresses is different from that for normal instructions.
Therefore, the address is the R1 register instead of the UATB register.
used as the base address of the address translation table. this
is the logical space where the program is currently running from O5 etc.
This is to enable operations on other spaces.
Ru. This instruction allows you to register a fixed number register like the high-function instruction.
The reason why data is used for spatial specification is that it is used directly in high-level languages.
Since the command never occurs, there is no need for symmetry in the command.
This is due to the fact that there are constraints from bit allocation. In the MOVPA instruction, after getting 5 rcaddr,
During the process of converting it to a physical address, a page error occurs.
If an exception, address translation exception, etc. occurs, the error
- will be reflected in the flag and EIT will not start. This is 5r
5ection used for caddr address translation
Tables and Page Tables are paged out.
, the last page (in the page table)
) is paged out, further convert table
Error in format I of entry (ATE) (reservation AT
This includes cases where there is an E error). At this time, de
st does not change, Vjlag is set and the instruction ends
do. Also, whether there is a page fault or not is determined by FJ.
Indicated by Iag. No errors or page faults,
If the command ends normally, VJlag is cleared.
It will be done. This instruction can basically be thought of as an address operation.
The other flags remain unchanged. Figure 280 summarizes the flag changes of the MOVPA instruction.
become that way. In addition, at 5TATE, Vjlag=O, F-flag=1
If it corresponds to (page out of the next stage), MOVP
In A, Vj Iag=1. F, f Iag=1 page
Since it is absorbed in case of out, 5TATE and MO
The pattern of flag change is different from VPA. 5rcadr, dest, etc. until you get the effective address.
If a page fault occurs during the process, the normal
A page not found exception (POE) is fired just like the instruction.
Ru. This command is a privileged command. dest/EaW! In S, @-5P mode is prohibited.
ing. This is caused by an error or page out.
If VJlag is set and dest cannot be transferred.
In this case, if @-5P is specified for dest, the command will operate.
This is because it is difficult to be confused. LDATE, 5TATE, LDP, STP, LDC
, STC, MOVPA instructions that refer to special spaces.
In perando, memory indirection is performed using append mode.
occurs, the logical space (
Please refer to LS). Also, the stack pointer SP
If there is a reference, the current ring R instead of PRNG
The NG stack is referenced. Special space address
Only the effective address finally obtained has meaning.
It is. MOVPA, LDATE, 5TATE commands
If the ASB of the dress is 1 (indicates SR), R1
So < 5 Perform address translation using ATB. Ma
When you stop it, it will look like Figure 281. Between VPA, LDATE, 5TATE, add
Set the pace register for response conversion to R1 instead of UATB.
It is specified by At this time, UATB reser
The bit of R1 corresponding to the ved part (expressed as =”
2"4.2"50 bits) is not 'l', especially
It is not checked and is simply ignored. This is an imp
This is because the burden on customers was taken into account. Even if no check is performed, R1's 2"4°2"
Make sure to put '0' in bit 5.
It is necessary to provide guidance through manuals, etc. After getting the effective address of 5rcaddr, use R1.
until the address is translated and the physical address is obtained.
The operation of is not affected by the AT bit. In other words, A.T.
Even if =00, 5rc is the same as when AT=01.
The address translation of addr is performed and the physical address is obtained.
It will be done. This instruction is used as a preparation before address translation.
This is because it was assumed that . Of course, 5r
Caddr, dest effective address calculation (indirect reference)
etc.) or dest is written to the physical address when AT=OO.
It is performed on a dress subject. [Program exception] - Reserved instruction exception - When + = 90' - When enemy = '11 - εaA is RnJimm-data, Iiii! SP+,
(When i!-5P, φEaW!S is #imm-data, @SP+, li!
-5t'・<<ll>>Functional exception ・Correct bit pattern of MOVPA was decoded
Time [mnemonic] LDATE src, destac! dr(``Book
[Instruction function] 1 oad address translation
Load table entry ATE [Instruction option] /AS Purge TLB of all logical spaces 155 Logical space with SID specified by RO
Purge the TLB of <<L2>>/PT P
TE operation/ST STE operation [Instruction bit pattern and assembler notation] Figure 282
[Flag change] Shown in Figure 283 [Explanation] Effective address of the operand specified by destaddr
(logical address) and convert it to physical address
Address translation table entry (A
Transfer the data obtained by src to TE).
cormorant. The address translation method for destaddr is
Unlike regular instructions, the R1 register is used instead of the UATB register.
register to the base address of the address translation table (physical
address). This is currently from O5 etc.
Operations on spaces other than the logical space in which the program is running
This is so that they can also do some work. destaddr
If the MSB of is 1 (indicating SR), it is not R1.
5 Perform address translation using ATB. For both /PT option and /ST option
, R1 is the base address of 5ection Table
refers to As a result, in the case of /PT, there are two stages of indirect references, /ST
In this case, one stage of indirect reference is performed. If the setting to the ATE is successful, the ATE
TLBs and logical cues affected by value changes
will be purged automatically. However, SID is a system that supports multiple contexts (processes and tasks).
) TLBs are allowed to mix, this is a number that distinguishes them.
be. In the case of a TLB that can distinguish between multiple logical spaces,
, by specifying the /SS option.
TLB whose LSID matches the LSID indicated by RO
can only be purged. In addition, the theory currently in use
The SID for the physical space is placed in the LSID control register.
However, it is not directly related to the execution of this command. Mail
Memory management and TLB configuration are highly implementation dependent.
By the way, when implementing this instruction, it is not always necessary to
There is no need to implement the .155 option. Ma
Furthermore, the LSID function is not essential either. /SS O
This option is available only for processes with LSID.
This is to ensure compatibility with processors that do not have a 510 processor.
be. See PSTLB section. This instruction allows you to register a fixed number register like the high-function instruction.
The reason why data is used for spatial specification is that it is used directly in high-level languages.
Since the command never occurs, there is no need for symmetry in the command.
This is due to the fact that there are constraints from bit allocation. With this command, errors in the ATE itself, page outs, etc.
, to distinguish between various cases, jflag, VJI
Use ag. The behavior in each case is as follows:
It becomes like this. 1. 5ec used for address translation of destaddr
Ti. n Of the Table and Page Table, the operations
A format error (Reservation A
TE error) In this case, the ATE to be operated cannot be reached.
Therefore, setting to ATE is not performed. VJlag=1
．． F-flag=o and the instruction ends. 2. 5ec used for address translation of destaddr
Ti. n Of the Table and Page Table, the operations
The table containing the ATE of the stage that is, or the stage above it.
If the table is paged, in this case as well, the target ATE cannot be reached.
Therefore, setting to ATE is not performed. V-fla3=
1. Fjlag=1 and the instruction ends. In addition, on the way
In the middle ATE, the reservation ATE error and the next page out
If the errors occur at the same time, the reservation ATE error is
Priority is given to Vjlag=1 and F-flag=o. 3.Otherwise In this case, the data in src is set to ATE.
, V, , flag becomes 0. AT by LDATε
If the P1 bit of the data set in E is O, then
Fjlag
=1. Also, the set data is reserved as ATE.
If it is something that causes an ATE error, then
FJIag=1. These two cases are set
An exception occurs when trying to perform address translation using ATE
What they have in common is that it occurs. If there is no error in the set ATE and the P1 bit is 1,
In this case, F-flag:0. Figure 284 summarizes the fluctuations of the DATE command.
It becomes like this. This instruction is basically considered an address operation;
flag, Zjlag, etc. do not change. Also, src
, destaddr, etc. until the effective address is obtained.
If a page fault occurs during the
A page out exception (POE) is triggered in the same way. This command is a privileged command. LDATE/ST is equivalent to PSTLB/ST
However, DATE/PT corresponds to PSTLB/PT.
Processing is done automatically. LDATE, 5TATE, LOP, STP, LDC, S
Operators that refer to special spaces in TC and MOVPA instructions
Attach mode causes memory indirection in
In this case, use the logical space (LS) instead of the special space.
). Also, reference to stack pointer SP
, the current ring RNG instead of the PRNG
Stack is referenced. Special space address
Only the effective address finally obtained has any meaning.
Ru. Between VPA, LDATE, 5TATE, add
Set the base register for response conversion to R1 instead of UATBO.
It is specified by At this time, UATB reser
The bit of R1 corresponding to the ved part (expressed as '='
2″4.2-5 bits) is not Jt, especially
It is not checked and is simply ignored. This is an imp
This is because the burden on customers was taken into account. Even if no check is performed, R1's 2"4°2-
Make sure to put '0' in bit 5.
It is necessary to provide guidance through manuals, etc. When LDATE is executed with AT=OO, the src phase is
The effective address calculation for
This is done without address translation, just like the command. but,
The LDATE command operation itself is not related to the value of AT.
stomach. That is, even if AT=OO, the obtained des
The execution address of taddr is interpreted as a logical address.
and the AT used when converting it to a physical address.
Transfer src to E, which is the address
This instruction is intended to be used as a preparation for conversion.
It's for a reason. If AT=OO(7) (7) LDATE, 5TATE
, MOvPA(7) specifications are the specifications for AT=01.
In addition to consistency, the OS first sets the MMU operating environment.
Also, the user program is available to
There is no contradiction if 05 moves at AT=01 and O5 moves at AT=OO.
It was decided with the intention of making it available for use.
. [Program exception] ・Reserved instruction exception ・When +R='Th (not detected when 1=?oj)
) When P='l', when ttt='oxo' to '111', when EaR is @
-5P, ΦEaA is Rn, #imm-data, @SP+, @-
When 5P ・<<l l>>Functional exception ・The correct bit pattern of DATE was decoded
Toki [Mnemonic] 5TATE 5rcaddr, dest “This invention
[Instruction function] 5tore address translation
Store table entry ATE [Instruction options] /PT PTE operation/ST STE operation [Instruction bit pattern and assembler notation] Figure 285
[Flag change] Shown in Figure 286 [Explanation] The effective address of the operand specified by 5rcaddr (
logical address) and convert it to a physical address.
Entries in the address translation table (AT
Read E) and set it to dest. 5rcaddr
The effective address conversion method for
Unlike the command, the R1 register is used instead of the UATB register.
to the base address (physical address) of the address translation table.
used as a This is currently a program from O5 etc.
It also performs operations on spaces other than the logical space where the RAM is running.
This is to make it wow. In addition, 5 rcaddr
In case of MSBtfil (indicates SR), in R1
Address translation is performed using 5ATB instead. For both /PT option and /ST option
, R1 is the base address of 5ection Table
refers to As a result, in the case of /PT, there are two stages of indirect references.
, /ST, one stage of indirect reference is performed. This instruction allows you to register a fixed number register like the high-function instruction.
The reason why data is used for spatial specification is that it is used directly in high-level languages.
Since the command never occurs, there is no need for symmetry in the command.
This is due to the fact that there are constraints from bit allocation. With this command, ATE reservation ATE errors and page missing
In order to identify various cases such as errors, FJla
2<, use V-fla3. in each case
The operation is as follows. 5ect used for address conversion of 1.5rcaddr
Operation of ionTab+e and Page Table
There was a TE error in the reservation on the ATE in the higher level than the one in the previous stage.
In this case, the target ATE cannot be reached.
Therefore, reading of ATE is not performed. V,,,f
lag=1. F-flag becomes 0 and the instruction ends.
. 5ect used for address conversion of 2.5rcaddr
Of ionTable and Page Table, the operation
The table containing the ATE of the stage to be created or higher
If the table in the second row has been paged out, in this case as well, it is not possible to reach the ATE that is the target of the operation.
Therefore, reading of ATE is not performed. Vj Iag=
1, F-flaB=1 and the instruction ends. In addition
, At the middle ATE, reservation ATE error and next page
If outs occur at the same time, a reservation ATE error will occur.
Priority is given to V-flag=l and F-flag=0.
do. 36 Otherwise, in this case, ATE is read and set to dest.
and V-flag becomes 0. Read by 5TATε
If the P1 bit of the discovered ATE is O, then
FJIag=1 to indicate page-out of the lower row.
becomes. Also, the read ATE is a reserved ATE error.
If this does not occur, then F− “lag=
It becomes 1. In these two cases, the read eight TEs are
An exception occurs when trying to perform address translation using
They have this in common. The read ATE has no reserved ATE error and the P1 bit is
When the set is 1, FJlag=O. Figure 287 summarizes the flag changes of the 5TATE instruction.
become that way. In addition, considering the meaning of flag changes, it is compatible with Fjlag, or, V-flag of 5TATE.
The corresponding one is MOVPA's V, jlag,
The flag change pattern is different between 5TATE and MOVPA.
It's different. This instruction is basically considered to be an address operation, so M
JIag, Z-flag, etc. do not change. Also, 5r
Until you get the effective address such as caddr, dest, etc.
If a page fault occurs during the process, a normal instruction
A page fault exception (F'OE) is raised in the same way as
. This command is a privileged command. dest/EaW! In S, @-5P mode is prohibited.
ing. This is caused by reservation ATE errors in the middle or page failures.
VJIag is set due to the occurrence of
FA-S P h to dest if transfer is not possible.
<This is because if specified, the command operation will be difficult to confuse.
be. LDATE, 5TATE, L Kano, STP, LDC, ST
C. Operan that refers to special space in MOVPA instruction
Attach mode causes memory indirection in the
In this case, the logical space (LS) is used instead of the special space.
Please refer to Also, if the stack pointer SP is referenced, 1
．． The current ring RNG stack is referenced instead of PRNG.
be done. The address that has the meaning of a special space is
Only the effective address finally obtained. If 5TATE is executed with AT=OO, 5rcadd
The effective address calculation for r and dest is similar to other instructions.
This is done without address translation. However, the 5TATE command operation itself is based on the ATO value.
It doesn't matter. In other words, even if AT=OO, we can obtain
The effective address of 5rcaddr is a logical address.
and is used when converting it to a physical address.
Transfer the ATE to dest. This is an address translation
Because we assumed that this instruction would be used as a preparation for
It is. Address conversion between VPA, LDATE, and 5TATE
's pace register by R1 instead of UATB
Specified. At this time, UATB's reserved
The bit of R1 corresponding to the part (2' expressed as 9)
``4.2'' 5 bits) even if it is not jll, especially chie
No tsk is made, it is simply ignored. This is an implementation
This is because the burden on the client was considered. A check is performed
Even if the
Instruct them to insert 20′ using manuals, etc.
There is a need. [Program exception] - Reserved instruction exception - When +=10' - When enemy:'19 - EaA is Rn, #imm-data, @SP+, @-
At 5r'・EaW! S is #imm-data, @SP+, @-5
When P ・<<l l>>Functional exception ・Correct bit pattern of 5TATE was decoded
[Mnemonic] PTLBCr Not supported by the device of the present invention. That is, (R2). ) [Instruction function] purge TLB Purge TLB [Instruction options] /As Purge all logical space B /S
T of the logical space with the LSID specified by S RO
Purging LB [Instruction bit pattern and assembler notation] Figure 288
[Flag change] Shown in FIG. 289 [Explanation] Purges the TLB. Perform detailed operations such as locking and enabling TLB
A control register is used for this. However, it is recorded in the TLB.
If you only perform purge operations, use controls just for that purpose.
Adding control registers is a heavy implementation burden.
Therefore, a separate TLB purge instruction is provided. LSID refers to multiple contexts (processes and tasks).
) of T1. Number to distinguish if B is allowed to mix.
It is. /SS option, indicated by RO.
Only the TLB in the logical space with S10 is purged.
. Note that the LSID for the logical space currently in use is L
Although it is placed in the SID control register, execution of this instruction
is not directly related. With the PTLB instruction, only the TLB at a specific logical address can be accessed.
There is no purge function, all T in the specified logical space
LB is purged. Pass the TLB for a specific logical address.
If you want to log, use the PSTLB instruction. However, /S
If the S option is specified, the specified logical space
Only UR B is purged, SR is not purged at all.
I can't get used to it. When purging the SR part, be sure to use /AS.
There is a need to. This command is a privileged command. Memory management and TLB configuration are highly implementation dependent.
This is a strange place, so this command is written as <<L2>>.
. Also, when implementing this instruction, not all
There is no need to implement this option. LSI
Function D is also not essential. For PTL8, even when AT=00, when T=01
The purge is executed in the same way. This is the address translation
Assuming that the PTLB instruction is used as a preliminary preparation,
It's a good thing. [Progera 11 exception] - Reserved instruction exception [mnemonic] PSTLB pr3addr (rThis invention device)
Not supported. In other words, (L2). )【order
Function] purge 5specific TLB specific address
Purge TLB [Instruction option] /AS Purges TL[3 of all logical spaces]
TL of the logical space with the LSID specified by 15SRO
Purge B/PT Entire logical address (2”31 to 2-12 bits)
) purges entries matching prgaddr.
In other words, purge the affected parts when changing I'TE.
/ST Logical address 2”31 to 2°22 bits
purges entries that match prgaddr, i.e. purges the parts that are affected when the STE is changed.
/AT 2'''31 bit of logical address is prg
Purge entries that match at+dr, i.e. affected when changing UATB, 5ATB
[Instruction bit pattern and assembler notation] Figure 290
[Flag change] Shown in FIG. 291 [Explanation] Purges the TLB of a specific logical address. If the /PT option is specified, the target logic
Of the rLB of the space, the index corresponding to STE to PTE is
The corresponding logical address (that is, the entire logical address) is p
Purge those matching ry, addr. Also,/
If the ST option is specified, the target logical empty
Among the TLBs between, the logic corresponding to the STE index
purge those whose address matches prgaddr
. /AT option specifies the target argument.
Of the physical space cache, the MSB of the logical address is p
Purge all entries matching rgaddr. LSID refers to multiple contexts (processes and tasks).
) TLBs are allowed to mix, this is a number that distinguishes them.
be. /SS option indicated by RO
Only the TLB of the logical space UR with the LSID is purged.
It will be done. The LSID for the logical space currently in use is
, is placed in the LSID control register, but this instruction's
Not directly related to execution. This command is a privileged command. Memory management and TLB configuration are highly implementation dependent.
This command is written as <<12>> because it is a strange place.
. Also, when implementing this instruction, not all
There is no need to implement this option. LSI
Function D is also not essential. The /AS and /SS options depend on the presence or absence of LSII).
This option is provided to maintain compatibility. meaning
In terms of taste, only /SS can always be specified in the case of PSTLB.
However, in the case of r'sTl, B, always specify /SS.
Therefore, there is a risk that compatibility will be lost depending on the presence or absence of LSID.
There is. For example, if a process without LSID functionality is
Once the server is created, the program that runs on it will be sent to the RO.
Execute PSTLB command without setting SID
It will become a thing. The same program will be used in the future for SID
If executed on a processor with
Due to the rubbish that was floating around, it was decided against a completely random LSID.
Then PSTLB will be executed. To prevent this
option, if you have not set the RO.
Specify /AS if RO is set in the future, /SS if RO is set in the future.
It is sufficient to specify the /As finger in PSTLB.
The definition has this meaning. Therefore, for PSTI, B, /AS/PT /AS/ST /S5/PT /SS/ST are all valid, and /SS is the TL of the UR in the logical space specified by RO.
Purge B/As purges TLB for all logical spaces, A
TLB performance on processors without SID functionality
page (/PT and /ST options are also valid, RO is not used)
(not used). /AS option allows processors with LSID
However, if a processor without SID uses a common program,
You can write it, but you won't be able to take advantage of the LSID functionality. one
However, if you use the 155 option, you can take advantage of the SID function.
However, unimplemented options are available for processors without LSID.
This causes an error (such as a reserved instruction exception). The /SS option is specified in the PTLB and PSTLB commands.
If specified, T1. of the UR of the specified logical space. B
SR is purged, and SR is not purged at all. When purging the SR part, be sure to use /AS.
There is a need to. PTLB, PSTLB/SS
The behavior when options are specified is summarized as follows.
It becomes like this. Purge the UR of the logical space specified by PTLB/SS RO PSTLB/SS/AT @uraddr ;ur
addr purges tJR of the logical space specified by URRO PSTLB155/AT @5raddr ;5r
addr specified SR with SR/SS, so if you want to purge the entire SR without doing anything, use PSTLB/AS/AT @5raddr PSTLB/SS/l'T @uraddr ;u
raddr purges part of tJR in the logical space specified by URRO PSTLB/SS/I'T @5raddr ;5
raddr is SR/SS″r: SR is defined as 1, so if you want to purge a part of SR that does nothing, use PSTL [l/As/Pd1i!5raddr.
If it is difficult to implement the /ST option in PSTLB for
, I decided to degenerate the functionality and run it as is for compatibility.
However, it is not considered an EIT. Specifically, instead of /ST
/AT operation will be performed. If PSTLB is executed with AT=OO, prgadd
The effective address calculation for r is performed using the address
This is done without conversion. However, the instruction behavior of PSTLB
That is not related to the value of AT. That is, AT=
Even if it is 00, the effective address of the obtained prgaddr
The address is interpreted as a logical address, and when AT=01,
Purge is executed in the same way. This uses the PSTLB instruction as a preparation for address translation.
This is because it was assumed that it would be used. [Program exception] - Reserved instruction exception - 6'lt1. [1if” Set reference line
: Instructions not supported by the device of this invention (data transfer instructions)
) MOV src, dest Data movement and sign extension MOVU src, dest Data movement and zero extension PUSH src Bush to stack POP dest Stack to pop STM regl ist, dest multiple registers
Data storage DM src, reglist multiple registers
Load MOVA 5rcaddr, dest effective address
PUSHA srcaddr Push effective address onto stack (compare/test instruction) CMP 5rcl, 5rc2 Compare, sign extend and compare CMPU 5rcl, 5rc2 Zero extend and compare CIl bound, 1ndex, xreg allocation
Check column range (arithmetic operation instructions) ADD src, dest Addition, sign extension and addition ADDLI src, dest Zero extension and addition ADDX src, dest Addition including carry 5LIB src, dets Subtraction, sign extension and subtraction 5IJBU src, dest zero extension and subtraction SU[3X src, dest subtraction with carry MUL src, dest multiplication MULLI src, dest unsigned multiplication MLILX src, dest, tmp extension multiplication,
DIV src, dest division old VU src, dest unsigned division DIVX src, dest, tmp extended division, support
The size becomes smaller, and the remainder is generated REM src, dest Remainder REMLI src, dest Complement operation of the remainder N EG des from unsigned division <<L2>> INDEX 1ndexs
ize, 5ubscript, xreg multidimensional array access
Dress calculation (logical operation instruction) AND src, desL OR
ORsrc, dest OR XORsr
c, dest Exclusive OR NOT dest Invert all bits (shift command) SHL count, dest Logical shift
SHA count, dest 7F-
Technique shift ROT count, dest
Rotation 5) IXL dest Extended left shift
5HXRdest Extended right shift RV
BY src, dest By l-reverse order
(<L2>> RVBI src, dest
Reversal of bit l1lff (supported by the device of the present invention) (Bit manipulation instruction) BTST offset, base
Test BSET offset, base bit
Set BCLRoffset, base bit
NOT offset, base bit
Transfer BSCII data, offset O
or search for 1 (within l word) (fixed length bit field instruction) BFEXT offset, width, h, ba
se, dest bit field extraction (signed) BFEXTU offset, widtb, base
, dest bit field extraction (unsigned) BFINS src, offset, widtt+
, base bit field insertion (signed) BFINSU src, offset, width,
Insert base bit field (unsigned) BFCMr' src, offset,, wid
th, base bit field comparison (signed) BFCMPU src, offset, width,
base bit field comparison (unsigned) (arbitrary length bit field instruction) BVSCII O or 1 search (arbitrary length bit field instruction)
BVMAP Bitmap operation BVCPY Bitmap transfer VPAT Pattern and bitmap operation (decimal operation instruction) * ADDDX src, desL B
CD addition* 5UBDX src, dest
BCD subtraction t I'ACKss src,
+1st Pack to BCD* UNPKss src, dest, adj
Ampank from BCD (string instruction) SMOV String copy SCM
P string comparison 5SCI+
String search 5STR same data
Repeats old input (string fill) (queue operation command) QINS entry, queue double link
Insert into queue QDEL queue, dest Delete double link queue end QSCI+ Queue search (jump command) BRA newpc Jump (r'c relative) Bcc newpc Conditional jump (pc relative) BSRnewpc Subroutine jump < pc phase
vs) JMP newpc Jump JSRnew
pc subroutine jump Ace 5tep, xre3. l1m1t,n
Loop instruction to increase ewpc index value SCB 5tep, xreg, I 1m1t,
Loop instruction ENTER1ocal to decrease newpc index f1α, reglist stack frame
system formation, subroutines for high-level languages EXITD reglist, adjsp high-level language
Subroutine return and parameter release RTS Return from subroutine NOP No operation PIB
Ensure consistency of instruction cache and pipeline (multiprocessor instructions) BSETI offset and base bit settings
(Lock the bus) BCLRI offset, base bit
Rear (lock bus) C5I comp, update, dest ratio
comparison and store (lock bus) (control space, physical space operation command) LDCsrc, tJesL Loto STCsrc, dest to control space. Store from control space LDPSB 5rc Load to PSB LDPSM src Load to PSM 5TPSB dest Store from PSB STr'SM dest Store from PSM LDP src, dest Load to physical space STr' src, desL Store from physical space (O5 related commands) 1: JRNG vector inter-ring code
* RRNG Inter-ring return T
RAPA vector software interrupt
Software interrupt based on TRAP condition
, Trap REIT Return from EIT processing (interrupt, exception handling) WAIT imask Stop, wait for interrupt LDCTX Pcbaddr Process container
Loading text5TCTX process context
Load (MMU leap destiny luck command CS chkadd r access right chi
* MOVPA 5rcaddr, dest physical address
Address transfer* LDATE src, dest, add
Load rATE* 5TATE 5rcadr, dest8TE
Store (<L2>>nePTLB TLB
Purge <<L2>>! I I'5TIJ3 p
r8a mountain (“Purge TLB at a specific address (signed decimal operation instruction) <comb 2>>ne DCADD src, des
t Signed BCD addition <comb 2>>* DCADDU src, de
st unsigned BCD addition <<L, 2>>* DC5UB src, d
est signed BCD subtraction <<L2>>* DC5UBU src, de
st unsigned BCD subtraction <<L2>>ne DCX src, des
BCD addition/subtraction including t carry <<1,2>>* DCADJ src, d
est signed BCD complement <<L2>>* DCADJU src, de
st unsigned BCD complement <<L2>>ne DCADJX src, des
t Complement of BCD including carry <<L2>>, t DCCMP 5rcl,
5rc2 Signed BCD comparison <<L2>>ne DCCMPU 5rcl, 5r
c2 unsigned BCD comparison <<L2>>* DCCMPX 5rcl, 5
Comparison of BCD including rc2 carrier, 2. [I y sen, -Nλ for the answer
21-Hawk I This document describes instruction mnemonics and addressing modes.
The specifications for the device of the present invention regarding mnemonics, etc. are shown.
It is something. Clarify the meaning of the descriptions in the document and
For the purpose of deepening understanding of the invented device
There is. A2-1-1. I am very excited about this `` Yu ゛ (
,,,> indicates a metacharacter. [A] A may or may not be present. (A) Ne Repeat A zero or more times A) +
One or more repetitions of A A::=Bll
CA is B or CA A ::= BCA is what connects B and C A2-1-
2. ■ Create a general mnemonic and a format-specific mnemonic for t'
. A generic mnemonic is a mnemonic that corresponds to each instruction,
For commands that have multiple formats such as abbreviated forms and -ship forms, etc.
There is also one generic mnemonic. On the other hand, if
- Mat-specific mnemonics distinguish between abbreviated forms and general forms.
This is a mnemonic if you want to. Decide on the characters that represent the instruction format, and use the generic
Regularly create format-specific mnemonics from nicks. When a user writes an assembler source program
usually uses a generic mnemonic. for generic mnemonics
As a general rule, the selection of the optimal format for
will do it. ■Establish uniform rules regarding data type specifiers. Data types that require description are
data type specification, operand size for the entire instruction
specification, and size specification for each operand. these
Establish uniform rules regarding ■Mnemonics are, in principle, IEEE Microρr.
ocessor assembly language
The standard is 5tan dard (P694). Ta
However, this may seem like something that doesn't fit the feeling of boat fishing.
However, it does not match the architecture of the device of the present invention.
Please use this as a reference when deciding on individual names.
It's just that. Completely IEEE based on ideas and rules
It doesn't match. ■Avoid using special symbols as much as possible. The assembler defined here uses special symbols as much as possible.
Our policy is not to use it. It's an operand
If a mathematical formula appears in the file, or if the assembler is extended,
This is to avoid conflicts with the symbols used in . Also, the characters
In order to develop even large machines with few sets, it is necessary to
It is undesirable to use too many symbols. special symbol
To avoid using it as much as possible, parentheses are used in the assembler.
only one type is used, and j; t, j
& j etc. are unused special symbols. A2-1-3. Assembler-6 One command in the assembler language for the device of the present invention is
one operation mnemonic and multiple (0, 1)
), is described by the operand mnemonic. O
There is only one character between the pecode mnemonic and the operand mnemonic.
separated by more than one white space character (space or tab)
, a comma ′, ′ is used between the operand mnemonic and the
Separated by Assembler instruction〉222 Operation〉 [<operand>(, (operand
>) Cat A2-1-4. 1 The order of operands is determined for each instruction, but the principle is as follows.
become that way. Move instruction (NOV) The first operand is the source and the second operand is the destination. That is, 1st operand; => 2nd operand This is the same as the IEEE standard. 2-operand instruction of binary operation (SUB etc.) 1st opera
The second operand is the second source, and the second operand is the first source and destination. That is, 2nd operand, op, 1st operand ==> 2nd operand This is different from the IEEE standard, but on many processors
This is a commonly used method and is easy to get used to. A2-2. Operation Mnemonic A2-2-1
．． Mnemoni...I In EEE, verbs that indicate arithmetic operations are used after the mnemonic.
This idea comes to mind, but with the device of the present invention,
Furthermore, a data type specifier is placed in front of it. Arithmetic operations
The mnemonics for things are based on IEEE.
. The command mnemonic for the device of this invention is according to the following rules.
generate. operation>::= [(data type>](arithmetic operation>((variation)
))ne(/<option))ne(:<format))
Ne [, <Size>] Example: 0V SNOV/NE, W NOV, MOV: L MOV:Q, W Data type> Specify the operation at the beginning of the instruction.
Data types that have a significant impact on the method, i.e., data types that are not orthogonal to the arithmetic operations. This data type includes strings, queues, bit fields, etc. Specify the data size (8.16, 32.64 bits for numbers, 32.64 bits for floating points, etc.) instead of here. Also, specify signed or unsigned, and address Specify the operation not here, but in (Variations).
Conform to IEEE as much as possible. The specification of the condition for a conditional jump instruction should originally be an option, but according to convention, it is included in the basic part ``arithmetic operations''. Variations> Detailed operations and attribute changes for calculations
Make the specification. (Optional) A few bits in the instruction format
Indicates the command option being expressed. Options include string instruction termination conditions and queue search conditions. Format> Format such as abbreviation, -ship shape, etc.
Specify the target. Normally, it is not necessary to write it, and if it is not written, it becomes a generic mnemonic. If you use a generic mnemonic without writing an assembler source format, the assembler automatically selects the optimal format. If the user writes (format), it becomes a format-specific mnemonic description. If the user writes (format) in the assembler source, it indicates that the format is forcibly used. Mnemonics are used when you want to distinguish instruction formats in specifications, manuals, or in disassemblers. <Size> Specifies the size of the operand. Instructions that use <Size> mainly use integers. These are instructions that handle floating point numbers and instructions that handle floating point numbers.Unlike size and data type, they are characterized by an orthogonal relationship with (arithmetic operation). A2-2-2.-1 (data The following characters are used to represent type:
There is. None Integer operations, address operations, miscellaneous instructions, etc. F Floating point S String Q Queue by double link 8 1-bit bit operation 6F Fixed length bit field operation eV Arbitrary length bit field operation ↇj≦tae! Follow the IEEE mnemonic as an operating principle. What to use
is as follows. ADD, Sue, MUL, old V, CMP, NEG, AN
D.OR. XOR, NOT, LD, ST, MOV, PUSH, PO
P.WAIT. OP Caution - How to use V, LD, and ST NOV Transfer between registers and memory
Memory to register transfer ST Register to memo
LD and ST need to be aware of the direction.
Used for instructions.・For shift-related operations, use the IEEE mnemonic because the left and right specifications are different.
Although it is not used as is, it is 5IIA that takes advantage of the principles of l EEE. SHL and ROT. - Regarding branch (conditional branch) instructions, according to IEEE, 'BV' etc. conflict with different meanings.
Because we wanted to make it easier to understand the difference between signed integer comparisons and unsigned integer comparisons, we did not follow EEE as part of the condition specification.
stomach.・JMP, JSR, RTS are balanced with branch instructions
It does not follow IEEE from the start.・Extended operation is expressed by lXj in (variation)
In particular, AD OX, 5UBX, MULX, DIVX! ;: Rai T is also 1
EEE Ni is not following. A2-2-4. Variations> allows you to specify attributes etc. for calculations.
It is something that Use characters such as: X Extended calculation examples: A[)DX, MtJLX, etc. Unsigned data calculation examples: C control space (control space) such as MOVU, ADDU, MULU, etc.
(control register): LDC, 5TCP Example of operation on physical space: LDP, 5TP 1 Example of processing performed by locking the bus: BSETI, BCLRI, CS+Gate Multiple devices
Data processing example: LDM, STM A Address calculation example: MOVA, PUSIIA, MOVPAo 10
Proceed W (unsigned, no data check) Example: ^ooox, 5ueox Or processing example to discard parameters on the stack: EXITD A2-2-5. -Ma... (Format> distinguishes the details of the instruction format.
Used when you want to Use characters such as: Q Literal abbreviation Example of a literal abbreviation of a static loop instruction for a bit field instruction: NOV:Q, #3. @abs BTST: Q, B $4, @abs ACB: Q 111, R1+15. Ioapl R register Register abbreviated form of register open operation Example of register abbreviated form of loop instruction: ANr): R, W R1, R2 MOVA: R, W @(disp:18.R2), R3 Ace: R 11, R1, R2, Ioop2 Example of abbreviated form of operation between memory registers: ADD: L, W @abs, R2 MOV: L, S/ @(disp, R2), R3 S Abbreviated form of operation between register and memory (NOV only) Example: MOV: S, W R2, @abs 1 Immediate abbreviation example: ADD:1. W $100000. @abs2 G General form of 2-operand instruction Examples of general form of loop instruction: ADD:G, @absl, @abs2 ACB:G @absl, R1, @a bs2.1oop3 E 8-bit general form of 2-operand instruction Date example: ADD: E, W #lOO, B, @abs2 8, newpc is 8 bits Example: Ace:G @absl, R1, @abs2゜1oop3:8 16 netzpc is 16 bits example: BEQ:
G error: 1632 newpc is 32
Bit example: BNE:G next:32 64 Example where newpc is 64 bits: BRA:G 1oop:64 In addition, l shown here: Q l, t e G
9 Format specifications such as , , , etc.
Differentiate the format within the mnemonic (generic mnemonic),
The purpose is to create mnemonics for each format.
Ru. In other words, it is a format specification in assembler notation.
Ru. On the other hand, the G-form used in the explanation of the instruction format
For formats such as at, E-format, etc.
should explain the format within the entire instruction.
is the purpose. Therefore, for example, the same ′:G′
Even if 'MOVA:G', it is one of the MOVA commands.
Since it is a general form, it is GA-format, 'NOV:G'
If so, it is the general form of the NOV instruction, so it is called G-format.
That's what I'm saying. υ−2jLtEEE does not consider up to 64-bit integers.
However, the data size handled is definitely different from L EEE.
become something. In the case of integers, four sizes are supported symmetrically, and the data type can also be specified on the operand side. Since the same thing is written on both the operation side and the operand side, they are separated by ' and '. Use the following characters as the size. B Byte ・8-bit integer HHa
lfword 16-bit integer W Wor
d 32-bit integer L Longwo
rd 64-bit long integer 'L2 is the inventive device 32
cannot be used. Determined separately for floating point numbers. A2-3. Open's mnemonic operand may be a general addressing mode or
for which a subset of is available (called the -acid operand)
), and those that specify special specifications according to the command (special opera
There is a For special operands,
A format will be established for each ordinance. life that takes a special operand
The orders are BRA, Bcc, BSR, Ace, SCB (ne
wpc operand) LDM, STM (reglis
t operand). (Oherand>::: (-Acid Operand> II <Special Operand>) Regarding general operands, in the device of the present invention,
The feature is that the data size can be specified for each land.
This also applies to the way general operands are written in assemblers.
It has such abilities. Also, for the operand
We also have a generic mnemonic and a format-specific mnemonic.
There is. The general operand's name is the actual operand's name.
Distinction between value (effective address) and appended mode format,
and size. (-acid operand>::: (operand value>[:(additional mode specification>][,-acid operand>:::
>] A2-3-1. °゛Shinnomo゛ Ordinary, follow
Modern processors have a limited number of addressing modes.
Since there were not many modes, each mode was considered separately.
It would have been better if they had been assigned different symbols. Also, the notation
and the actual addressing operations correspond well.
There were also cases where they were not. For example, on a certain processor
disp register relative indirection addressing mode
It is sometimes expressed as (Rn), but this is an operation.
is mem[disp+Rn], and disp
The handling of the part and the part Rn are not symmetrical. only this
There is no problem if you use it in
If you create a complex mode at the same time, a contradiction may occur.
Sometimes. Since the device of the present invention has an extra function called an additional mode,
Unless a uniform and regular addressing notation is used,
invite chaos. Therefore, in the device of the present invention, actual operation
Establish principles regarding the relationship between symbols and their notations, and
consistent addressing mode up to append mode.
I decided to write it down. Addressing basically consists of repeated addition and indirect references.
It is. Therefore, for these two operations,
All you need to do is decide on the notation method to use. The notation principles of the device of the present invention can be summarized as follows. [Description of the addressing mode of the device of the present invention Original shell@A or @(A) Memory contents to address
Reference mem[A] @(A, B, C,,,,) Add A, B, C,,
and refer to the memory contents of the address of the addition result.
It has no meaning. As with general formulas, the order of joins
It only shows that. However, @A and @(A) are completely different.
It means the same thing. Syntax explained below
Even if 1(,,)ゝ is entered in the
, )' If there is only one term, omit '(,,)'
I don't mind if you do. Traditional processors use '(,,)' for indirect references.
This is a somewhat idiomatic notation.
It has become. However, in this notation, the following
This can easily lead to misunderstandings. Example: Conventional notation Operand value Rn Rn (Rn) mem[
Rn core abs mem[abs
] or abs (abs) mem[mem[[ab
s]] or mem[abs] There may be cases where it is not possible to take appropriate measures. In the device of the present invention, indirect references are always expressed by 1@'.
This is happening for these reasons. Immediate, addressing mode for stack operations
, processing such as index scaling falls into this principle.
Therefore, we will write each notation separately while referring to the principles.
Establish. A2-3-2.・The specification of (additional mode specification>::=AIIN 'A' in the mode is when using the format of the addition mode.
Add an appendix when you want to emphasize something. Also, specifying tit means that the append mode will not be used.
Add an attachment when you want to emphasize something in particular. These specifications correspond to format-specific mnemonics.
It is something. #; H1, t; If neither A1 is written
if the addressing is in a short mode other than attach mode.
The assembler determines whether it can be realized in the code and
Use that mode if possible. This can only be achieved in additional mode.
If not, use append mode. Example: @(disp, PC):A Always PC relative addition mode
Use additional mode even if the isp is 32 bits or less @(disp, PC):N Always use PC relative indirect mode.
Error @ (disp, PC) if disp is 64 bits If disp is 32 bits
If the isp is 64 bits, use the PC relative indirect mode. If the isp is 64 bits, use the PC relative addition mode.
size and silk as indicated in the operation mnemonic.
Please take a look and specify the actual size. size specification statement
The characters are the same as those used for operations. size in the operand and the size in the operation.
In principle, the relationship between・If the size is specified during the operation
is the default size for all operands.
Effective as size. However, you cannot specify the size.
no operand, immediate operand, special
This does not apply to operands that have meaning.・If (size) is specified in the operand,
That will be the size of that operand. operation
Even if different sizes are specified in the
The specified size is given priority.・Specify (size, size) in the operand, and
If the size is not available, an error will occur. Example: MOV, W @src, @dest src, dest are all East WORD) type MOV, W @src, B, @destsrc are B(
BYTE) type, dest is W (WORD) type MOV
@src, B, @dest, Wsrc is B (BYT
E) type, dest is %l1 (WORD) type A2-3-4
．． In the following sections, we will discuss addressing with respect to general operands.
The assembler notation for each mode is shown below. With the contents such as immediate value〉, (absolute 7 dresses〉)
, you can write numbers, variable names, formulas, etc., but the syntax is
Taxes are determined separately. (Format> is the address
Write this when you want to specify the format selection for single mode.
Ku. Mainly the size of the addressing mode extension.
Used to specify. Normally you don't have to write it;
If not, the assembler automatically selects the optimal format.
Select (size). The mnemonic for each format is as follows:
In writing specifications and manuals, or disassembling
For bras, etc., we purposely use a former in the addressing section.
Used when you want to distinguish between different sets. (Format> ::= 41+ 161132
I+4 4-bit long addressing modifier 16 16-bit long addressing extension @(disp:16.Rn). ABS: Addressing extension with a length of 3232 bits such as 16@(disp:32.Rn) Addressing extension part with a length of 6464 bits such as abs:32 (ABS:64, etc.)
This is the size of the command format itself. On the other hand, the size specified by
It is the size of Pelland. For immediate mode
Other than that, the two are completely different. Example: MOV RO,%I! , @addr:16. W this life
In the command, the contents of RO are stored in the memory indicated by 'addr'.
Forward. Absolute addressing is used. ':16' represents 'add r' in 16 bits
to show that Therefore, 'addr' ranges from $ffff8000 to $0OO0
7fff roars. On the other hand, ', W' are calculated using %10RD (32 bits).
Show what you do. In other words, this command transfers 4 bytes of data. (The register number is the general-purpose register mnemonic.
It is (Register number>::=ROII RI II R2II R3II
R4IIR5II R6II R7II R8II R
9II RIOllR11It R12II R13I
I R14II R15IIPIISP FP and R14 have exactly the same meaning, and SP and R15 have exactly the same meaning.
Ru. A2-3-4-1. Cashier Operand = Rn (Operand value>::= Register number> Example: l A2-3-4-2. Cashier Operand = mem[Rn] (Operand value>::= e register number〉 Example: @R2 A2-3-4-3.Register -statement・1゜operand=
mem[disp16 + Rnlmem[disp
32 + Rn] (operand value>::= @(<displacement>[:(format)>]
, <Register number>) (Format> ::= 161+ 32 example: @(disp:16.R5) A2-3-4-4.1-1 REMIE knee operand
= imm-data <operand value>::= #> literal value> (operand value>::= #> immediate value> Specifies that the literal instruction format is used.
If you want to indicate it, indicate it in the operation mnemonic.
. For immediate, the size of the extension is
Since it is determined as the size of the
is〉 has the same meaning. As an assembler,
ーMat〉 or (size〉) refers to its size.
can be determined. Note that in the immediate operand, the signal is sent to the operand side.
There is no size specification, and there is freedom in size based on the command function.
If there is, the smallest size will be automatically selected.
To be. Example: ADD:Q, W 111. RO Use literal format (2 bytes) ADD:1. Enemy $1. RO Uses immediate format (6 bytes) Source operand Ill is expressed in 32 bits ADD: L, W #1. RO Use abbreviated format (6 bytes) Specify 32-bit immediate as source operand ADD: G, W #1. B, RO Uses general format (6 bytes) Specifies 8-bit immediate as the source operand. Expresses 111 using the lower 8 bits of the 16-bit field. '1' is sign extended to 32 bits
be done. ADD: E, W old, RO Uses general 8-bit immediate format (4 bytes)) '1' signifies 32 bits
Expanded. ADD: G, enemy 1tl, RO #1 has no size specification, and since it is a 2G format, there is still a degree of freedom in size.
. Therefore, the smallest size is automatically selected, ADD:G #1. B, RO, W (6 Hyde instructions) and
become equivalent. ADD:G #1. Support, RO0%l1 (8-byte instruction)
It's not about becoming. ADD:G,%Il#1:16. RO This depends on the format, not the size.
This is an example of selecting the command: ADD: G, W #1. It becomes equivalent to ll, RO. Generic mnemonic simply ADD, enemy #1. When written as RO, ADD with the shortest code: Q, W #1. RO is selected. Also, depending on the instruction, the size is fixed to one.
Not really, but practically only in one size
There are things that are used. For such things, especially the operand side
Default set by command unless marked with "Z".
Apply default size. This means that the mnemonic for (operation) is
This is an exception to the rule that it costs Rand. [Example] The access size of the bit manipulation instruction (BB specification) is 8b.
it(,B) is the default, H2, is <<L2>>,
, L is a comb×>> Fixed-length bit field manipulation instruction register size (×
(specified) is 32 bit (, W) Cub fault 1, H,, B cannot be used 1. Shihakukushi × >> BTST,
W RO, @addr = BTST RO, W,
li! addr, B A2-3-4-5. %I knee operand == mem[abs16]mem[abs
32 comem[abs64] (operand value>::= @absolute address>[:<format)] (former
> ::= 16 II 321164 Example: @abs:32 A2-3-4-6. PC, 1 operand = mem[disp16 + PCIme
m[disp32 + PC] (operand value>::= @([(displacement>[:<format>
]], PC) (Format> ::= 161+ 32 Example: @(disp, PC) A2-3-4-7. Stacked operand = mem[sP++] (Operand value>22 = @SP+ Example: @SP+ A2-3-4-8. -- ---9 Operand: mem[-5P] Operand value>::= @-5P Example: @-5P A2-3-4-9.FP Statement - Operand = mem[disp4 + FP] (operation
Land value>::: @([<Displacement>[:<Format>
], (register number>) (format>::=4 register number> ::= FP II R14 example: @(disp4:4.FP) In this addressing mode, the specified
Multiply the specified disp value by 4 to calculate the actual displacement value.
However, the value used in assembler notation is multiplied by 4.
This is after. If no format is specified, the assembler will
Since the notation is the same as the mode of register relative indirection,
The best mode is selected by the assembler. In other words
, for the operand written @(d+sp,Rn), R
n is R14 or FP, and disρ is −32 to
When 31 is a multiple of 4, FP relative indirect mode is selected.
otherwise, register relative indirection mode is selected.
The choice is made. A2-needleman "Mei u1 pair" J- operand = mem[disp4 + SF'] (o
Pelland value>222@([<displacement>[:(format>
Format>::=4 (Register number> ::= SP II R15 example: @(disp4:4.SP) In this addressing mode, the specified bit pattern is
Multiply the specified disp value by 4 to calculate the actual displacement value.
However, the value used in assembler notation is multiplied by 4.
This is after. υ≦L month'
A file that encodes the format and bit pattern.
Provide a mnemonic for each format. [Indirect reference is expressed by e or @(,,,) for a generic mnemonic, (,
, , , , , , , ) represents addition of addresses.
The principle remains the same.・The order of notation is basically base mode or previous additional mode tmp value ==> Displacement ==) Index. This will change the flow of effective address calculation.
It becomes a simple shape from left to right, and is necessary for the append mode in the previous row.
The necessary information is placed first, and the information necessary for the additional mode in the later stage.
gather at the back. That is, the generic mnemonic notation
The order of is the same as the order of machine bit patterns in append mode.
It will be the same. Therefore, format-specific mnemonics and
It has good correspondence with the actual machine language append mode, and
becomes simpler and easier to understand. [Co-format regarding mnemonics by format]
By introducing the three characters ggi for designation.
, there is a notation that corresponds one-to-one with the bit pattern of machine language.
make it possible to do so. 2B Achieve that part of the processing using base mode.
Indicates that: A The processing up to that part is performed in -stage addition mode.
:N The processing of that part is executed in the next stage's additional mode (':A
Note that "the processing of that part" means that if a format specification character is attached to a displacement or register, the addition process of that value is performed by the format specification. If the character is in the closing bracket 9)', it is an indirect reference.
means processing. Also, ``:8'' means ``processing up to that part''.
Processing of the part to :8 and adding ′:N° on the left side.
part (I:NI in leap with previous ′:A9 or ′=B′)
Indicates that the processing for the parts marked with ) will be performed at the same time.・If all formats are specified, input to ′:8.
The number becomes the number of stages in addition mode. Also, usually one
:8 corresponds to one level of indirect reference. However, multiple
When adding index registers (even without indirect references)
′: A′ is required), when double indirection is performed in the last stage (
Even if there are two levels of indirect reference, only one ':8' is an exception.
Ru.・If the format is not indicated, the generic mnemonic
An additional mode that can realize the processing described as
Dynamically selected. In addition, formats that cannot be realized in the actual append mode
If you specify a format-specific mnemonic, an error will occur.
becomes. Additionally, the format specification mnemonic
- If you remove the mat designation character, the generic mnemonic character remains as it is.
It becomes dark. For these points, refer to the mnemonic for each format.
The same general principle applies. [If there is no addition of multiple addresses regarding the general format, use the brackets @(,,,)
It is not necessary to write, for example, it can be realized in append mode.
The triple indirect reference @(@(@(R1))) is @@@
It may also be written as R1. This is an address other than attach mode.
This principle also applies to syntax, which is a type of syntax.
I grow up 100 times.・The index scale value is ':B' in IEEE.
I am using size specification characters such as t=wl, but in the future
Is it possible to consider adding a larger value to the scale value?
So, here, write the rescale value directly as usual.
do. Also, the characters that specify scaling are I EEEE
Use ``*'' instead of ``sote''. This means that ′:1
This is because it is used separately for the purpose of format specification.
. Examples: @(offset, PC) mem[offset + PC] Generic mnemonic. If offset is 32 bits, P
It is realized in the C relative indirect mode, and if it does not fit in 32 bits, it is realized in the additional mode. @(offset, PC): N mem [offset + PC] Always implement in PC relative indirect mode, not in addition mode. In the device 64 of the present invention, offset does not fall within 32 bits.
If not, an error will occur. @(offset[:NI, PC[:Nl):Amem
[offset + PC] Must be implemented in additional mode. Since there is no part corresponding to the base mode specification, absolute addition mode + addition mode EI=IO, disp=offset,
1ndex=PC, 5cale=1. @(PC[::B], offset[:NI)[:Al
mem[offset + PC] Always PC relative addition mode + addition mode EI=10. disp=offset
, 1ndex=0. Realized with 5cale=ne. @(@(@(R3[:B], basel[:Nl, R4
Ne4[:Nl)[:A], base2[:Nl, R5[
ne1][:Nl)[:Nl)[:A]mem[mem[
mem[R3+ basel + R4ne4]+bas
e2 + R5] R3 relative addition mode + addition mode EI=01. disp=basel
, 1ndex=R4, 5cale=4+additional mode
EI=11. disp=base2, 1ndex=
R5,5cale=1 @(R3[:B], basel[:Nl, R4
Ne4[:A], R5*2[:Nl)C:A] mem[R3+ basel ÷ R4ne4 +
R5ne2] R3 relative addition mode + addition mode EI=OO, disp=basel,
1ndex=R4, 5cale=4+additional mode
El=10. disp=base2, 1ndex=R
5,5cale=2 @(R3[:B], basel:A, R4ne4
:A):Amem[R3+basel+R
4] R3 relative addition mode + addition mode EI=OO, disp=basel,
1ndex=0.5cale=ne+additional mode EI=OO, disp=o, 1nd
ex=R4,5cale=4 +additional mode EI=10. disp=o, 1n
dex=0.5cale=* This is an example in which the format is specified and the three-stage addition mode is intentionally set, although this can be achieved in the -stage addition mode. The syntax of the append mode is summarized below. just
shorthand notation to omit parentheses, and symbols to separate parts.
Ma2. The syntax for ′ is not included here.
do not have. Operand = mem[mem[,,,] + dis
p + Rn5calel + Rm5cale2
．． ,,](general operand>::: (operand value>[:Nl[,<size>]11(additional
Mode operand value> [, (size>] (additional mode operand value>::= @((additional mode intermediate value>, [<disp value> [2N]
], [(index value>[:N13)[:A]El=1
Corresponds to 0 +1 8(@(<additional mode intermediate value>, [<disp
value〉[:N13. [(Index value) [:N13) [:Nl) [:A] Corresponds to El=11 This represents the final stage of the addition mode. (Additional mode intermediate value>::= (Additional mode intermediate value>, <disp value>C:AlI3(
Additional mode intermediate value>, [<disp value>[:N13, <
Index value>[:A] Corresponds to El=OO II @(<additional mode intermediate value>, (<disp value
) [2N]], [(index value - C:N]]) [:A
] Corresponds to EI=01 This represents an intermediate addition mode. (Additional mode intermediate value>222[0[:B11 Corresponds to absolute addition mode 11 (
Register number > [:B] Register relative addition mode
Compatible with II PC[:B] with PC relative
Supports addition mode This is base mode (register relative addition mode, PC phase
(distinction between paired addition mode and absolute addition mode). <disp value>::= (displacement>[:<format>] Compatible with D, dddd field (format>::= 41+ 161+ 32
1+64 index value> ::= (register number> [, (size)] ['N' scale
value>] II PC[,<size)]['l'<scale
Value〉] Compatible with S, M, Rx, XX fields (Size〉::=11㎡Scale value〉::=l 112114118'ne
ゝ indicates that the asterisk ``zero'' is used as a character.
. It has no meta meaning of "repetition". (Index size) is the size of the index register.
It is a valid data size. 1. With the device 64 of the present invention. Suss
is specified, the lower 32 bits of the register are 64
Sign extended to bits. (If index <scale> is omitted, l
is assumed. A2-3-6. Operates Specified using a method other than the general addressing mode.
For perandos (special operands), use the following system.
It is assumed to be tax. Note that commas ′, ′ separate each part.
The actual syntax is not included here. re I ist LDM STM ENTEREX
ITD total Δ(register number>or register number>−
Arrange the register numbers separated by ′, ′, and write ’(,,,
)' (special operand) 222 ((<consecutive register number>, ) ne) consecutive register number>22 = (register number) Specifies the register with that number 11 (register number> - (register number between
Example of specifying all registers: ENTER, -$110. (') LDM, enemy@block, (SP) STM, W (R1, R3, R9-R13, FP), @
-5Pnew c BRA Bcc BSRACB
The SCB+3Δ addressing method is in PC relative mode.
It is only. As an operand, simply write the jump destination label.
Ku. In this case, the assembler will
The difference between the address and the jump destination address is the newpc bit.
The label is set as a target pattern and the label is
Allows you to jump to locations. (Special operand>::= (destination label>) Example: BEQ nextaddr nextaddr
Jump to ACB, B #l, R1, @11m1t,
Jump BRA, acc, BSR, ACB, SCB instructions appear in Ioopaddrtoopaddr
Frequent, special addressing (PC relative only)
It's better to be able to write the label of the destination as it is idiomatically.
For some reasons, just write the destination label.
automatically (destination label) address and these instructions
The difference between the address where the
It has become established. All operand notation
Among them, symbol names other than registers start with ``#'' as well.
The only place that appears without @' is the destination label.
It will be done. Therefore, for example, BRA 1abel has the same meaning as JMP @(label-$, PC).
will represent. Note that ``$'' includes this symbol.
Indicates the start address of the instruction (JMP instruction in this case)
. special operand>::= +t #<correction value> Example where the value is set as is: BW to LINP @src, @dest, #)l'23
302330vector TRAPAa”
Add 'II' to the beginning. Special operand>::= 11# (vector>) Example where the value is set as is: TRAPA #l Literal specifications such as iShorihiki/Bit field instructions are in the abbreviated form.
It is expressed as # (literal value) in the same way as the literal specification.φCHK, INDEX, AcB, SCB bit fee
Register specifications for commands, commands, etc. are similar to general addressing.
As in the register direct mode in programming, it is expressed as a register number. A2-4. -Ma・' 1 Nimonipa, Nemo'
"genericmnemonic" and "format specific mnemonic" are
This is one of the features of the device assembler of the present invention. traditional pro
There is no similar way of thinking about some commands in Sessa.
(68020 MOV and MOVQ etc.), but the present invention
The device fully codifies both mnemonics and
The same idea should be applied not only to the description of the operands but also to the description of the operands.
What makes it special is what it incorporates. Between format-specific mnemonics and generic mnemonics,
The relationship is as follows.・Various restrictions arising from implementation and format
A generic mnemonic is one that does not impose the terms on the user.
As long as you write generic mnemonics, the assembler will write the optimal code.
choose. Instructions with the same function and flags set in the same way
should be combined into one generic mnemonic whenever possible. The mnemonic for each φ format is the machine language bit pattern.
There is a one-to-one correspondence with the Even if the format mnemonic changes, it remains the object.
It only affects the object size and number of execution cycles;
The instruction functions are exactly the same, including flag changes.
. In this respect format specifiers and size specifiers are fundamentally
different. For size specifiers, if the operation size changes
The command function from the user's perspective also changes. conditional jump instruction
Then use a format command like BRA 1abel:32.
Even though a constant is used, in the case of an addition instruction, ADD s
Use size specifiers like rc, B, dest, W.
This is why they are there. -Usually users use the "generic term". "For
"By mat" is the explanation of the format in the specifications, the reverse address.
It is only used for special purposes such as assembly. therefore
, although it may seem a bit redundant in some cases,
There is no particular problem considering the purpose of use. Mainly used by users
It is only a generic mnemonic. Also,"
``generic term'' and ``by format'' are just extreme notations.
, there is also an intermediate notation that specifies only part of the format.
do. For example, add @(offset, PC) to the mode
I want to write it as
If it is acceptable, write @(offset, PC):A. Why does it say "by format"?
Just specify only the necessary parts of the format.
In reality, the description is usually not that long.
be.・ To convert from “by format” to “generic”, use ′:
It can be done mechanically by taking X'.
. The reverse conversion is also applicable to the extent that the format allows.
All you have to do is add 9:X9. opera
The order of the commands does not change. As a mnemonic for each format, you can change the symbol or change the order.
It is possible to think of a way to change the order, but then the generic term
The relationship with the mnemonic will no longer be smooth, so
I have not taken such a method. (There are various cases)
It becomes necessary, and on the contrary, it becomes difficult to understand. Good scalability
do not have. ) Also, like the above @(offset, PC):A,
- If you want to specify only the format of the
It would be better to be able to uniformly distinguish between "by mat" and "generic name"
desirable.・In the end, the interface that receives information from users is
It is a mnemonic, and is an input language that is subject to constraints from machine language.
The interface is a format-specific mnemonic. of both
Adjustments are made using the format specification character ':X9' and
and assembler.・Use format-specific mnemonics and generic mnemonics together
The disadvantage of doing this is that it complicates the assembler. However, it is better for users to worry about formatting.
The assembler can handle anything that can be handled by the assembler.
We believe that it is better to use
It is inevitable that things will become complicated.・Instructions with different machines and flag changes may be
Even if the mnemonic pattern is similar, it becomes a different generic mnemonic.
Ru. For the above reasons, "by format" is often
Even if the description is long, you can use the mnemonic for each format.
``Which format to use''
I think it would be better to make it clear. centre
All parts representing the format are unified to ':X'.
This is why. Note that the parts marked '[,,,]' in the syntax can be omitted.
It is possible to omit it, but whether or not it is omitted is unified throughout.
There's no need to be there. For example, omit certain '[,,,]'
, you may leave another '[,,,]'. A2-5. The assembler notation described so far is a machine language bit pattern.
Notation for giving mnemonics to turns as commands
It is the core part of assembly language. present invention
The device has the <<LQ>> specifications up to this point. However, if we look at assembler as a language,
In addition to mnemonics, it is necessary to specify the following items.
Ru. Regarding these items, please refer to the architecture of the device of the present invention.
IEEE as much as possible without conflicting with IEEE.
Standardize to match.・How to use uppercase and lowercase letters ・How many characters can a symbol have? ・Whether an expression can be written in a symbol and what is its syntax?
What should be the format of the label? (Insert ′:′ after the label.)
・What are the notation methods for binary numbers, octal numbers, IO base numbers, and hexadecimal numbers?
- How to write comments - String description format - Expression format for special characters (such as line feed character tynt) - Detailed syntax and characters that can be used - Assembler pseudonyms
Similar instruction φ macro Among these, binary, octal, IO, and hexadecimal notation
Regarding the method, the IEEE has the following format: C
There is. B'~ Binary number Example: B'0OO10010=
H'12 Q'~ Octal number Example=Q'22=■'12 0'~ lO base number Example: D'1B=H
'12 H'~ Hexadecimal number In this specification, to represent hexadecimal numbers, tl H11~
゛2, using "B'"~'' to represent a binary number
There is. υj'' U bold letter AzuCmuζ2 embryonic l It is not particularly determined in EEE. In the device of the present invention,
Uppercase and lowercase letters are equivalent for mnemonics and reserved groups.
to be treated. In other words, the parts that are capitalized in this document
You may use lowercase letters for . However, the user
General variables defined by are case-sensitive.
The other one is the standard. Displacement, (literal value), (imide
Items (collectively referred to as
Symbol values) have four basic values, including constants and labels.
It is assumed that you can write arithmetic expressions. In the expression, '(,,,)' is used to change the priority.
can be used. However, undefined values (such as external names and
For expressions that include labels (such as labels that are defined later),
The form of the arithmetic expression is restricted so that the location can be
I don't mind. Furthermore, in the expression, the address of the instruction currently being focused on is
'$2 can be used as the indicated value. The notation for PC relative indirect mode is @(d i sp * P C), and the value of disp is set to direct displacement.
determined. However, PC-relative and relocatable programs
When writing a program, write the address of the operand itself.
Operand address instead of setting it as disp
The difference between the address and the address where this instruction is located is called the d isp value.
You need to set it. Use ’$2 for this purpose
be able to. That is, (operand − $) is di
It may be set as an sp value. ``Loram 1 Address〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉〉
#1. @(foe-$:16,PC) )1'0104 NOV, B #2. @(
8:16. PCH'010B )1'010C H'0180 foe: ,,. MOV at address H'0100, second operan of B instruction
In de@(loc-$:16.PC), the actual dis
The value set in the bit pattern of p is H'0180-H
'0100=H'0080. This command causes
1 is set in foe of address lI'0180. one
On the other hand, in the gate OV and B instructions of H'0104, 7, L, and
11'0104+8=l+'010C1,:2 is set
be done.・ Mo゛9＄9 It was snowing in Vane＠（＠（
[:0:B,] 1abe11-$[:N], PC[:
N]) [:A]. Iabe12-$[::N], PC[:N]) [:A]
This is mem[mem[displ + PC]÷disp2
+ PC]. However, displ is the pointing address of 1abel 1 and the current address.
The difference disp2 is the address pointed to by 1abe12 and the current address.
The difference from the above and the extension part of the addition mode is absolute addition mode + addition mode El=01. disp=displ,
1ndex=PC, 5cale=1+additional mode E
l=10. disp=disp2.1ndex=PC
, 5cale=1. This mode allows you to program relocatable tables (such as jump tables for case statements).
Can be used when placed in the RAM area. The first level PC relative indirection mem [displ + PC] makes the table reference for the case statement relocatable.
It is used to In addition, the second stage PC relative indirect mes+[a+em[,,,] + disp2 +
PC] is used to relocatably determine the jump destination address. −・−゛・ Considering the use of the device of the present invention in applications such as embedding in memory
Then, the instruction set is the device of the present invention, but the memory
A barge that does not have management hardware
You can also consider tipping. Therefore, the memory management mechanism 2 of the device of the present invention must
No need for ports <LQ>> Standard specification instead of <LQ> specification
It is designed to only display the following information.
. Below, the present invention device standard as <<LA>> specification
Describe memory management methods. A3-1. Memory... Formula〇゛1 and <<LIRA>
Specifications The device of the present invention performs address conversion by hardware.
The standard specifications for the memory management method (hereinafter referred to as ``U'') are <
<LA>> Prepared as a specification. However, the present invention
When installing lTR0N or μBTRON in equipment
In many cases, mon-U is not necessary, and in some cases, mon-U is also used.
Even if the application is for
Instructions are executed without address translation until the line environment is set.
need to be executed. Therefore, the device of the present invention uses an MMU mechanism.
Indicates whether address translation is being performed.
Set a field in 18w and change this field.
By specifying the presence or absence of address translation and memory protection,
It is possible to set the This field is set to AT (Address Translator).
(Lion) field, AT is pss.
It is located in b116 to bit7. AT18
By setting it in w, the context by toc:x etc.
switch, start BIT processing, and RCIT command.
The address is also returned from the taxa processing handler.
It is possible to switch between the presence and absence of space conversion. The meaning of the AT field is shown below. AT Meaning 00 Address translation, no memory protection Ol Book
Inventive device 4! Standard address translation and memory protection
〉 10 Clauses using only addresses without address conversion
l [Memory protection <<LIRA> (Discrimination of memory area by MSB of address, 2 rings
) 11 reserved Of these, the standard memory management of the <<l8>> specification is implemented.
AT・00.01 can be used with the device of the present invention, <<1
1117>) Corrections 00 and 10 can be used with the device of the present invention.
becomes. <<IIR>> If the specification is AT, 10, there is no MMU.
Therefore, memory protection cannot be performed for each page, but <<LA>
> 4 rings are degenerated and only ring 0 and ring 3 are effective.
and performs simple memory protection using addresses. a
The area of MSB = 1 of the dress (〈＜LΔ〉〉dius■υ
is accessible from ring O, access is prohibited from ring 3
Normally, the OS is placed here (. On the other hand, the MSB/0 area of the address (<<LA>>
) can be accessed from both ring O and ring 3.
This is the possible area, and the user program is usually placed here.
<, Since there is no MMU, memory protection between user programs
However, it is possible to protect the OS from user programs.
is possible. For AT・00 (no address conversion), memory access
No ring protection checks are performed for accesses. Therefore, page out exception (POE), address change
An exchange exception (ATRE) does not occur. However, even in the case of revision 00, privileged instructions are not checked.
It will be done. Regarding the operation when AT=OO, <<Ll>> and <<
It is desirable that LIR >> be exactly the same, but,
In commands such as LDATIE, if <<Ll>> then MM
While it is a practical command in the sense of setting up the U environment,
<<1. IR>> has no meaning at all, and
If an instruction such as PTLB is also <<Ll>> AT/00, then
It has some meaning, but in <<LIR>>, TLfl
Since there is no such thing, it has no meaning at all, therefore,
<<Ll)1>> In the specifications, these MMU-related instructions
We decide not to implement it. <<LIR>>
If an attempt is made to execute an instruction that has been
A reserved instruction exception (1?rE) will occur. A3-2. This invention device is <
It is a <LIRA> specification chip. The meaning of the AT field of the device of the present invention is shown in Fig. 292.
. 1 and IO to access the I10th hole of A3-301 mouth
MASK, for I10 space indicated by l0ADDR
Instruction fetch and memory indirect addressing mode
An operand fetch caused by this will result in an address translation exception. Memory indirect addressing is performed when accessing the I10 space.
In the case of
, an access operation is performed in the case of an instruction fetch. Therefore, the external 170 device is of bus access type.
Check the (BAT) signal and do not respond if it is an instruction fetch.
It is necessary to do so. The I10 space is usually located in the ring O area, so the ring
Access from 3 will result in a ring protection violation being detected.
I think so. Ring protection violations can be detected quickly
Therefore, no memory access is performed. Also, with I10 space! A that straddles a space other than 10
If an access is made, an address translation exception will occur, but
In that case, re-execution behavior cannot be guaranteed. A3-4. Memo!・In order to achieve the following objectives, the device of the present invention has the following objectives:
Introducing a hardware memory management unit (MMU)
ing.・Implemented with support for instruction re-execution and virtual memory
It provides a logical space larger than the existing physical memory.
provide・With the introduction of the multiple logical space function, the context
maintain independence between programs and processes) and create programs.
Make it easier to access.・With the introduction of the ring protection function, O3 and shared data are protected.
Memory protection between user programs and user data
Let's do it. In order to provide the above functions, the device of the present invention has the following features:
Address using paging method for each memory access
Perform the conversion. Address before address conversion (logical address
The space created by LogicaI 5pace
LS and spare, address after address conversion (physical address)
Physical Space refers to the space created by
It's called PS by taste. In the case of paging, to speed up memory access,
First, TLB (Translation Lookas)
ide Buffer)
It is common to introduce a storage buffer. However, T
LB is an implementation to speed up memory access.
MMC specifications of the device of the present invention
As such, there are no regulations regarding TLB. Also in this document
, TLn are not explained. Also, purge TLB due to context switching.
To reduce HA fiii empty as <<L2>>
It is possible to introduce the functions of 8 & Besshi (LSID)
. The LSID is uniquely given to each context.
The logical address of the TLB, including the LSID.
If you do a comparison, you can switch contexts.
There is no need to purge all TLBs even when However, the functionality of LSID also depends on the implementation.
Since the MMU specifications of the device of the present invention are strong, LS
0 that does not specify detailed ID functions or number of bits
In the specifications of the invented device, the address of the control register indicating the LSID is
Address assignment and TLB when LSID is implemented
Only explanations regarding cache consistency are provided.
There is. ^3-4-1. Paging The address conversion of the device of the present invention is based on paging.
There is. The page size is 4KB and is unified throughout the device of the present invention.
It has been done. This changes the TLB structure etc.
It can be limited to a certain extent and has a built-in memory management mechanism.
Opportunities get bigger. Also, if you fix the basic parameters, you can tune to them.
Performance improvement can be expected by During address conversion, the logical address of the device 32 of the present invention is
It is divided as shown in Fig. 293, thereby creating a two-stage
Perform cleaning. A 32-bit logical address creates 4GB of logical space.
. 4GB by R bit (MSB of logical address)
The logical space of 5hared Region is 2GB.
(UR) and SharedRegion (SR)
Divided into. Each region has a SX feel.
It is divided into 5 sections of 4 MB each depending on the code. Furthermore, each 5ection has a PX field
It is divided into pages of RKB each. Therefore, the page in the upper stage of the two-stage paging
The table uses Sx as an index, and the lower page
This will extract the base address of the table. this
is called 5ection Table (ST), and
Let's call one table entry STE.
Also, the lower page page of the two-stage paging
The base of the physical page is indexed by PX.
It will bring out the address. This is Page T
able (PT), and its one table entry
The entry is called PTE. For one STE change
One more 5ection is due to one PTH change.
One Paze will receive jF+G Cゝ
. ATE (Address) is a generic name for PTE and STH.
s Translation Table Entry) and
Use the name. The base address of ST is the base address of UATBSSH in case of OR.
The case is indicated by a control register named 5ATB. By changing UATB or 5ATB, one Regi
0 or more relationships that are affected by on (UR or SR)
A summary is shown in Figure 294. A3-4-2. ” In the device of the present invention, the logical address ff5B allows the common
Common space (S,hared Region) and individual space (S,hared Region)
UnsharedReg 1on) is distinguished. For each Region, set the address translation table.
There are bull base registers UATB and 5ATB.
, among these, only 0ATH is switched for each context
This makes it possible to realize multiple logical spaces.
Ru. That is, OR(logical at L, 7.H'0000000
0-H'7ffffffff) separately for each context.
physical space (physical memory) is allocated whereas
, SR (logical address 11°80000000~II'
ffffffffff) is common between context 7.1-
Physical space (physical memory) is allocated a 5har
ed Region is mainly used for interrupt processing handlers and O8
The Unshared Region is mainly used by users.
The program uses it, but it is not user data.
Also, use SR for things that are shared between tasks and processes.
In some cases, even the data managed by O3 may include tasks and programs.
URLs may be used for items that need to be held for each access.
Ru. By using the multiple logical space function, the same logical address
You can run multiple programs at the same time from
performs all object code relocations at runtime.
There is no need to Also, the URL of other tasks and processes
cannot be directly referenced, so there are no messages between programs.
It also helps protect harpoons. Note that [distinction between iR and SR and memory ring protection described later]
There is no direct relationship with the function of In other words, riB3?
You may not be able to refer to the SR while the PC is in the UR.
Restrictions such as not being able to refer to UR and SR themselves
Not included in functionality. Accessing memory like this
If you want to limit it, you can use the memory ring protection function.
Set appropriate protection codes for STE and PTE using
must be kept. [Configuration of multiple logical space] In Figure 295, Unshared Region/5hared R
egion switching is done by logical address MSH.
It is done.・In the Unshared Region, the UATB record is
The address is translated by the register.・In 5hared Region, 5ATB register
The address is translated by・Only the tlATB register is switched for each context
Therefore, in Unshared Region, each
contexts can have separate logical spaces. Since the address translation is two-stage paging,
If the two STEs in the context are the same Page T
A shared section in uR by pointing to
You can also set up a shared page. Note that programs that straddle the boundary between OR and SR,
Think about the data as follows.・When expanding to 64 bits, the currently consecutive OR and SR
Since the boundary becomes discontinuous, from H'7ffffffff
The program that extends first is used when expanding to 64 bits.
become unable. This is the bag rf1.32 of the present invention, +1
The next address of '7ffffffff is 11' 000
Even if you think of it as 00000)! ' 80000000
It's the same no matter what. Therefore, [notes that span both iR and SR]
re-access and consecutive instructions in IIR-5R.
You shouldn't do it.・However, whether it straddles UR and SR or is assimilated
Performing the check every time is a burden on the implementation.
Because of the large size, there are accesses that span both UR and SR.
Even if it is, it will not be considered a BIT. In this case, the address is linear regardless of the region.
Taking advantage of the idea that it is an address, 11゛7ff
After fffff)l'80000000. ! I°f
The next address after ffffffff is I+' 00000000.
The dress shall be accessed. However, as mentioned in the previous section,
As mentioned above, you can write a program that uses this specification.
It shouldn't be. LDC command for PSW, 0ATH, 5ATB,
LDATE. When switching the logical space using the LDCTX instruction, the current
It also affects the address conversion of the program area in the line.
can give. Therefore, depending on how you use it,
There are also cases where the robot flies to a completely different location based on the command.
arise. This must be handled by the program.
No, specifically, when changing the AT bit, V
=When using RGI area or executing LDCTX
Use 5R (Shared Region)
It turns out. A3-4-3. Ring protection: The memory protection method of the device of the present invention has four levels of ring protection.
It is. Protection information is a logical address or OR. It can be specified for each page regardless of SR distinction.
Ru. In ring protection, the current ring number (
RNG) and the STE of the logical address to be accessed. PT [! C, depending on the relationship with the protection code included in
Determines whether access is possible. With a small RNG value
The closer the ring is, the stronger the access
RNG/3 has the weakest access rights.
. If rngl<rnH2, RNG=rng2
Pages that can be accessed are always RNG=rnfXl
You will be able to access it. 1. One control related to the μL register MMU will be explained.・PS- See separate section. Related to U are the fields RNG and ^T.
.・LSID See separate section. The presence or absence of this register and the number of valid bits depend on the implementation.
Depends on the l UATB (Unshared region)
Address Translation table
Ba5e) Shown in FIG. 296. ' 5ATB (Shared region Ad
Dress Translation Table B
a5e) Shown in Figure 297. STB: 5ection Table Ba5e
Reserved in the physical base address 101 of the Section Table The manual for users instructs them to write "0". However, even if °1' is written, it will be ignored. When reading, the value is undefined. D: 5 when the size of Direction Section Table is small
Ection Table Direction DJ 5ectio
n Table's lower address side is valid row I 5ection Table's upper address
The valid side and LL fields limit the range of valid logical addresses, and at the same time limit the size of the 5ection table, for small-scale applications.
It is used to reduce the size. LL: Length Section Table size LL・00 1/2 size 512 entries 2K B
Blue 2GB Region LL-011/4 size
256 entries IK B table IG B Re
gion+, t,, to 1/16 size 64 en
Tori 256B table 256MB RegionLL
・11 1/64 size 16 entries 64B table
64MB RegionPI: Page I
n PI*O5ection Table to physical address
not exist. In this case, the STB has no hardware meaning and can be used freely in O8. However, the Pl, O, and LL fields are valid. D and LL are used to distinguish between an address translation exception (ATRE) unused area reference error and a page out exception (POE), and the former is given priority in exception detection. In other words, if you try to perform address translation using this register when PT is 0, D. If an unused area reference error is detected by the LL field, an address translation exception (ATRE) is generated; otherwise, a page out exception (POE) is generated. PI=I 5ection Table is physical address
It exists on the reply. P! If it is -1, it is possible to perform address translation using this register. However, if an unused area reference error is detected in the D or LL fields, an address translation exception (ATRE) will occur. 5ATB, P in UATB! The bit is exactly Pa
ge In de na (5ection Table In
The pr bit in STE, which will be described later, represents the meaning of
is Page Table I instead of Page In
It expresses the meaning of n, but there is no need to distinguish it.
Therefore, both use the same name “PI”.
use "Page" in the broad sense includes "page table" and "
'sectiontable', i.e. the section table for evictions to disk.
It will include all the units, so the page table
"Page Fault Exception" also occurs when a table or section table is absent.
The name of the exception is used as is. 5ection Table+ Page Table
Although it is possible to page out itself,
For tables that have been
Addresses (STB, PTB) represent physical addresses.
To be. In other words, the page table is a physical space, not a logical space.
It can be thought that it is placed in Also, 5ect
ion Table and Page Table are changed to 4.
Allows page-out of ST and PT if the size is not large enough.
In units of 64B, 256B, IKB, and 2KB.
There may also be cases where a page is absent. In other words, UATB,
5ATB, P at STE! bit is not necessarily 4
Please note that this does not necessarily mean page absence in units.
There is a need. Section table and page table sizes are now variable
However, the table is at its minimum size (1/64).
If not, the valid bits of STB and Sx overlap.
For example, tlATB, 5ATBteD-0, LL
−00, the actual STE is calculated as follows.
It is necessary to calculate the effective address. X is a valid bit (0/l) - is an invalid bit (0) ゛〉〉゜゛〉〉〉゛ represents a shift Here, the overlapping bits of IXI, that is, ST
[The handling of the bits 2'6 to 2'11 of l is a problem. The following ideas can be considered. ■ The bits 2'6 to 2°11 of STB must be lOo.
shall not be allowed. On implementation, STB
2'7~2°31 and SX shifted 20 bits to the right.
Calculate the STB address by concatenating the
can do. (Forced alignment) ■ Bits 2"6 to 2"11 of STB do not need to be 0.
However, if the effective address of STH is in the range up to 2"11,
up around. In implementation, there is no overlap.
Addition of only 5 bits is performed, and the carry generated by the addition is
The gap will be ignored. (Wraparound)■S
Bits 2'6 to 2°11 of TB do not have to be 0.
, higher than 2゛6 for 5ection Table
does not force any alignment. on implementation
First, 5 bits with overlap are added, and the carry is
If a carry occurs, the carry is propagated to the most significant digit.
There is a need. In other words, for bits higher than 2"6
All must be added. (Free alignment) Currently, ■ is the specification of the device of the present invention. LL=01°
10, and also in the case of PTB and PX alignment.
Similarly, the specification is ■. The functions of D and LL are 5ection T for small-scale applications.
This is provided to save space on ABLE.
be. When the designations of D and LL change, 5ection T
As able becomes smaller, there is a limit to the possible values of SX.
can. Permissible SX for each value of D and LL
The value of is as shown in FIG. 298. The reserved part of o-t, t, t, oo is
Do not use in software. Also in the manual
It is necessary to specify that it is eserved. just
However, if this value is actually set to tlATB or 5TAB,
If so, the same operation as 0.0 and LL.00 is performed. In other words,
If LL=OO, D is ignored. Specify a value that does not apply to the above table as a logical address
In this case, address change exception (ATRE) is not used.
An area reference error occurs. Page Off Exception (POE)
and address change exception (ATRE) occur at the same time
The address change exception (ATRE) has priority. example
For example, UATII D.0. Discuss with LL=IO, Pl, 0
When accessing the physical address H' 40000000
is ATRE instead of POIE. This figure shows how table space is saved by specifying D and LL.
The result is shown in FIG. 299. At this time, since the range of logical addresses to be used is narrow,
■Example where only a few STEs need to be used
If so, by doing as shown in Figure 300, 5e
The size of cHon table can be saved.
. Also, in the stack area, O8 area, etc., the last few
In the example of ■, where only the STE of
, by doing as shown in Figure 301, 5ectio
The size of n table can be saved. *If 0.1, STB is 5ection table
The first address of the valid part of (for the intermediate value as SX)
5T, which corresponds to 5X=0, rather than 5T, which corresponds to 5X=0
Specifies the address where E (which does not actually exist) should be placed.
The same applies to the PTB in the STB. A3-6. STE and l'TE STE and PTB are address conversions placed on memory.
It is a disc libter for. STE and PTH format
Let me explain about this. -STE (Section Table Entry
) Shown in Figure 302. PTB: Page Table BasePage
Physical base address of Table: Write possible
Function m=1 Write access right is in PTH protection code
Follow W=OPTI! All rings, regardless of the protection code
If write protection is violated, an address translation exception (ATRE) ring protection violation error occurs.
However, if execution prohibition is violated from all rings, an address translation exception (ATRE) ring protection violation error occurs. D: Direction Page When the Table size is small
Table direction 0・OPage Table's lower address side is valid Dsl Page Table's upper address side is valid
Effect LL: Length Page TableO size LL・00 Full size 1024 entries 4K B
Table /IM B 5ectionL・01 1
/4 size 256 entries IK B table IM
B Region LL, 10 1/16 size 64
Entry 256B Table 256KB Region
LL, 11 1/64 size 16 entries 64Bte
64KBRegionpi: page l
l PI=OPage Table exists on physical address
do not. In this case, PTB has no hardware meaning and can be used freely in O8. However, PI/0 and LL fields are valid.
It is. The D and LL fields are used to distinguish between unused area reference error of address translation exception (ATRE), ring protection violation error, and page not available exception (POE), and priority is given to the former in exception detection. . In other words, if an attempt is made to perform address translation using this STE when PI = 0, an address translation exception (ATRE) will occur if an unused area reference error or ring protection violation error is detected in the D and LL fields. Otherwise, a page out of order exception (POE) will occur. PI=I Page Table is on physical address
exist. If it is PI-1, it is possible to perform address translation using this STE. However, if an unused area reference error or ring protection violation error is detected in the D and LL fields, an address translation exception (ATRE) occurs. As in the case of STB and Sx, in the case of PTB and Px,
PTB alignment is free. That is, L.L.
When ≠11, the valid bits of PTB and PX overlap.
may occur, but the address of the overlapping part
If so, add up to the most significant digit. The mouth and LL functions are I'agc Tab for small scale applications.
This is provided to save space for l(!).
Ru. When the designations of D and LL change, r'al! eTable
e! is small, so there is no limit to the possible values of PXO.
Ru. For each value of D and LL, allowable PX
The values will be as shown in Figure 303. A value that does not apply to the above was specified as a logical address.
In this case, the unused area of address translation exception (ATRE)
A reference error occurs. For the parts D, l, LL・00, W and E are
Use the STE of D-1, LL/00, which has a special meaning.
If you try to access memory using
make a creeping motion. At this time, the value of Sx is irrelevant. Also
, PTB field and E bit are used in hardware.
Since it is not used, it can be used freely from O3. In Figure 304, “book” is a bit that can be used freely in software.
Ru. This focus is ignored by the hardware. This bit is different from "・1" which indicates reserved.
It is clear that it will not be used in the future due to expanded usage.
That's the bit. °・“ and °＊゛ are in current use.
The hardware behavior is the same, but future expansion
Because of this, the specifications δ are different. In addition, the distinction between unused area reference error and reservation ATE error
is triggered by an address translation exception (ATRE).
This is done by the error code loaded on the tack. this
The activation of an address translation exception due to an error such as STB,
Rather than being detected when setting the value of the PTE, the value
(when using address translation, that is, memory access)
is detected when the process is performed). D=1. LL=00. The function of W=0 is one 5ect
This function is used when you want to make the entire ion an unused area.
be. In this case, Page Tab for this STH
There is no le. Small size 5ecti using the function of LL≠00
When using onTable and Page Table
However, the positions of Sx and PX in the logical address do not change.
. Therefore, Pag of small size from multiple STEs
When using eTables, a valid logical address
This means that the value of This situation can be seen in the 30th episode.
It is shown in Figure 5. In this way, you can use a small-sized Page Table.
In this case, the valid logical address is connected to the b4- area.
There are some things that should not be done. However, one entry of STE
For small-scale applications where the
Regarding the table in the last part of the logical space, which has become incomplete.
LL≠0 in order to "save table space"
Considering that the function of 0 is being facilitated, LL≠00
There is no particular problem even if the addresses are not consecutive when . In STE, address translation exceptions (ATR
[E) Unused area reference error due to W.O.E.0
Address translation exception (ATRE) ring protection violation error
, a page-out-of-existence exception (POE) due to PI-0 occurs at the same time.
However, exceptions should be detected in this order.
. In other words, first check whether it is an unused area.
, then check for access rights, and finally page failure.
Check the current status. This also applies to PTH. Therefore, the page
Ring protection-related information is valid even when the ring manager is absent. However, this exception detection order is limited to one stage (STE or
I'TE), and the order of exception detection within
Priority is given to the order in which the tables are drawn. In other words, 1. At the side
Exceptions that occur in STE have higher priority than exceptions that occur.
It will be done. PTE (Page Table Entry) 3rd
It is shown in Figure 06. PFN: t'a6e Frame Number pair
The unit is 4 KB of the starting physical address of the corresponding page. This bit is freely available in this book 20S. It has no meaning in terms of hardware. R: Referenced Set to l when this page is referenced. M: Modified Set to ■ when a part of this page has been modified.
. RL: Read Level Rei/00 ring 0 can be read only RL, 01 ring
Is it possible to read from ring O~1 RL/10 ring O~2?
RL・11 Readable from ring θ~3
If a possible violation occurs, an address translation exception (ATRE) is reset.
Generation protection violation error occurred T: Type T・00 Write prohibited, execution prohibited T・Ol Write prohibited, executable T=10 Writable, execute prohibited T・11 Writable, executable If “writable”, n+1n (RL, AL)
Can be written from the ring, from outside it
It is prohibited. In the case of "Executable 11hi", IIIIX (RLIAL)
Can be executed from the ring, but prohibited from outside.
Become. If a violation occurs, an address translation exception (ATRC) will be issued.
Protection violation error occurred AL: Access Level for 1nd
icated type (when T≠00) AL・00 Access from ring O only (write, execute)
row) Possible ^L=01 “Access (fortune telling,
Execution) Possible AL = Access (write, execution) from IO ring θ~2
) Possible AL=ll Access (write, execute) from rings O~3
row) Possible (in the case of T・00) Readable from 00 ring 0-RL Write, execute
Lines are prohibited (used in the original meaning of T, R1, etc.) Refer to the unused area of the 01 address translation exception (ATRE).
8I, = 10 (reserved) ALJI (r
eserved) In the case of T・00, designation of accessible ring by 肚
Since it is not necessary, AL is used for a different meaning. This way
A1.・Unused area reference error occurs due to Ol specification.
The raw function is to make one entire page an unused area.
This function is used in cases. In this case, for this PTH
There are no physical pages to do so. NC: Non Cachable NC, 1 Specifies prohibition of import into cache.I10 register, VRAM area, etc.
This bit is set for pages where it is not allowed to import or change the order of memory accesses. NC,O Specify that it is a normal page PI: Pa
ge In PI・Q Page does not exist on the physical address. In this case, since PFN has no hardware meaning, it can be used freely for ds. However, even in Pl.0, fields such as RL, T, and ^L are
It is valid. These fields are used for address translation exception (ATRE) unused area reference errors and ring protection Ra1.
It is used to distinguish between a 5< error and a page out exception (POE), and the former is given priority in exception detection. In other words, when the PI is 0, this PTE is used to change the address.
When attempting to exchange, unused space is
If an area reference error or ring protection 8S violation error is detected, an address translation exception (ATRE) will occur;
If so, a page out exception (POE) will occur. Pl/IPageT exists on the physical address. If it is PI-1, use this PTE to perform address translation.
It is possible to do so. However, due to fields such as RL, T, and AL,
If a used area reference error or ring protection violation error is detected, an address translation exception (ATRE) occurs. Between the PFN and the logical address offset, there is no valid
Bits never overlap, so there are no alignment issues.
No problem occurs. PTE RL, T, AL values and how to actually activate them.
Specifically, the relationship with accessible rings is as shown in Figure 307.
It becomes like this. In the figure -RO is the access right from ringo, R1 is ring
ringo~ring3, indicating access rights from l
The distinction is indicated by the RNG field in PS-.・R means readable, - means writeable, E means executable
shows. When T・OO, AL≠00, 肚 has a special meaning,
The operation is as shown in Fig. 308. At this time, ・offse
The value of t is irrelevant. °Among these, T・00. A1.・
If it is 01, the PTB flap not used by the hardware is
Fields and RL fields can be used freely from O3.
be able to. If T・Ol is specified, reading is not possible but execution is possible.
You can create a page that describes your ability. This prohibits copying of the program and prevents the program from being executed.
It is also intended to introduce a charging mechanism for
It is. On the other hand, T.00. If you specify T.10, the reading
Pages that can be read but not executed
can be made. Using this feature, you can
When the counter jumps into the data area a,
You can prevent the program from running out of control by checking the
Ru. The function that prohibits execution is to protect data in memory.
It can be thought of as a function for depacking rather than a function of
I can do it. If it is possible to insert a male, please use Karanazu J1.
is also possible. A3-7.64 beat 1 SR/llR switching bit MSB of logical address
If fixed to 64bit, problems may occur when expanding to 64bit.
In the device of the present invention, the logical address is signed.
We deal with this problem by considering the number of . Expanding both SR and OR from 32 bits to 64 bits
The address space needs to extend in two directions in order to
It is. Therefore, considering the address as a signed number, UR
Consider that the SR'8M area extends in the negative direction in the positive direction of the area.
If so, this problem will be resolved. Specifically, for the 32-64 extension, the logical address
is sign-extended, and the memory map is set to the 30th
It will look like Figure 9. Or, change the way you rewrite the diagram, as shown in Figure 310.
become. By considering addresses as signed, both SR and UR can be used.
Continuity for expansion is maintained in one region. Instead, OSj+ at H' 80000000
The contact point between the i region and the knee 4←゛ region will be cut,
This is considered to be no problem. Note that the 16-bit absolute addressing mode of the device of the present invention
code (aads:16) to sign extend the logical address
The reason for this is the idea that addresses are signed.
This method was commonly used. 73 variations and LSID functions
is <<L2>>, so it is not implemented in the first chip.
is likely to be introduced in future chips, therefore
By using the LSID function for the first chip released,
Programs that do not yet exist are also available in anticipation of future implementation of LSID functionality.
It is desirable to keep the initial
Even chi knobs must avoid unnecessary overhead.
Therefore, these LSID (Logical Space Identification)
Child) Presence or absence of functions and various variations of MMt1 functions
and the compatibility of the program (O3).
It is necessary to conduct an investigation. -As for boat fishing, there are variations of specifications related to MMtl.
There are two policies for responding to this problem: ■In order to maintain compatibility, this function is not implemented.
is also executed as is with the degenerate function. In this case, performance
object-level compatibility is achieved.
It will be done. ■For functions that are not implemented, use EIT to detect them. The purpose of BIT startup is error detection and emulation.
However, emulation results in extreme performance degradation.
As a practical matter, if the object
Changes are often required at the level. Therefore, object-level compatibility is difficult, but
Specifications for each variation are revealed in advance.
If so, both specifications can be supported at the source level.
Writing such a program is not difficult. For example, if the function of the PSTLB instruction is not implemented,
It is the policy of ■ to execute STLB as PTLB.
, BIT (RIE9 is the policy of ■. ■ or ■
This needs to be considered individually.・For PSTLB /ST option, TLR and cache
Depending on the implementation of the
implementation can be difficult. However, the /ST option
The specification of the option only affects the purge range of the TLB.
, adopt the policy of ■ to maintain compatibility. That is, /S
If it is difficult to implement the T option, instead of BIT
/We decide to perform the action envisioned by AT.・LSIDa function implementation PTLB, PSTLB (7)
/SS, t 7' Regarding the implementation of /SS obscion of PTLB and PSTLB
If so, include the LSID value in the TLB and cache tags.
Even if there is not, use /SS option to purge all
Therefore, it is possible to conform to the policy of ■. but,
LSID control! Write a value to a register or
When thinking about reading things out, the object level
To achieve full compatibility with the LSID control layer,
It is necessary to provide something equivalent to a register. However, one register was implemented just to ensure compatibility.
There is a lot of waste in doing so, and it is not just the hardware.
Regarding software, LSID operation is performed in O3.
The parts that need to be done are useless if you don't take advantage of LSlo's functions.
Therefore, the LSID will be deleted.
If so, we will adopt the policy of ■. Accordingly, the /SS option
Regarding the implementation of・LSI0 function
Implementation of PTLB and /SS option of PSTLB
Regarding the implementation of the /SS option of PTLB and PSTLtl.
Therefore, the TLB and cache tags should include the LSIDO value.
Even if you do not see it, use the /SS option to purge everything.
It is possible to comply with the policy of ■. but,
LsIof#] Writes a value to the ill register or
When thinking about reading out the object record,
To achieve full compatibility with Bell, the LS [D system]
It is necessary to provide a register corresponding to the control register. and
However, one register was implemented just to ensure compatibility.
You need to have something to do. However, regarding registers just to ensure compatibility,
Also, the part that performs LSID operation in O3 is LSI
If the function of D is not utilized, it will become a wasteful process. Therefore, regarding the presence or absence of LSID, we will adopt the policy of ■.
. In line with this, regarding the implementation of the /SS option.
■The policy is as follows. The specific LSID-related specifications are as follows.
. - Presence of LSID function and implementation of /SS option
Create a one-to-one correspondence between nothingness. Processors with LSID
/SS option is available and there is no LSID.
The /SS option is not available to the processor. -1. A processor with SID is a processor without LSID.
Fully upward compatible at the object level with respect to processors.
Ru. In other words, 1. Written for processors without sIn
The installed O3 remains unchanged even on processors with LSID.
Ma'j)J<. However, the functions of LSID cannot be utilized. - Written for processors with LSID, LSID
An O3 that takes advantage of the functions of is a processor without an LSID.
It may not work with sa. Specifically, a reserved function exception occurs when using the LSID control register.
(RFE) occurs or the /SS option is specified.
A reserved instruction exception (1?lE) occurs when the instruction is executed.
or In addition, the LSID-related specifications for open U-related instructions are as follows:
It looks like this: - For LSID, when there is no LSID, PSTLB/A
Performs an operation equivalent to S/ATauraddr. Also, L
When implementing SID, in order to take advantage of its functions, use LDCTX.
TLB: Cache is not purged. When implementing LSID, write L in the tag part of TLB and cache.
Since it includes SID, LS is transmitted by LDCTX.
When the ID is changed, the error occurs in the logical space before LDCTX is executed.
The entry that was currently running is now the new logic after LDCTX
It won't hit in space. Even if it's not a hit, it's new
Parsed unless replaced as the entry loads.
Since the change is not performed, LDCTX is executed again and the previous
When you return to the logical space, the entry remains as is.
It becomes effective. (Parse cache and TLB with LDCTX.
LSID will lose its meaning if it is ignored.
. ) - then DATE/PT, LS ([PSTL when there is no 1
Performs an operation equivalent to B/As/PT. When implementing LSID,
If prgaadr is SR, I'5TLB/AS/P
If the operation equivalent to T is performed and prgaddr is OR, then
PSTLB/SS/PT (LSI low oITAG=RO
) Performs the corresponding operation e prgaadr is SR or UR
It seems that the operation is different depending on the case, but this:=LD
The problem with ATE is that the PSTLB operation is different from tlR.
This is because they are different in SR. L D A T E life
The operation of the command itself is affected by changes in the ATE.
By purging LB and cache - thoroughly
There is. -LDATIE/STte is [,5ID(7) when P
Performs operations equivalent to STLB/AS/I'T. LSID
When implemented, if prgaddr is SR, r'5TLB/
^ Performs an operation equivalent to S/PT, and prgaddr is tl
If it is R, PSTLB/SS/5T (LSID-of-
TAG=RO) performs an operation equivalent to (/PT)
) - If UATB and 5ATB are changed using the LDC command,
, if we consider that we have executed the virtual command LDATE/AT.
Good<, similar to LDATE/PT, LDATE/ST
Perform the action. In other words, when there is no LSID, 5ATB
If you change the PSTLB/AS/AT (prga
ddr=SR) and perform the corresponding operation [Change IATB]
PSTLB/AS/AT (prgadd
r・OR). 5A when LSID is installed
If you change the TV, PSTLB/AS/AT (pr
gaddr=SR) and change the UATB.
If the PSTLB/SS/AT (LSID-o
f4AG=LSID, prgaddr=UR) equivalent
Perform the action.・4. ■ -j and Z nu ``L'' format of each command
The notation for lag changes is as follows. - No change 10 Tree that changes according to the original meaning of the flag Changes different from the original meaning of the flag 0 Cleared to 0 l Set to 1 As shown in FIG. 311. A4-3. -Δ Shown in Figure 313. ^X-flag of DDX and 5UBX is the size of dest.
Indicates carry up and down from the zero. src and d in 5UBX
If the sizes of est are equal, XJIag is an unsigned operation.
It can also mean the relationship of size in calculation. On the other hand, Ljlag has a magnitude relationship as a signed operation.
represents. MtJL, MULU, MULX, DIV, DIVU, D
IVX, REM, REMU, NEG town flag, Z
-flag is set to de regardless of the occurrence of overflow.
The st setting value is the reference. MULX, DIVX road flag, Z-flag is r
It is not related to the eg setting value. VJIag of old ■ is divided by 0 or (minimum negative number) ÷ (-
1) is set. The VJlag of the old vU is set when dividing by 0. The V-flag of DIVX is divided by 0 or the quotient is dest.
Set when the size does not fit. VJlag of NEG is when dest is the minimum negative number
is set to INDEX town flag and ZJIag are Xreg settings
The value (part of the result) is the criterion. LJlag is the result
being negative, VJIag is
Shows bar flow. A4-4. tAri・. Δ Shown in Figure 314. NOT town f lag, ZJ lag are set to dest
The value (inversion result) is the standard. M-flag and Z-flag set des to the set value (shift
results) are the standard. The last value shifted out is stored in the X-flag. If count#f O in SHA, SIL, ROT
becomes X-flag=o. In SHA, if there is a change in sign with count > 0,
VJ lag=1. Otherwise Vjla
g: 0° Shown in Figure 316. For fixed length bit field instructions, BFCMP, BFC
MPU changes flags according to CMP, CMPU, and
Instructions other than these change flags according to MOV and MOVU.
do. 8FINS, BFINS (J(7) case, Figure 318 (
DBBBB888B is the reference for flag change. Also, BFEXT and BFEXTU are the extracted bits.
destination field, not the destination field.
The flag changes based on the value. This is the MOV instruction
etc., the value set on the destination side is
This is based on changes in the flag as a reference. Shown in FIG. 319. Since sign extension is meaningless for BCD numbers, they are basically unsigned.
It is assumed that the number of
Let it be a lag change. In addition, AD()X, StJ[3X are
Somewhat irregular because it handles both unsigned and signed numbers
The flag changes are ADDU, ADDDX, S
This is a different flag change from t, IBU, and 5UBDX.
. The device of the present invention does not support lO base operations. F-flag of 5M0V, SCMP, 5SCH is finished.
Indicates termination due to conditions (search success in case of 5SCH)
. Vjlag is determined by the number of elements when the instruction is finished.
Indicates the M-flag is used to distinguish between multiple termination conditions.
Ru. 0 if it ends under conditions related to R3, otherwise
If it ends due to the relationship of 0 or R4 (<<L2>>
) is 1. SCMP X-flag, L-flag, Z-flag
is set based on the comparison result of the final element.
Ru. XJIag is when considering elements as unsigned data.
Size, LJIag considers elements as signed data
Indicates the size when QINS Z-flag indicates that it was inserted into an empty queue
shows. QDEL's ZJlag is the entry deletion result queue
indicates that it is empty. In addition, QDEL V-fla
g is an attempt to remove an entry from an empty queue
shows. QSCII's F-flag indicates termination (support) based on termination conditions.
success). V-flag indicates termination (search) by queue termination field R2.
failure). The town flag is used to distinguish between multiple termination conditions.
. 0 if it ends under conditions related to R3, otherwise
If it ends with a relationship of 0 or R4 (<<L2>>)
) becomes 1. A4-12. It is shown in Figure 323. For jump-related instructions, the flags do not change at all. Shown in FIG. 324. A4-14. ■ 'n-n
o - Shown in Figure 326. If PSW is specified as dest in LDC, all the
changes. A4-15. O5' n A Shown in FIG. 326. The device of this invention does not support JRNG and RRNG.
-16. MMU' jA is shown in FIG. 327. MJIag of AC5 instruction is readable, L-f lag
indicates that it is possible to execute, and ZJIag indicates that it is possible to write.
. MOVPA's Vjlag is a page fault or
Indicates that the physical address could not be obtained due to an error.
. FJIag indicates a page fault. LDATE, 5TATE VJlag is page for
ATE transfer could not be performed due to default or error.
and The device of the present invention supports MMU-related instructions other than AC5 instructions.
does not start. (hereinafter l, pa extra -;, white) also -,, -,ni- S 5. With respect to ′ of j, in the device of the present invention,
, performing various operations between integers of different number of bytes
This is called "operation between different sizes." Even though it says "different sizes", it currently only targets integers.
data size conversion is zero-extended or signed.
All it takes is a simple process of number extension. For example, 32 bit
When adding an 8-bit signed integer to an integer, the 8-bit
Extends the sign (MSB) of an integer to the upper bits
After that, addition is performed. The sign extension process is
Since it can be done in one or two stages, it is much smaller than a general addition instruction.
It's not that complicated. A3-1. Operations between different sizes of size μ are often used in the following cases.
. ■Time variables and constants where one of the operands is an immediate value
When performing an operation, the size of the constant is determined at compile time.
Therefore, if the constant is treated as a smaller size, the instruction
Effective in reducing length. For example, 32 bit register
When adding the 8-bit constant 100 to the data, the 32-bit
If you use the addition instruction, it takes 32 bits to specify the constant 100.
field is required. However, 8 to 32 bits
If you use the instruction to add bits, you can specify the constant 100.
Since the field is only 8 bits, the instruction is shorter. Furthermore, in the case of multiplication and division, not only the instruction length but also the performance
But it has an impact. 32 to 64 bits for microprocessors
It is difficult to have multiple parallel multipliers, so
Multiplication is performed by calculation and shift, but the calculation method for multiplication is
increases in proportion to the product of the two operand sizes, so
Therefore, even if only one of the two operands is small,
The latter is advantageous. If there is no function for calculations between different sizes,
For example, you can simply multiply a 32-bit variable by 3.
must also perform 32-bit multiplication.
do not have. ■Address calculation In address calculation, the size of the destination of the operation is
The address width must be the same as the address width. But then,
For 32-bit processors, 32-bit and other sizes
Frequently perform calculations with For example, a character conversion table
In this case, the table index range is 8 bits.
If it settles, the addition of the index and base address is
, as an addition of an 8-bit unsigned integer and a 32-bit integer.
This will be realized. (Hereinafter, ,'mu-...white) -I, + ■High-level language Generally, in high-level languages, the size of subroutine parameters is
Make sure to expand the file size to the base size of the machine (for example, 32 bits).
often tense. This uses the stack to create a subroutine.
Chin parameters can be passed and split compilers
This is to make it easier to access files, etc. Furthermore, like language C
The expression is evaluated regardless of the data size of the variables in the expression.
In some cases, the value is always determined based on the basic size of the machine.
. On the other hand, variables in memory, especially arrays,
To save money, it is common to keep the size to the minimum necessary.
. Therefore, programs that use arrays and subroutines at the same time
In the program, during data movement or calculation processing,
You may need to perform a size conversion somewhere.
come out. To evaluate the expression and convert the size at the same time
It is convenient to perform calculations between different sizes like the device of the present invention.
be. A3-2. In order to support calculations between different sizes, the device of the present invention
Therefore, orthogonality regarding data size specification is very strong.
2-operand film format (G-format)
Most of the basic operation instructions can perform operations between different sizes.
be. In other words, in a two-operand-membrane basic arithmetic instruction,
, the source size and destination size are unique.
It can be specified as
It is designed to truncate bits, etc. De
destination size is smaller than source size
The operation is also performed if the size of the destination
Overflow is detected according to Below is a practical example of operations between different sizes in each instruction.
Bell. B: Byte 8 bit H2) ralf
word 16-bit W: Word
32 bit MOV src, B, dest, W8
Sign-extend bit src to 32 bits and make it dest
transfer. MOV src, W, dest, B Transfer lower 8 bits of src to dest. When the value of src as a 32-bit signed integer and the value of destO as an 8-bit signed integer are different, an overflow occurs. ADD src, B, dest, W 8-bit src is sign-extended to 32-bit and des
Add to t. The values set in ADD src, dest, B dest are the lower 8 bits of src.
is the same as adding dest to dest. However, the meaning of the instructions is src (32 bits) and dest (
8 bits to 32 bits) and add 8 bits to 32 bits.
This means converting it to a bit signed integer and storing it in dest.
That is. Therefore, the sum of 32 bits can be expressed with 8 bits of dest.
If it reaches a value that does not exist, an overflow occurs. In the device of the present invention, source and destination data
If the sizes are different, sign extension is usually performed. however
, especially instructions that are considered to require zero extension (MOV, CM
For P, ADD, St, 18), zero extension and sign
Separate extensions at the instruction level, MOVU, CMPU, A
The DDU and 5UBU instructions are used. MOVU, CMPU, ADDU, 5UBU <Additional 1”
MULU, DIVU) Te is the destination service.
Zero-extend when the size is larger than the source size.
Detect overflow by considering the result as an unsigned integer
do. A3-3. In the case of “logic operations” in the sensor, each bit is completely independent, so
The calculations between the flags are meaningless, and apart from changing the flags, the calculations are small.
(equivalent to the size of the dice), the opera of logical operations
Zero-extension and sign-extension for the
do not have. However, for example, if you write the following function in C,
Even if there is no meaning, it is necessary to perform the operation of sign extension → logical operation.
be. foo(X 5hort 1nt16; /*32-bit signed integer*1 int 1nt32; /*32-bit signed integer*1/1nt32 &= 1nt16; /, t 1nt16 is sign-extended ne/However, like this
Such examples are not determined due to the regularity and symmetry of the language.
Some tricky programs
It can be said that it is a function that is hardly used except for. Whether to support different size openings for logical operations
The problems can be summarized as follows. ■Logical operations between different sizes at runtime are extremely rare and have no logical meaning. Essentially, they can be substituted with other instructions, or are only used in tricky programs. ■Compiling time In the C language, zero extension or sign extension may be required even in logical operations. Even if the function is not used often, the compiler must always generate correct code. Symmetry of instructions is important. ■Chip Implementation If the distinction between sign extension and zero extension is made uniformly for all instructions, there is an advantage in introducing zero extension and sign extension even in logical operations from the viewpoint of regularity of implementation. However, this requires a large number of bit patterns for instruction assignment, which makes encoding the instructions difficult. In reality, it involves logical operations
It is not possible to distinguish between sign extension and zero extension for all instructions, and there is no advantage in implementation regularity for sign extension and zero extension of logical operations. Additionally, manufacturers may have different opinions on this area, making it difficult to match specifications. In the end, the question is which of the above should be prioritized: ■ or ■.
However, if you are aiming for substantial performance improvement,
I think it is appropriate to select ■. In other words, ・There is little meaning to be performed, such as logical operations between different sizes.
The performance improvement will be slowed down due to unnecessary calculations.
Regarding the problem of ■, including sign extension,
Logical operations between different sizes are infrequent operations.
However, the execution speed may be slightly slower. For example, AND src, B, dest, Wsrc
MOV src, B, @-5P, Wsrc instead of
Zhang AND @SP÷, W, dest, W, then many
Although the execution speed is slightly lower, it is possible to use sign extension to uniform calculation instructions.
Replacement is possible. This way, the burden on the compiler will be
does not increase that much. Therefore, the specifications of the device of the present invention are that
does not support logical operations. Instruction bit patterns corresponding to logical operations between different sizes
If you do so, we do not guarantee operation.
It's full. Instructions supported by the AFr4 j device of the present invention and integer data types
The relationship can be summarized as follows. ψ8. IS, supports 32.84 bit long integers
.・Support signed integers with priority.・For signed integer arithmetic operations, two-operand instructions are required.
Operations between different sizes are supported in the instruction. The source size and destination size are completely
can be specified independently, and there is no size limit. The source is better
If the size is small, it is sign extended. The result is signed
tree! ! treated as a number and flags are set accordingly
be done.・Unsigned integer operations can be performed using some instructions (MOV, CMP
, ADD, SUB, MUL, DIM)
It is. As for size, it still depends on the size of the source and the design.
Destination size can be specified completely independently
. If the source is smaller, it will be zero-extended.
. The result is treated as an unsigned integer and flagged accordingly.
settings are set.・Signed integers and unsigned integers! ! Operations involving mixed numbers are
Can not. However, in cases such as addition instructions, the destination
The presence or absence of a signed version only affects the flag, so
If you don't see the flag, use 8DD or ADDU instead.
can. - Logical operations between different sizes are not supported. (Hereafter, 5 o 1, white) ・6. 1 o ki ru ゝ call in high-level language
In a subroutine call, it is simply a return address.
In addition to evacuation, frame pointer settings and local
Processing such as securing variable area and saving general-purpose registers is also performed.
is necessary. These processes are performed using instructions such as JSR and STM.
Although it is possible to decompose it into
is formulaic, one command (ENTER,
EX ITD). Rune call advanced language in AS-1, II 't
In the edict (especially C, PASCAL) subroutine call
, the process shown in FIG. 328 is normally performed. In the device of the present invention, the high-level language subroutine command ENTE
R and a return instruction EXITD are provided. Here are some points to keep in mind.・Languages with static scope such as FP (frame pointer) and display register PASCAL
Now, at the intermediate level (inside local variables and global variables)
display registers to access variables (levels between)
Use. Processes with many registers, such as the device of the present invention,
In the server, this display register is placed on the general register.
It is effective to put This means having multiple FPs
Equivalent to. (The implementation method will be described later.) To pass the medium parameter parameter, write it as a packet and its starting address.
How to pass parameters using registers, stack parameters etc.
The latter method is more common in high-level languages.
Ru. Parameters on the stack on the side of the called subroutine
FP-relative mode is often used to access data.
stomach. After the subroutine is executed, the caller saves the parameters on the stack.
The meter needs to be released. Folded and divided by language
If you do not compile, the callee will not be able to specify the exact parameters.
Since the number of data is known, release it in the return command.
You can specify the number of parameters (additional value to SP).
Ru. The device of the present invention provides an EXITD command for this purpose.
Ru. In some cases, the number of parameters is determined dynamically (for example,
For example, to inform a subroutine of the number of parameters,
(e.g. when using fixed registers or stack), EXITD
The value added to SP in the instruction is immediate
You can use not only values but also values in registers.
. However, like the language C, the number of parameters of a subroutine is
In languages where numbers are not determined, whether the subroutine is called
are the number of parameters determined by the subroutine caller.
I don't understand. Therefore, the EX executed on the called side
I TD command specifies the number of parameters to be released.
Can not. In that case, the side that called the subroutine should
DD #n, perform SP to release parameters. In the end, the EGI T ER command of the device of the present invention
2. Processing of ~4, EXITO command is 5. ~7. of
processing, or processing 5 to 8 (however, the package released in 8.
The number of parameters is specified on the subroutine side).
Ru. 1. The process is the same as JSR, and 8. is a sub-rouche
The person who called the player performs ADD *Nene, SP. The stack frame in high-level language in the device of the present invention is:
The result will be as shown in Fig. 329. 111 local variables and parameters
In order to ensure that the ers is as close as possible to the FP,
Saved registers after securing local variables.・EXITO command requires PC glue store (RTS) operation
It includes up to , Δg, ′ (when the number of parameters is unknown on the subroutine side) is shown in Figure 330. (When the number of parameters is known on the subroutine side) This is shown in FIG. 331. AS-2, Mouth... 9th position
Die the FP register processed by ENTER-EXITO.
In order to use it as a dynamic link, the inner block must be
frame point relative to the peak (highest lexical level)
It is better to allocate the FP register to the data. Other lexical level frame pointers have values
Use R13, R12°R11, etc. in order of least change in
cormorant. In other words, to the inner block with a higher lexical level
As you go, use the registers with lower numbers, and go to the lowest number.
Make the contents of the number register the same as FP. In each subroutine, after executing the ENTER command, the FP is automatically
A frame pointer register corresponding to the lexical level of
register, and display registers with that number or higher.
The registers below that number are used as ray registers for evaluation.
You can use it as. However, the newly rewritten register
The data must be saved and the value saved. Shown in FIG. 332. *proco*, varOne proco, but due to recursive call, the first ρr
The frame is different from ocO.・Registers that will be destroyed by copying the FP should be
All must be evacuated using the ENTER command. cash register
If you save the data, when the subroutine finishes executing and returns to the previous function, the display will return to its original value regardless of the lexical level. In the above example, the following relationships hold regarding how to use registers. Regarding subroutine execution at lexical level n, n registers R13, , R13-n+1 are disks.
It is only read as a play register and not written to. ■The R13-n register is a local variable at this level.
To use it as a display, copy it from the FP after pressing ENTER.
. ``This display is used to access variables at this level from the called subroutine when a higher level subroutine is called during execution of this subroutine. To access variables at this level from this subroutine, it is best to use FP, which has the same content. ■R13-n-1. ．． (13-n) registers of RO
is used as a register variable or for evaluation. ■R13-n register and R13-n-1, RO
Registers used later must be saved with the ENTER instruction. All registers must be saved.゛ 7・'9' E control register
The related specifications are based on the chip bus (coprocessor and cache).
, bus connected to TLB, etc.) and implementation method.
Because of the close relationship with ``LA'', it is specified as <<LA>>. A7-1. ' In the device of the present invention, the main processor on the chip bus
and all registers included in the coprocessor, MMU,
Cache, control registers such as TLB, and chips
High-speed memory for context switching connected on the bus
We give a unique address to this space and call it the control space.
The control space of the device of the present invention is different from that found in conventional processors.
address space for the coprocessor
or-ID, etc.) in the control register of the main processor.
It is integrated with the address and has become a membrane, and the following
have characteristics.・The control space of the device of the present invention includes the following:
be caught. The control register PSW of the main processor, the stack pointer of each ring, and other MMtJ-related control registers (the ``device of the present invention'' refers to the MMU
Registers that are required depending on the implementation such as UAT8, 5AT8 [Coprocessor control register] [High-speed memory for context saving] Items that are intended to be built into chips in the future [General-purpose registers in the processor, The purpose and control space for diagnosis and debugging from outside the rally register is
It is a common space. Control space access is address translation
fast access with a simplified protocol.
access is possible. This feature is particularly useful for fast contexts.
Also used on switches. In the future, the concept of control space will be expanded to include coprocessors and contexts.
For memory storage - when memory is built into the main processor
, is considered to be particularly effective. However, in the first version of the chip, the implementation
Due to the limitations of the control space or the structure of the chip bus,
In the future, it may be difficult to perform operations uniformly.
Deciding only the address assignment in preparation for the
Interoperation instructions may be used with some restrictions.
I'll say it. Specifically, the following restrictions apply.・For the purpose of diagnosing the processor, RO~R15 and PC
The control space address is also assigned to
is <<L2)>, which must not be implemented in the device of the present invention.
stomach.・LDC and STC are originally control layers within the main processor.
Unified access to registers, FPU control registers, context save memory, etc.
That's what I was aiming for. However, in the device of the present invention
Due to implementation limitations, constraints within the main processor
Other than control registers (effective addresses H'0 to N'07ff and above)
Those outside) can be accessed at LDC and STC.
do not have.・In the address of the control space of the “device of the present invention”, the byte address is
access, halfword access is not available. Also,
Alignment is forced on word accesses.・Context save memory is an area where control registers are placed.
It cannot overlap with the area (H'0~). context
As the save memory, H'ffff8000 to H'f
fff ffff address is assigned (
Furthermore, as an extended area H' 80000000 ~)
So, H' 80000000- H' ffffffff
Set a value other than f to CTXBBCZ and set it to LDCTX/C5
If ,5TCTX/C5 is executed, an error will occur.
. Also, LDCTX/C5, 5TCTX/C3 (7)
Function 01 is also <<L2>>.・In the “device of the present invention”, LDCTX/C5,5TCTX/
Does not support C5. □: Required specifications <<Ll>> 1----near address assignment only <<L2>> 33rd
In the control space shown in Figure 4, byte access and halfwork
Byte address access is not possible even though address access is not possible.
It has become a shing. This is used in general commands.
Just as in the logical space, the control space also uses general-purpose addresses.
Execution addressing can be specified by programming, and logical space and
If you do not use the same form of byte addressing, confusion will occur.
This is because it invites In addition, general-purpose addressing is possible in the control space.
The reason why the control space can be used is when the control space is saved as a context.
This is because we thought that it would be used for Control registers in the main processor with LDC and STC
Byte addressing
It loses its meaning and becomes a somewhat unnatural specification.
Ru. However, behind this is the future outlook as mentioned above.
, and if only the − part of the function is realized, it will look somewhat unnatural.
It is unavoidable to see it. A7-2. 9 control registers
The mnemonic and address of is as follows. Control register at. The response at position 80+4 means that the register is set to 64 bits.
This is because we took into account the expansion to other areas. o'ooo~H'03ff Main processor, M
MU (TRON reserve) H'0400~H'07ff Main processor, M
MU <<LV>> )! '0800~H'0bff FPU (TRON
reserve))1'0cOO-H'0fff
The FPU<<LV>> is a register that is prepared separately for each context.The register address does not necessarily need to be implemented (address assignment).
PS H'0O0B
reserved H'000c (ne) S
MRNGt('0010 r
eserveH'0014 (ne)
H'0018 to IMAS
reserveH'0O1c
reserveH'0020
reserved-EITVB)l H'0024 EITVBH
'0028 reserve
d-JRNGVBH H'002c rThis invention device'rese
rved --JRNGVBH'0030
reserved-CTXBBH H'0034 *CTXBB
11'0038 reser
ve)1'003c res
erveH'0040 re
served-5ATBH H' 0044 rThe device of the present invention"eser
ved --5AT8 H'0048 reserved-U
ATB) I H' 004c ne "device of the present invention" res
erved --UATB )1'0050 reserveH
' 0054 zero "device of the present invention" rese
rved --LSID H'0058 reserve)1
'o05c reserve1('
0060 reserved
-10ADDRH 1 ('0064 / l0AD
DR11'0068 res
erved-10MAsK)I H'006c/IOMAs
KH'0060~H'007f rese
rveH'0080 res
erveH″0084 (ne) “Device of the present invention”
reserved --DCE )1'o088 reserved1
('008c DI)1'0090
reserveH'0094
``The device of the present invention'' reserved --
C3W H'0098 reserve
H' 009c (ne)r present invention device'res
erved --CTXBFM)1'00aO~H'
0Off reserveH'0100
reserve-5PIH H'0104 5PI) 1'0
108~H'011f reserveH
'012f) reserve
-5POH H'0124 * 5POH'
0128 reserve-5
PIH N'012c ``This invention device'' rese
rved --5PI fl'0130 reserved-
SP2H H'0134 * rThis invention device"res
erved --5P2 H'0138 reserve
d-5P3H H'013c * 5P3H'0
140～)l'o17f reserve
d H'0180 reserve
ed-ROH H'0184 No. r This invention device"rese
rved-RO H'0188 reserve
ed-RIH H'018c ne "Invention!! Placement" res
erved --RI H'01eOreserve d-R12H H'01e4 *rThe device of the present invention"reser
ved --R12 f('01e8 reser
ved-R13H H'01ec *rThe device of the present invention"res
erved --R13 11'o1fOreserve d-R14) 1 11'o1f4 *rThis invention device're
served --R14 H'01f8 reserved
ed-PCI+ H'0ffc trThis invention deviceJres
erved --PC I'0200~)l'03ff rese
rved (H'0400~) l'07ff
<<ll/>>H'0410 8
8C)1'0414 8BP)1
'0500 9BCH'052
0 XBPOH'0524
XBPIH'0540
08POH'0544
0BPIA7-3.1' Cash register
Bits: Bits that are not used in the control registers.
If you write l, check it and write EI.
It is desirable to set it to T. However, a half-hearted check
Doing so will maintain compatibility (especially with lower chips)
overhead for checking
, unused bits except PS%/
We will not perform the check t. For registers with <<L2>> functions such as CTXBFM
Even if <<12>> is not implemented, an error will occur.
A search is not performed and the written value remains unchanged.
However, it does not necessarily mean that it will be read out. However, even if no check is performed, free bits are
In the manual, etc., be sure to enter '0' in
It is necessary to instruct. For PSW, write '1' to unused bits '-2'.
If you try to log in, a reservation function exception (RFE) will occur.
. 2-j, l= in the description of the contents of the control register below
The meanings of bits j, J, and j are as follows. '-20 reserved (Exception occurs when violation occurs) 1+
This bit is reserved to 21 (an exception occurs when a violation occurs).
Although it is possible to write a 0 (1) to this bit, it is not possible to write a 1 (0) to this bit.
Then, a reservation function exception (RFC) is generated in LDC, LDCTX, etc.
) occurs. Reserved to ゝ=10 (ignored even in case of violation)'#'
Reserved to 1 (ignored even in case of violation) This bit
is the bit to which 0 (1) should be written, but any attempt to write 1 (0) to this bit will simply be ignored, and the operation will be the same whether you write 0 (1) or 1 (0) to this bit. be. The user manual specifies that this bit should be written to 0 (1) for future expansion. ′＊ゝ The value when writing is free. The hardware operation is the same as j=j, Ill, and which
If a value like , is written, it will simply be ignored. However, this bit differs from ) = Zjllt in future chips.
This bit is not used even if the function is expanded. Therefore, the user may write any value. In the manual for users, it should be clearly stated that these pits will be ignored, and the user should be asked to omit bit masking.・IMASK, SMRNG, DI, DCE, CTXB
In FM, unused bits are 'zero'. P.S.
In W, unused bits are 2-9. After that
In the external control register, unused bits are 2 = 1.
be.・Unused fields of PSB and PSM are also '-2.
Ru. Therefore, even in LDPSB and LDPSM, reservation function example
outside (RFE) occurs.・When reading the −ゝ bit, 20′ is read.
be done. l=? , when reading the bits of
The value obtained is indeterminate. The previously written value remains unchanged.
However, there is no guarantee that it will be read out. A7-1' The contents of the Processor 5 status word shown in Figure 335.
See text for details. User-accessible lower 2 bytes of PSW
Extracted only. LDPSB, LDPSM, 5T
It is accessed by PSB and STPSM instructions. Control level
Among registers, only PSB and PSM are larger than ringo.
Accessible from outside. Of the PS%/ shown in Figure 336, IMAs that are frequently accessed individually
The field in S is extracted and made into a separate register.
be. Easier operation of IMASK and improved performance
It was aimed at For fields other than IMAsK
, whatever you write will simply be ignored. Among the PSvs shown in Figure 337, SMRNs that are often accessed individually
The G field is extracted and made into a separate register.
Ru. SM, RNG ease of operation and performance
It is aimed at improvement. Feel other than SMRNG
Whatever you write to the code will simply be ignored. Context Block Ba5eCTX8 base shown in Figure 338
A register that points to the address. LDCTX, 5TCT
Used by the X command. CTXBB is designed to be expanded to ``device of the present invention''64, and
Forcing 8-byte alignment even with “Invention Device” 32
There is. Therefore, the lower 3 bits of CTXBB are '==
=2. In other words, it is reserved to 0, but
Ignored even in case of violation. DI Dela ed Interru as the third
Figure 39 shows the DI (Delayed Interrupt) request.
register. DI=OOOO External interrupt (NMI) processing with priority O
Later 01 request DI = 0001 D after priority 1 external interrupt processing
I request DI = 0010 0 after priority 2 external interrupt processing
1 request o+=ttto After processing an external interrupt with priority 15
01 request DI=1111 DI without DI request (Delayed Interrupt)
Mechanism for generating external interrupts by software
, and bends various processing requests that occur asynchronously.
Useful when you want to log or serialize the processing order
It is. After processing a high priority external interrupt
If there is a process that you want to start separately, register that request in Dl.
By recording the process, the process will be started automatically. Dl performs the same processing as DCE for external interrupts.
It is now. PS%II due to REIT orders etc.
If the group ASK changes, if 01<IMASK
For example, D10EIT processing is activated. What should I write to the fields other than DI in this register?
is simply ignored. Context 5tatus Word This register shown in Figure 340
out of the information that needs to be switched for each context.
This is a collection of items that are not on strike. DCE(
Delayed Context Exception
) DCE field indicating the request and CTXB formatter
It consists of a field in CTXBFM that indicates the cut. CTX
See Appendix 8 for BFM functions. If the CTXBFM functionality is not implemented
, the DCE register and C5W register handle exactly the same information.
Therefore, the C3lll register must also be implemented.
(RFE when accessing). At this time,
Formally, what is placed in CTXB is the C5W register.
However, it is actually a DCE register. The relationship between C5W, DCE, and CTXBFM (7) is with PSW.
IMASK. The same applies to the SMRNG relationship. It is placed in CTXB
is C5% compressed information such as DCE, CTXBFM, etc.
/ is the one who is. ocE='ttt7 is fixed for the device of the present invention. Delayed Context Exception shown in DCE No. 341ffl
Among C5 enemies, DCE that is often accessed individually
The field is extracted and placed in a separate register. The aim was to make DCE easier to operate and improve performance.
It is. Anything you write to fields other than DCE will simply be ignored.
be seen. If the Cs%ll register is not implemented, the code
CT instead of C5W register when text switch
It is this DCE register that transfers with XB.
be. In this case, when saving the context, the
All bits become O and are written to CTXB. Ma
In addition, when loading the context, the value of the 'zero' part is
The value of the set is not checked. CTXBFM Context Block Format C5W shown in Figure 342
CTXBFM files, which are often accessed individually.
The field is extracted and placed in a separate register. CT
The aim is to make XBFM easier to operate and improve its performance.
It is something. What are the fields other than CTXBFM?
Even if you write it, it will simply be ignored. This register is <<C2>>. EIT Vector Ba5e EIT (exception, interrupt) at the beginning of the vector table shown in Figure 343
Indicates a physical address. EITVB is “device of the present invention” 64
Considering the expansion to
Forcing the line. Therefore, the EITVB
The lower 3 bits are '==='. In other words, res to 0
erved, but is also ignored in the event of a violation. Note: JRNG Vector Ba5e shown in Figure 344. Logical address at the beginning of the JRNG instruction vector table.
shows. The base address of the table by JRNGVB is r.
Considering the expansion to "Inventive Device" 64, r Inventive Device H, No. 32
also forces 8-byte alignment. Also, JR
The LSB of NGVB is an enable bit,
When E is 00 o'clock, JRNG execution is prohibited. therefore,
J The lower 3 bits of RNGVB are expressed as l == E I.
has been done. '=2 bit is reserved to 0
However, it is ignored even in the event of a violation. SPO~SP3 5tack Po1nter for ring3ri shown in Figure 345
Stack pointer used in ngO-ring3. Alignment constraints for SPI, SPO to SP3
It is valid up to the LSB. Nail 1 5tack Po1nter for Interru shown in Figure 346
pt Stack pointer for external interrupts. 10ADDR101 payment S When address conversion shown in Figure 347 is not performed (, PSW AT = 00
．． 10), specify the physical address of the 110 area.
This is a register. Normally, when performing address translation with MMU, during PTE
The 110 area is specified by the NC bit of the
When address conversion is not possible, such as when starting the system,
is l0ADDR. 110 area fingers using two 10MASK registers
make the determination. When accessing memory without address translation, the physical address
The AND of address and IOMAS is equal to 10ADDR
If so, that area is considered to be one area. data for that area
For information on caching data and briefing
The fetch is not performed and the memory access requested by the instruction is
There is a one-to-one correspondence between actual physical memory accesses. l0ADDR if there is address translation. No registers are used for 10MAS. Also, the processor
Caching and prefetching by implementing
If not, l0ADDR, IOMA
There is no need to use the SK register. ■ tJnshared region Address shown in Figure 348
Translationase See Appendix 3 for details. ■ 5hared region Address Tra shown in Figure 349
nslationBase See Appendix 3 for details. ” (not implemented in the ``device of the present invention'') shown in Figure 350.
Logical 5pace IQ Inserts a number that distinguishes between multiple logical spaces. Mixing B and logical caches belonging to multiple logical spaces
Use this number when placing your order. Valid LSID
The number of bits is implementation dependent. −8,r [1? (7) CTXBA8-1. C
Regarding TXB, the "device of the present invention" does not have an MMU, so it is called the "device of the present invention".
How to support CTXB format in
It is currently under consideration. O5 supports parallel processing and collaboration such as tasks, processes, etc.
- If the machine supports the functions of a PC or general cash register,
Information about hardware resources such as
It is normal to have a separate one for each program.
be. These hardware resources, like processors,
This is used for programs that are not currently running.
Information about hardware resources to be used is saved to memory, etc.
It is necessary to keep it. In the device of the present invention, this is the unit of parallel processing.
The flow of a program is called a context. Also, each
hardware resources to run this context.
Conte is the information that has been saved in memory.
It is called xtBlock (CTXB). The space where CTXB itself is placed is LDCTX, 5TCT
As an option for the X instruction, the logical space and control space C5
You can choose from more. In terms of O5's respectability, LS is better.
Suitable for use, but do not specify context switches.
When you want to speed up the process, or for saving context switches.
When providing memory within a chip, C5 can be used.
You can also do it. However, the designation of C5 means that the future context
It is effectively utilized when the save memory is built into the chip.
Currently, it is <<L2>>. Ma
In addition, in the device of the present invention, the currently executing context
A register is provided to hold the start address of CTXB.
This is the CTXB Ba5e Register
It is called (CTXBB). The format of CTXI3 of the device of the present invention is as follows.
The sea urchin is turning. Some of these are LDCTX, 5T
Supported in hardware by CTX instruction
. rll32c7) c'rXI3-mer
・As shown in Figure 351, it is generally necessary to switch by context switch.
is located on the user program, not on the O5 PC or PSI/
program PC and PS%/. However, the user
The program's PC or PSv is normally used when O5 is called.
It has been saved in the stack. The above CTX8 former
In the set, the PC and PSW are placed in the stack.
That's why. At the end of the external interrupt handling handler using SPI
When performing a direct context switch, use the above CT
In order to realize the XB format, the PC and PSW are separated.
Must be transferred by command. However, in this case DCE
, D is used when exiting from an external interrupt.
CE says to perform a context switch using the old
There is a way. Then, specify SPO with DCE or 01
By doing this, the above data structure can be realized naturally.
. Of the information included in MhiLevamnoteCTXB, 'ne]' to 1ne5'
The attached part may vary depending on the system configuration etc.
It is a part. These points will be explained. The content and format of CTXB depend on the following factors:
Therefore, it can change dynamically (or depending on the context).
There is.・O5 configuration and presence or absence of MMLI (*1 to 3) O5 configuration
Depending on the configuration, it may not make sense to switch between SPI and SP3 using a context switch.
If you do not want to evacuate SPI to SP3 because there may be boring cases.
There is. Also, for context switches in applications that do not use MMLI,
There is no need to switch LIATB and LSID. ($1) In JRNG-RRNG, the outer ring is inside
SP values of rings outside the current ring have no meaning. Especially in rfngo
At the time of a context switch, which is performed only
1- The value of SP3 has no meaning. 5PI-SP3
is held directly or indirectly in the SPO stack.
Therefore, by switching SPO, 5PI-SP3 is also
This is because the switching will occur indirectly. On the other hand, a context switch has occurred within TRAPA-REIT.
If this happens, it is also necessary to switch between SPI and SP3.
. Therefore, if you want to include SPI~SP3 in CTXBCZ, and if you want to include it,
There may be no. (N2) Do not implement MMU. <<LI R>> specifications
, UATB is not required. (N3) LSID is used to distinguish between multiple logical spaces.
It's a number. LSID implementation is <<L2>> note, LSID includes CTXBC:
Sometimes it happens and sometimes it doesn't.・Specification of general-purpose register to save (*4) in context
Regarding unused registers and working registers used in O5, CTXB
If you do not evacuate and restore the data, there will be no unnecessary transfers.
This reduces context switch time.・Whether or not a coprocessor is used (N5) The FPU registers are separate from the general-purpose registers;
It is also necessary to have it as context information. So depending on whether that context is using FPU or not
, CTXB may change dynamically. In order to deal with the above variations of CTXB
, the "device of the present invention" uses the following method.
.・-In the first version of <<Ll>> chip, L
DCTX, 5TCTXteC5W, SPO~SP3.
Performs UATB (7) transfer only. Regarding RO~R14
If so, use separate commands LDM and STM to transfer (*
Address 4).・For other CTXB variations, the current
A register that identifies the current CTXB format (C
TXBFM) and by this register, CTX
What is included in B and what is transferred in LDCTX and 5TCTX?
I would like to know if I have to send it. In addition, C
The combination of TXBFM and DCE is the C5v record.
It is also treated as a jista. [:CTXBFM command specifies that the FRFPU register shown in FIG. This function will be used especially when an FPU is built into a chip in the future. Specify to save RG RO-R14 This function will be used especially when a memory for context saving is built into the chip in the future. SP Specify to save SP 5P=00 Save SPO, SPI, 5P25P3
5P=01 reserved SP=10 Saves SPO, SP3 (for <<Lm R>>) SP=11 This function saves only 5PO, when calling O5 by JRNG, avoids unnecessary transfer of SPI to SP3. Use it to avoid doing it. Also, it is used when 5PI SP2 is not implemented in <<LIR>>. MM Specifies saving of MMU-related registers M units = 00 Saving UATB = OI Saving UATB, LSID = 10 Do not save MMU-related registers (for << l l fi >>) MM = 11 reserved [However, CTXBFM The details are still under consideration. Ko<<
In the standard format CTXB with Ll>>, LD
CTX, 5TCTX! i: From C3W (DCE,
CTXBFM), SPO~SP3. UATB is transferred
Ru. This can be done by setting all CTXBFM to 0.
specified. In the DCTX instruction, the new
Look at the CTXBFM in C5v of the context, CT
Determine the format of the following parts of XB and use the specified
Load things. In addition, the 5TCTX instruction sets the current CTXBFM value to
and save the specified items to CTXB. however,
CTXBFM (7) function has <<L2>> border,
This is a future expansion. In other words, the CTXB fixed specifications are <<
Ll>>, CTXB variable specifications (higher combination) are <<
L2>>. For <<LIR>> chips, SPI, SP2
．． Since UATB transfer is not required, CTXB also has these
Do not include values. CTXB contains these register values.
Identification of whether the
Is possible. However, implementation of CTXBFM is heavy
In this case, additional options for LDCTX, 5TCTX instructions
Directly specify the CTXB format using the option
Specifications and additional options for LDCTX and 5TCTX instructions
This specification specifies whether or not CTXBFM is effective.
It is also possible that A3-3. ' Econ - Some of the information held by each process or task is
It also includes information managed by software. these
Since the information is not constant depending on the O5, it is natural that the hardware
It cannot be supported by hardware (LTCTX. 5TCTX instruction). This information
is called a software context. For example, l TR
If 0M, the task status and end processing routine address
address, exception handler address, wakeup counter
area for links for configuring queues, etc.
included in the software context. If CTXB is placed in the logical space (LS), the general-purpose storage
Hardware context and software such as registers
Contexts can be treated in the same way. but,
A separate space such as C5 as a hardware context
If used, the software context will also be in C5.
In this case, commands such as LDC and STC are effective.
), or connect the two with a pointer and
It is necessary to take a method such as making a direct reference.゛9・rll-L9”-Second External Burial EIT Processing
The outline is as follows, but detailed specifications are still under consideration.
be. The flow of normal program execution is controlled by hardware mechanisms.
asynchronously in a j-shape that interrupts and interrupts it.
The process to be performed is called EIT process in the device of the present invention.
Bu. EIT processing includes the following: j
・Internal interrupt (trap) ・Exception interrupt
(exception) '・External
Interrupt (interrupt-1ninterrupt)
) The distinction between traps, exceptions, and interrupts depends on the programmer.
It is carried out depending on the cause of the EIT seen.
This is the difference between the two implementation mechanisms.
This refers to the difference in information saved to the stack, etc.)
It's not something you do. When the processor detects an EIT during instruction execution, the sequence
interrupts the execution of a formal instruction and starts EIT processing.
. In EIT processing, the processor's
Save the state to the stack and start the EIT handler. Everything up to this point is done by the processor hardware.
Ru. On the other hand, in the activated EIT processing handler, the EIT
Depending on the error recovery, error message display,
Performs processing such as curation. EIT processing handler
is realized by software. most part
In this EIT, the REIT command is executed at the end of the EIT processing handler.
By issuing an instruction - the original sequence of instructions that was interrupted
It is now possible to return and resume processing. In the "device of the present invention", future functional expansion is considered J, undefined
error detection and emulation for commands and illegal commands.
The plan is to strengthen the mechanism department for applications. Therefore
Therefore, illegal operations may be performed due to combinations of instruction formats.
or if the machine is not implemented.
When attempting to perform a function, try to avoid errors as much as possible.
is detected and generates an exception interrupt. The EIT generated by "Moryu"H Koshukari device of the present invention" includes the following:
There is. [Memory, address related] Page out of existence exception (POE)
・・・・・・・・・・・・r This invention device does not cause
No Page Out Exception (POE) life
In address translation when accessing an instruction or operand, UATB, 5ATB, STE
, occurs when the P1 bit of the PTE is set to 0. meaning
In terms of taste, it includes page absences, page table absences, and section table absences. This is a so-called page fault exception. Address Translation Exception (ATRE)
(ATRE) Occurs due to an error during address translation. Specifically, reserve in STE, PTE
If you are using the ed bit pattern, UATB,
5ATB, STE, and PTE make it an unused area.
This occurs when a memory access that violates ring protection is performed, etc. The cause of EIT occurrence and detailed information are distinguished by the information loaded on the stack at ATRETR. Bus Access Exception (BAE)
) Occurs when there is no response from the bus within a certain period of time during instruction or operand access, and memory access cannot be performed. This is a so-called bus error. Odd address jump exception (OAJE) Odd Add
Ress Jump Exception (OAJE
) Occurs when the branch destination address is an odd number and is left blank in a branch instruction. This exception applies to instructions that directly specify the jump destination as an operand (JMP, Ac1, etc.), the return address from the stack, etc.
Instructions to obtain (RTS, EXITD, RRNG, REIT
), and JRNG instructions, when EIT processing starts.
does not occur. If the new PC is an odd number when starting the EIT process
will result in a system exception (SEE). [JRNG. EIT is currently adjusting detailed specifications] [Instruction, operation related] Privileged Instruction Violation Exception (PIVE) Prtvileged In5truction Vi
olation Exception (PIVE) When an attempt is made to execute a privileged instruction from a source other than ringo.
Occur. <<Ll>>Function Exception (LIE)
E) <<Ll>> function is not implemented.
This occurs when the processor attempts to execute the function of KukuLl>>. If the processor implements <<l l>>, this
The exception does not occur, and the vector number for this EIT becomes reserved. Reserved Instruction Exception (RIE)
ption (RIE) Occurs when an attempt is made to execute an instruction or addressing mode bit pattern that is not currently allocated. This is an exception to so-called undefined instructions. If a size of 64 bits is specified in ``device of the present invention'' 32 and the P bit is set to 1, an attempt is made to execute an unimplemented <<L2>> instruction.
This also includes undefined and unimplemented options. This also includes the use of an addressing mode that is prohibited by an instruction (such as immediate specification in a JMP instruction) or the use of an additional mode with an unimplemented number of stages. Reserved Function Exception (RFE)
This occurs when an attempt is made to use a function reserved for future expansion other than the on (RFE) instruction or addressing mode bit pattern. For example, regarding psw, XA and reserved (
If you write 1 to the bit '-'), the SMRNG
Enter a reserved value (SM, RNG=OO1, etc.) in the field.
If written, the non-privileged instructions LDPSB, LDPSMCm, TPsM and PSB (7
) reserved ('1 was written to one bit.
A reservation function exception (RFC) occurs in such cases. In addition, there are other unimplemented regulations.
An example of a reservation function is also used when attempting to access a control register or when imask≧16 is specified with a WAIT instruction.
outside (RFE) occurs. In addition, in the "device of the present invention", an instruction that can be determined to be an error based only on the instruction bit pattern (including addressing mode and size specification) is called a reserved instruction exception (RIE), and an error is determined based on the instruction bit pattern (including addressing mode and size specification).
Therefore, an exception whose status changes as to whether it is an error or not is called a reserved function exception (RFC). Co-processor instruction exception (CIE)
Exception (CIE) Occurs when an attempt is made to execute an instruction allocated for a coprocessor when no coprocessor is connected. Coprocessor Command Exception (CCE)
ption (CCE) Occurs when an error occurs in the interface with the coprocessor. Co-processor execution exception (CEE)
ception Occurs when an error occurs in the execution of an instruction by the coprocessor. Illegal 0perand Exception (IOE)
(IOE) Occurs when an unreasonable operand is specified. Widt of 32 (64) bits or more with fixed length pit field instruction
This includes the case where h is specified. Jumps to odd addresses and division by zero are semantically considered to be part of illegal operand exceptions, but they are classified as different exceptions because they have special meanings. In addition, as countermeasures when the operand of an instruction is invalid in the "apparatus of the present invention", in addition to cases where an invalid operand exception or division-by-zero exception is used, there are also cases where no check is performed (the upper and lower limit values of the instruction are set in CH). cases where the command is executed as is with appropriate interpretation (such as when count is large in a shift command), etc.
There is. On the other hand, if the result of executing the instruction is invalid (such as overflow), the EIT is not activated. In this case, if you set VJIag and end the instruction (many cases such as ADD, NOV, etc.), do nothing in particular.
Cases where there is no (such as overflow in UNPKss),
and so on. Decimal Illegal Operand Exception (DDE) Decimal Illegal 0Perand E
xceptton (DDE) Occurs when data other than 0 to 9 is specified as an operand in a signed decimal operation instruction. Although this exception is also semantically part of the illegal operand exception (IOC), it is classified as a separate exception.
has been done. Reserved 5tack Format Exc
eption (RSFE) When returning from EIT by REIT command, EIT
The number indicating the format of the stack frame (FORMAT) is the REIT instruction.
Occurs when the item cannot be processed. Ring Transition Violation Exception (RTVE)
Exception (RTVE) Occurs when an illegal ring transition is attempted, such as when an attempt is made to move to an outer ring using a JRNG command or when an attempt is made to move to an inner ring using an RRNG command. Additionally, the page containing JRNGVTE that should be referenced by the JRNG command was an unused area.
address translation exception (A) instead of ring transition violation exception (RTVE).
TRE) unused area reference error occurs. Zero Divide Exception (ZDE)
E) Occurs when division by 0 is performed. [Debug] Debug Exception (DBE) Debug Exception (DBE) Debug
Occurs in connection with. Specifically, this is an exception for realizing single-step execution of instructions and breakpoints, and the detailed specifications are <<LV>>. [Trap command unconditional trap instruction (TRAPA) TRAP^In5truction Generated by the TRAPA instruction. TRAPA's EIT vector is TRAPA's operan
There are 16 types available corresponding to the different vectors. Conditional Trap Instruction (TRAP) Conditional TRAP In5truct
Generated by the ionTRAP instruction. [DCE, DI] Delayed Interrupt (DI) (old) D Lugis
The 01 field in the data has a smaller value than the I MAS field in the 15w.
Occurs when This EIT is useful for processing asynchronous events independent of context. The EIT vector for D1 processing is 1 for each interrupt priority.
Five types are available. This EIT is issued by executing an instruction such as a REIT instruction.
Although it is an exception in that it occurs, it is an interrupt in the sense that it is activated regardless of the context in which it is being executed at the time. In other words, it is something between an exception and an interrupt. (PS battle including IMAsK field)
! It is context-dependent, but only fields in IM^S are context-independent.
It is usually operated as follows. ) See later chapters for details. Delayed Context Exception (DCE)
(DCE) C5W register (or DCE register
) is the SMRNG field in PSv.
Occurs when the value becomes smaller than the field. This exception is useful for handling various context-dependent asynchronous events (such as completion of human output). See later chapters for details. [Others] Reset Interrupt (R1) Reset Interrupt (R1) From outside
Generated by a reset signal. System Error Exception (SEE)
EE) Occurs when a fatal error occurs during EIT processing. [Interrupt] External Interrupt (El) External Interrupt (El)
Generated by hardware signals from. The EIT vector is specified externally. Generally, checking for external interrupts is performed at the end of each instruction. However, in the case of the device of the present invention, there are high-performance instructions (arbitrary length bit field instructions, string instructions, QSCH instructions) whose execution time has no upper limit. These instructions are designed to accept external interrupts even during execution of the instructions. Fixed Vector External Interrupt (FVEI) Fixed V
ector External Interrupt (
FVEI) Generated by an external hardware signal. One EIT vector is determined for each priority. This is a so-called autovector interrupt. Of the above EITs, reservation exceptions, fraud exceptions, and violation exceptions are
The distinction is based on the following idea. Reservation xx× Exception may be resolved by expanding the function.
With future feature enhancements, this may no longer be an exception. There may be differences in implementation between manufacturers. Illegal xxx Exceptions that are semantically clearly errors Unlike reserved exceptions, they remain permanent exceptions even if future functionality is expanded. There are no differences in implementation between manufacturers. XX×Violation Execution is restricted from the perspective of exception ring protection.
O5, system configuration exceptions, and multiple classifications.
Exceptions that apply A9-2. When the EIT operation processor detects the EIT, it performs the following steps.
and performs EIT processing. However, the reset interrupt (
R1), system error exception (SEE), see here.
It behaves differently. In addition, the following explanation is “the present invention”.
"Apparatus" 32, and "Apparatus of the present invention" 64
There is a possibility that the parameters etc. will be different. (El) The vector number generation processor processes the vector number according to the EIT.
generated inside the processor. However, in the case of external interrupt El
is an EIT base from outside the processor (peripheral LSI, etc.).
Get your vector number. (R2) EITVTE (7) Read/write Mi In the “device of the present invention,” the processing hardware for each EIT is
Pair of the head address of the driver and the vector number of the EIT
The table showing the response is called the εIT vector table (EITVT).
call. Also, set one entry in that table to EITV
It's called TE. EITVTE of "device of the present invention" is EI
It is set to 8 bytes considering the flexibility and expandability of T processing.
Just the start address (PC) of the EIT processing handler
It is not possible to set some fields of PSW.
can. Therefore, EITVTE is based on PC+PSW.
The structure is as follows. The format of EITVTE is
It is as shown in Fig. 353. VS (Vector SM): Protein after EIT treatment
However, the vS does not directly become the SM after EIT processing. Details later. VX (Vector XA): XA current after EIT processing
Currently reserved to 0 (ignored in case of violation) VAT (Vector AT): AT after EIT processing
VD (Vector DB): DOV after EIT processing
IMASK (Vector IMASK): EIT processing
However, VIMASK R1 does not become IMAs after EIT processing. Details later. VPC (Vector PC): PC after EIT processing I: Reserved to '20 (at the time of violation)
(Ignored) Reserved to 0 (System error exception in case of violation) The processor uses the EIT vector number generated by (El)
According to (EIT hector number) X 8 + EITVTB thing
Reads the EITVTE at the physical address. (E3) Update PSW Based on the read EITVTE, change the PSV as follows.
Update. [Command for other than external interrupts (VSy old SM) ==> New SM stack point
Inter selection. If a stack pointer other than SPI was used before the EIT occurred, VS selects the stack pointer (spo or 5PI) to be used in the EIT processing handler. If SP+ was already in use before the EIT occurred, use SPI as is in the EIT processing handler, regardless of vs. The reason for this specification is to take into consideration the case where EITs are nested. Old RNG ==>New PRNG 00 ==>New RNG The EIT processing handler is always executed in ring 0. Note that since EITVTE has unused bits, in the future it will be possible to specify that EIT enter a ring other than ring 0. VX ==> New XA Currently fixed to 0. VAT ==> New AT During execution of the EIT processing handler, it is possible to switch between the presence and absence of AT5 address conversion. VD ==> New 0B During execution of the EIT processing handler, the debugging environment can be switched. min (VIMASK, mouth opening ASK) ==> Shinkai A
Even in the case of an EIT caused by an exception interrupt or an internal interrupt, the group ASK can be manipulated by EIT processing. By using this function, external interrupts can be prohibited at the same time as EIT processing begins. Therefore, this function is effective when it is desired to perform some processing (for example, transfer of a stack frame generated by EIT) inseparably from EIT processing. [In case of external interrupt, conn+in (VS, old SM) ==> new SM old RNG
==>New PRNG 00 ==>New RNG VX ==>New XA VAT ==) New AT VD ==>New DB Iffin (2 external interrupt
Priority)==>In Shinkai As, only this part is different from the case other than external interrupts. This function allows multiple interrupts with low priority to be prohibited. Furthermore, due to the interrupt masking function, the following relationship should be established between the priority of an external interrupt that occurs and the old IMASK. (E4) EIT generation for saving processor information to stack
Regarding the previous old PC, old PSW, and the EIT that occurred
Various information (EITNF - EIT vector and stack)
(including formatting, etc.) to the stack. this
The stack used for evacuation is the new SM and new RNG (=O
This is the stack selected by O). generated at this time
The resulting stack frame is as shown in Figure 364. Of these, EITINF is generated by the generated EIT.
format of the stack frame (FORMAT
), EIT type (TYPE), EIT vector number
Information such as the number (VECTOR) is packed into 32 bits.
It is. The presence or absence of additional information and its contents depend on the type of EIT.
That's different. In the REIT instruction, FO in EITINF
By looking at RMAT, you can check whether there is additional information and its format.
- To know the mat and return to the original instruction sequence before EIT occurred.
Get the information you want. In addition, the E generated when the device of the present invention becomes 64
The IT stack frame was 10 ng words on an old PC.
Old PSW and EITINF are combined to form l long word.
It is planned that the structure will be as follows. The reason we placed EITINF adjacent to PS Yuko was because of the
In order to maintain the alignment in the device of the present invention”64,
It's a good thing. I also put PS%Il on the top of the stack
In the future, the “device of the present invention” 64 will be a 32-bit container.
Even when text and 64-bit contexts are mixed.
, the XA bit in the P cost saved in the stack is read.
This is to make it possible to (E5) Start the EIT processing handler Transfer the VPC to the PC and start the EIT processing handler
. Note that the EIT generated during instruction pre-fetch is
EIT processing continues until the instruction you are trying to access is needed.
be delayed. On the other hand, R placed at the end of the EIT processing handler
With the EIT instruction, no matter which instruction is performed, even if the following processing is performed,
Return to line. (R1) Read from the stack Read the old PSW and EITINF from the stack. reading
If the XA bit in the loaded PSW is O, the EIT is
The context in which it occurred (task or process) is 32 bits
As you can see that it was in the context of
Then read the old PC from the stack in 32-bit width. Na
Oh, in "device of the present invention" 32, all the contexts are
This is a 32-bit context. Furthermore, additional information is provided by FORMAT in EITINF.
Determine the presence or absence of the
Load. For additional information, EXPC. 101NF, ERADDR, ERDATA, SPl etc.
However, its detailed meaning is implementation-dependent.
. FORMAT has a value that is not supported by the processor (E
(a value that should not occur in IT), the reserved space is
This results in a tack format exception (R5FE). (R2) The old PSW read from the recovery stack of the PS attack restores the entire PSW.
Fields (SMRNG, XA, AT, DB, IMAs
K. P.S.M. PSB) is restored to the value before the EIT occurred. At this time, the old P.
If the S shift 1 reserved value is included,
Generates a reservation function exception (RFE). (R3) Re-execution of store buffer (implementation dependent)
) Depending on the value of FORMAT and additional information, the REIT command
The error caused by the store buffer that generated the previous EIT is
The light cycle may be re-executed. At this time,
address and data information necessary to execute the light cycle.
Then, ERADD which was in the additional information on the stack
R and ERDATA are used. For details, please refer to the EIT tab.
See type description section. Note that there is a function to re-execute only the store buffer.
Whether it is true or not depends on the implementation issues of the processor.
That's the issue. In other words, the REIT instruction's store buffer
When EIT processing is created assuming an execution function
Of course, it is necessary to support it with REIT instructions.
However, even if there is no re-execution function for only the store buffer, conflicts may occur.
If EIT processing is possible, it can be done using the REIT command.
There is no need to support this. From a programmer's perspective, EIT processing and REIT instructions
The processing by REIT corresponds properly, and the
When returning from EIT processing, the instruction that generated the EIT
It is sufficient that the columns can continue execution without any conflicts. This machine
There is a direct relationship between the functionality and the level of functionality as a processor.
Not related. (R4) Return step to the instruction sequence that was being executed when EIT was detected
Return to the old PCI-PC loaded from the tack and install the PC.
Resume execution from the indicated instruction. At this time, depending on the TYPE field in EITINF
, then the receiver is changing the type of EIT attached.
. This function is used to process multiple EITs without contradiction.
In addition, the single-step operation of instructions can be emulated.
used to ensure accuracy, including execution by
. Note that the VECTOR field of EITINF is RE
Not specifically used in IT instructions. Despite this, VEC
TOR is included in EITINF because of EIT processing.
This is to provide information to the handler program.
Ru. After the EIT processing handler finishes,
The location of the PC and the priority of EIT processing when restarting execution of
If you look at it and classify it, it will look like this: This classification is E
Corresponds directly to the value of the TYPE field of ITINF.
Ru. [Instruction interrupt type EIT (TYPE=O, PC undefined)]
When an EIT occurs, it is immediately detected and the EIT
Start processing. If this EIT occurs, EIT will be generated.
It is not possible to return to the previous command sequence. This applies to R1 and SEE. [Instruction completion type EIT (TYPE=1~3.PC next instruction
)] When this EIT occurs, the instruction processing being executed at that time
is detected and enters EIT processing after it has completed. Generally, for this EIT,
Execute the REIT instruction at the end of the EIT processing handler.
By doing so, the next instruction after the instruction being executed when εIT occurred
Instruction execution can be resumed from the instruction. In addition, the distinction between TYPE=1 to 3 is based on priority etc.
It depends on the relationship. This applies to TRAP and TRAPA. These include DBE, DI, and DCE. [Instruction re-execution type EIT (TYPE=4.PC current instruction)
] When this EIT occurs, the state of the processor and memory changes.
is the time before the execution of the instruction being processed when the EIT occurs
returned to the point. Generally, the EIT processing handle for this EIT is
By executing the REIT instruction at the end of the driver, the EI
Execution of instructions can be resumed from the instruction that was being executed when T occurred. This applies to: POE, ATRE, BAE, RIE, RFE, PIVE
, IOE, etc. Instruction completion type EIT is related to the previously executed instruction.
EIT, an instruction re-execution type EIT, is an instruction re-execution type EIT that
This is an EIT related to instructions. Therefore, multiple EITs
If these occur at the same time, - generally an instruction completion type EIT
need to be processed first. In addition, instruction interrupt type EIT
is a highly important EIT, and if it is detected,
It is meaningless to process other EITs. However,
Therefore, the instruction interrupt type EIT and other EIT occur at the same time.
In this case, it is necessary to process the instruction interrupt type EIT first.
be. After all, priority when multiple EITs occur at the same time
EIT
INF TYPE = 0 to 4 is the EIT priority as is.
will represent. The correspondence between EIT (7) type and TYPE is R1, TRA
There are some things that are clearly determined, such as P(7), but there are
The extent depends on the implementation. therefore,
When analyzing EIT factors using software, it is possible to
Only refer to or rewrite the TYPE field
It's better not to. For example, for a page not found exception (POE), this is the instruction
It is a re-execution type EIT and is usually TYPE=4.
It is. However, I use a store buffer for writing memory.
In the processor of the implementation used,
In the last write cycle of the instruction (using store buffer)
If a POE occurs, this entire instruction must be restarted from the beginning.
Redo only the last write cycle without executing it.
If so, there will be no processing inconsistency. Therefore, such a case
If the POE is an instruction completion type EIT, an error will occur.
Processing of the last write cycle is performed in the REIT instruction.
There are cases where it happens. In this case, even in POE, TYP
E=1. In addition, the PC stacked in the EIT process is
It becomes the next command instead of a raw command. As long as you follow the instruction re-execution method faithfully, you will not encounter errors during instruction execution.
If an error occurs, return to the state before executing the instruction and execute TY.
The principle is to start the EIT with PE=4. death
However, when the command is almost finished, an error occurs.
If this occurs, it is assumed that the command is finished and T
Start the EIT with YPE=1 and perform the remaining processing (store backup).
The financial write cycle) will be left to REIT instructions.
Implementation is also possible. If you choose to implement this way, the PO
There are two types of E, 1 and 4. In this case, T.Y.
The processing required by the REIT instruction varies depending on the PE.
It's going to change, and REIT orders can respond to that.
must be in the correct position. This method allows errors that occur during the last write cycle of an instruction to
The entire instruction is re-executed for EIT caused by error.
instead of rerunning only the last write cycle.
It's in shape. In other words, it is a type of continuous instruction execution method. this place
This corresponds to internal information that is saved for continued instruction execution.
is saved on the stack as additional information of the EIT.
ERADDR and ERDATA. Note that this occurs during a write cycle using a store buffer.
Immediately after the instruction that wrote the EIT
EIT processing may not always be initiated. A9-4. EIT... format EIT detection
Along with this, the information necessary for EIT processing is retreated to the stack.
avoided. The stack format is as shown in Figure 355.
It is. PS: The PS format number (8b) at the time when the EIT was detected.
it) Type 6: EIT type (8bit) Vect
or: EIT vector number (9 bits) PC: Execution restart address after returning from EIT handler Among these, "other information" is the stack format of each EIT.
It varies depending on the mat number, and in order to analyze the factors of EIT.
information for returning from the EIT handler.
It is rare. The stack format number corresponds to the stack format number.
The format is shown in FIG. PC: Execute after returning from EIT with REIT command.
Start address of the instruction EXPC: P of the instruction being executed when the EIT was detected
Co 101NF: Information related to input/output Error
Addr: Addr of the bus cycle that generated the EIT.
Dress Error Data: Bussa that caused EIT
cycle data (write only) SPI: SPI value format at the time of EIT detection
- Mat number 0: Reserved instruction exception, reserved function exception, reserved stack format
exception, ring transition violation exception, <<Ll>> instruction exception,
Coprocessor instruction exception, privileged instruction violation exception, illegal opera
Examples of command exceptions, fixed vector external interrupts, and delayed interrupts
outside, external interrupt. Format number 1: Bus access exception, address translation exception. Format number 2: Debug exception, odd address jump exception, division by zero example
Outside, conditional trap instruction, trap instruction. Format number 3: D[lG external interrupt, DOG) wrap instruction, DBG data
Bag exception, DOG access violation exception (i.e. DOG
(Exclusively for EIT) EXPC was introduced for the following purposes.・Provision of error analysis information - EI of TYPE=l when writing to the door buffer
If T occurs, the instruction that wrote the
EXPC refers to the ordinance. The PC has moved on. In one debug exception, PC points to the next instruction and EXPC
refers to the previous command. Therefore, for example,
A debug exception is now triggered when the dump instruction is executed.
, the PC value before the jump is changed to PC by EXPC.
You can find out the PC value after the jump. - Processing of multiple EITs - In the case of EITs such as TRAPA with TYPE = 1,
EXPC information may be required in the processing handler.
There is no such thing. However, EIT with TYPE=1 (TRAPA) and TYPE
= 2 EITs (debug exceptions, etc.) occur at the same time.
In case of EIT with TYPE=1, TYPE=2
You must save the EXPC you will use. TRAPA also has a specification that saves EXPC.
This is why. In this case, REIT instruction execution for TRAPA processing
The latter EXPC does not refer to the beginning of the REIT instruction.
and restore the old EXPC value that was popped from the stack.
It has to be something like that. That is, REI
Immediately after activating the debug exception that was immediately after the T instruction.
Fires a debug exception that was later bent.
EXPC saved to the stack is
It does not refer to the TRAPA Order, but rather to the TRAPA Order.
Must be. (This example uses TRAPA's EI
It is assumed that debug exceptions are masked in TVTE.
It is. ) Also, the configuration of l0INF is as shown in Figure 357.
Ru. =: reserved at 10' Wl: Write retry in REIT command
It has meaning in EIT (TYPE=1) for instruction memory access. 1 = 0 Write retry required 1 = 1 Write retry required MEL: Address conversion exception occurrence position 0000
No error 0001 Errors related to access rights 0010 to 1110 (reserved) 1111
Access error related to 110 area MEC: Error code for memory access related error 0000 No error 0001 Unused area reference error 0010 (reserved) 0011
(reserved)0100 rea
Ring protection violation error related to d 0101 Ring protection violation error related to rite 0110 Ring protection related to execute
Violation error 0111 (reserved) 1000
Unable to access the bus when reading 1001 Unable to access the bus when writing 1010 (reserved) 1011
(reserved) 1100 (reserved)
served) Memory indirect addressing for the 1101110 area 1110 Execute for the 110 area Crosses the 170 area and an area other than 170 when writing Crosses the I10 area and an area other than I10 when writing: Bus cycle type RW = Own RW = 1 read BL = Bus locked state BL = 0 Not bus locked BL = 1 Bus locked PA: Space specification PA = O (reserved)...Logical space (with address translation) PA = 1 Physical space (no address translation) AT: Access of bus cycle in which EIT occurred.
Stipe AT=000 Data AT=OO1 Program AT=010 Interrupt vector shift etch
0 AT=011~111 (reserved)512
: Data size when performing write retry 0000 (reserved) 0001
1 byte 0010 2 bytes 0011 3 bytes 0100 4 bytes 0101-1111 (reserved) Reset
Regarding interrupts and DOG mode EIT (No. 0 to 5)
The EIT table entry consists of SPI value and PC value.
be done. EIT table entries for other EITs
The bird consists of PS%l111II and PC value. The initial value at reset of EITVB is 'FFFFFFOO
O' is 5, so the reset interrupt uses the physical address 'FF'.
Entry (SP l, PC) from FFFOO19
fetched. 9-6. EIT - During EIT processing (from EIT generation to new PS after saving status)
(up to the setting of
If an error occurs, a system error exception (SEE
). Possibility of system error exception (SEE)
The reason for this is the bus access associated with reading EITVTE.
Stack exceptions, stack pages associated with saving the old PC and old PSW.
Such exceptions include address-missing exceptions and address translation exceptions. Also, E.I.
LS8 of the word containing TVTE's PC was Jj.
In this case, a system error exception (5EE) will occur. A system error exception (SEE) is generated by SPI. Deciding whether to use either SPO stack
is not relevant, a page fault exception occurs in the SPO stack.
If the problem occurs, you can switch to the SPI stack or
on the stack specified by EITVTE of the page fault exception.
(switch) and continue EIT processing.
It's not working. On the other hand, since ring transition by JRNG is not EIT,
If a page-out-of-page exception occurs during JRNG processing,
The stack specified by EITVTE of the page fault exception is
to be used during EIT processing of a page fault exception.
Ru. In this regard, TRAPA and E
System error in JRNG not included during IT processing
Please note that the steps to get to the point are different.
is necessary. (Refer to Figure 359) In any case, when creating O5, specify by SPI.
The stack area specified is memory resident and is controlled by SPO.
The specified stack area may also be used in special cases.
It is necessary to program it so that it is memory resident unless
There is. Moromi j Koso 1 upper ■ Except for EIT with TYP = 0, detection of EIT and response
This processing is performed at the end of each instruction. therefore,
In some cases, multiple EITs may be used at an instruction break.
They may be detected at the same time. This is called multiple EIT.
Bu. Here, we will explain the processing order of multiple EIT.
. For example, TRAPA with TYP=O and outside of TYP=3
If two interrupts (El) occur at the same time, first the TRA
EIT processing is in progress for PA, and continues for El.
EIT processing is performed. As a result, PC, PS
The state of W and the stack is as shown in FIG. 360. Therefore, in this example, after EIT processing is completed, first
The processing handler of l is executed. El's processing handler
After the end, the REIT instruction placed at the end
, - Move to a shallower level TRAPA processing handler.
Ru. In other words, the TRAPA processing handler with higher priority
This means that it will be postponed. However, in the above example, TRAPA's EIT processing is executed first.
Therefore, change the PS enemy and mask El.
be able to. In other words, if you specify the priority of VIMASK < El in TRAPA's EITVTE, TRAPA's EIT
IMASK was changed during processing and EIT processing for El
The training period will no longer be held. In this case, the TRAPA treatment
The processing handler is executed. And the last R in the handler
When IMASK returns to its original value with the EIT command, the mask
El, which had been previously installed, will now be activated. In this way, EIT with high priority (low TYPE)
EI masked by PSW updates during processing
T includes OBE, εl, DI, DCE EIT,
There are TYP=2 to 30 EIT. Conversely, mass
EIT that can hold processing requests (EIT that can hold processing requests)
IT) has a low priority of TYP=2-3.
That's it. On the other hand, in the case of TRAPA, the EIT processing request
There are no registers or hardware to hold the
do not have. Since the PC is also proceeding to the next command, the TRAPA command is
Nor can the command be re-executed. Therefore, TRAP
If the 81-piece processing is not performed immediately after executing the A command, EIT processing will not be possible.
Processing requests are lost. TYP TRAPA = 1
This is why it is given a high priority. Also, the EIT with TYP=4 is an EIT for instruction re-execution.
Therefore, try again after processing other EITs.
If the same instruction is executed, the same EIT will occur again. life
The instruction execution type (TYP=4) EIT has the lowest priority.
This is why. Therefore, in the case of multiple EIT, 61 of TYP=4
There is no need to process the dust. TYP=4 EIT activation required
The demand for EITs occurs simultaneously and detects EITs with TYP = 1 to 3.
It will be canceled without warning. The receipt is placed immediately after the REIT instruction is executed. Different from EIT
It has become. With the REIT instruction, pop from the stack
REIT by TYPE in EITINF
I am adjusting the EIT, which is placed immediately after the command is completed. R.E.
The type of EIT that is accepted after the execution of the IT command is
As shown in Figure 361. Among these, TYPE=2 is Depack exception (DBE).
Ru. In other words, the hand during EIT processing for depack exception
Immediately after executing the REIT instruction of
It means that you can't do it. TYPE=2 depending on whether it is immediately after executing the REIT instruction.
The difference in the handling of depack exceptions is for each instruction.
This is for single-step execution. In this case,
Depack again immediately after REIT instruction for pack exception
If the exception was caused, the execution of the program to be depacked may be
The line does not progress at all, only depack exceptions occur continuously
The situation ends up being like this. Therefore, the above mechanism
Due to the system, a depack exception is generated immediately after the REIT instruction.
Instead, a depack exception will be generated after executing one instruction.
This is what they are doing. Generally, when single-stepping, the next command is
Either execute the instruction or raise a depack exception.
It is necessary to have a partial state. rThis invention device", this
The two states are whether it is immediately after executing the REIT instruction or not.
Displayed by the combination of internal status and EIT TYPE.
It is thought that this is occurring. Note that single-step execution based on this idea is
Also applies when other EITs occur at the same time as a block exception.
can. Instructions in the reserved instruction exception (RIE) EIT processing handler
For emulation, use other IEIT
Unlike the processing handler for (such as page not available),
Do not trigger a depack exception before or after the RIE processing handler.
Must be. For example, if after single step execution, normal instruction → debug exception → page fault exception, next
It is necessary to execute a normal instruction, but normal instruction → debug exception → reserved instruction exception (emulator)
), the next step is to trigger a depack exception. This is the page
The missing exception is useful for debuggers and programs to be depacked.
Emulation is completely invisible, whereas emulation
For the program targeted by the debugger, the
This is because it is supposed to be seen as "execution." In the case of the "device of the present invention", during EIT processing of reserved instruction exception
Adjusting the TYPE of EITINF in the handler
The above is possible. kg-8, r B old A9-8-1.01 bereguyon "device of the present invention" old (Delayed Interru
pt), the old field in the old register is I in the PSW.
Occurs when the value becomes smaller than the MASK field.
This is an EIT. This feature is context independent
The asynchronous event that occurred is treated as bending, and only the processing request is processed.
When registering, serializing the processing order, etc.
It is valid. The EIT vector for 01 processing is 1 for each interrupt priority.
Five types are available. IMAS value and its flag
The relationship between the change and the external interrupts allowed at that time is determined by
It looks like Figure 362. I need to check whether to start Dl.
is when the group ASK is large or when Dl is small.
That's when it happened. Therefore, this applies to LDCsrc, @psv; ps- is in the control space.
PSW address LDCsrc, @imask; imask is control empty
The address of imask in between is DCsrc, @DI; DI is 0 in the control space.
1 address EIT AIT. Of these, other than LDCsrd and @di
, the old field before executing these instructions
The value becomes the level (priority) of the activated Dl. D
The level of l is the vector of EITs activated as Dl.
Affects the number. Also, by LDC6rd, @di
If 01 is activated, the DI feed before LDC execution is
newly set by the LDC, not the value of
The value of D1 field (i.e. 5cr) is activated Dl
level. Note that when EIT starts (external interrupt, exception, TRAP)
There are also changes in IMASK (including Bede),
In this case, the value of group ASK will not become large.
, the old one will not start. If 01 is activated, the D1 field is 1111 (
(without request). In addition, IMAs
The external assignment with priority is the level of the accepted DI.
The same change occurs as if the entry had occurred. In other words, ll1in (01 level accepted by VIMAS)
)==>New IMAsK. υj Him 1 country uL overthrow [Example: Delayed dispatch of the device of the present invention] With the device of the present invention
is a system interrupt issued from within an external interrupt handler.
When the status of the ready queue changes due to mucall
, and associated dispatching (such as register swapping).
etc.) are delayed until the interrupt handler returns. This is to avoid conflicts caused by multiple interrupts. This is realized by the function of Dl. The dish moxibustion system call is V in TRAPA's EITVIE.
In IMASK, =14 is specified for VIMAS. This is the end of system call processing due to the D1 function.
This is to perform dispatching.・The part that handles dispatching is handled by D114.
It will be started.・Ilj indicates the running state, and °1' indicates that the execution has been interrupted.
represents a state. -9-Mukor If you use the function 01 shown in Figure 363, the delayed dispatch of the device of the present invention can be
Processing can be accomplished quickly. In addition,
If multiple interrupts or nested system calls do not occur
can also be easily dealt with. DCE (Delayed ontext Ex) of the present invention
ception) is the DEC register (or C5W register).
The value became smaller than the DCE field in
This is an EIT that occurs when This a-noh is a context
Handling asynchronous events related to events (such as completion of input/output)
You can register only processing requests as vending, or
This is useful when serializing the order.
Ru. DCE file in DEC register (or C5W register)
The field for entering the DCE request is
This is a field for entering a DCE request. [) The EC register (or C5v register) is
Each context has a unique register, so
It is possible to provide separate DCE requests. Since the DCE is attached to each context, the
Processing an external interrupt independent of the context (SM=
00 case), the DCE is not activated. Also, the higher priority DCE request in other context A
Even if a request is issued, the dispatch is not made to that context A.
The DCE of context A will not be activated unless the The DCE request issued in another context 8 is lower than that.
Even if it has a higher priority, context B will be dispatched first.
If patched, context 8 DCE will start first.
It will be done. The value of the DCE field and the DCE activated at that time.
The relationship is as shown in Figure 365. In either case, when SMRNG > DCE
DCE is started. (reserved), the actual DC
Same operation as E=000. However, for future expansion
Therefore, do not program using this function.
I can't. There is a large possibility that DCE will be activated due to SMRNG.
or when the value of the DCE field becomes small.
That's when it happened. Therefore, the following that fall under this condition:
In the command, check whether to start DCE.
There is a need to. LDCsrc, @psw; ps%, I is control
Address the PSW in space DCsrc, @smrng; smrng is the control
Address of SMRNG in control space LDCsrc, @dce; dce is control space
Address of DCE inside LDCsrc, @csw; cs sail control space
Address of C5w inside; however, C5%lI may not be implemented. REIT RRNG Furthermore, when EIT starts (external interrupt, exception, TRAP)
) and when executing JRNG, SMRNG also changes.
However, in the case of EIT and J RNG, SMRNG
Since the value of is never large, DCE is activated.
Never. DCE itself is activated as one EIT process. When the DCE EIT is activated, the DCE field is
11! (unrequested). SMRNG Fi
The field is the same as general EIT processing.
according to the EITVTE assigned to the vector number.
Make a change. Because DCE processes each context
, in the activated EIT processing handler, instead of SPl
It is common to use spo. Establishment of EITVTE
Depending on the settings, SM=0 in DCE processing (using SPI)
However, this is an operational issue.
No particular checks are performed on the hardware. DCE is activated by REIT instruction or RRNG instruction.
In this case, the process of actually starting the DCE is performed by REIT or
It may be performed at the same time as NG, but according to the operation specifications,
Start EIT after REIT or RRNG execution is completed
It becomes like this. For example, when DCE=110
When you return from ringl to ring3 in RRNG, there
DCE is activated and enters r i ngO. At this time, P
RNG is not ringl but ring3.
Must be. Comparing DCE and Dl and external interrupts
Then, the result will be as shown in Fig. 366. In cases such as notification of input/output completion, an external interrupt handler is used.
Start the corresponding context OCE within the context
Sometimes it goes like this. Simulating DCE with software
Although it is not impossible, it is generally
Because it is necessary to change the installed PSW and PC,
It's quite a hassle. The interrupted Progeralom is
Transfer all mats to the list of programs that have been created.
This is because you must know it. A9-9-2. DCE's DCE becomes more effective if it can be nested multiple times.
Rinaru. Therefore, if multiple DCE requests occur,
, the question is what kind of processing to do. In Himuro equipment, nest processing (request queuing) is
The plan is to use software. (Example of queuing processing of multiple DCE requests)
When setting E request] if (DCE=111) then New DCE request ==> DCE field/ *DC
This is all E request*/lse The newly generated DCE request is sent to DCE configured in ring order.
ndif placed in the CE request queue (during DCE processing) / *When starting DCE, 111 == depending on the hardware
> becomes DCE */ if (DCE request queue is not empty) thenDC
Set the next entry in the E-request queue to the DCE field.
ndif A9-9-3. DCE 1 [Example: Starting an input/output management program] The completion of input/output is notified by an external interrupt, and the
Therefore, the input/output management unit (ringl) of process A
It is assumed that the 36th
(See Figure 7). φ′bi represents the running state9. ′ indicates that execution has been interrupted.
represents the state of affairs. ■The start address is specified for each process (context).
However, in reality, DCE's EIT processing vector
Since the torque is common between processes, each wrestling
It is necessary to parse the DCE request table and jump to it.
There is a point. In the case of this diagram, when an external interrupt occurs,
This means that process A was being executed. of other processes
If an external interrupt of human output occurs during execution, rin
The startup of the input/output management section in g1 is the disk drive to process A.
Delayed until patch is done.・Record 10. The life of zero
[Notes on Instructions] Instruction bit patterns are expressed as follows. −゛ Reserved to 0 (Exception occurs when violation occurs) +°
reserved to l (Exception occurs when violation occurs) This bit
If the bit is 0 (1), the process is successful and this bit is
If the bit is 1 (O), a reserved instruction exception (RIE) is generated.
Ru.゛Par reserved to 0 (ignored even in case of violation),,,
Vero, 87°*9 'It' reserved to 1 (ignored even in case of violation)
The user manual includes this bit for future expansion.
Specify that the cut should be set to 0 (1). in fact,
It will not work whether this bit is 0 (1) or 1 (0).
The work is the same. ``Ignore even when there is a violation'' is not a good idea due to the architecture.
Although not desirable, instruction focus pattern assignment
Therefore, it is unavoidable from the standpoint of future expandability and high-speed execution of instructions.
There are cases where ”～゛ Reserved to 0 (Guaranteed operation in case of violation)
No) °!゛ Reserved to 1 (behavior when violation occurs)
(not guaranteed) The user manual contains information about future expansions.
Therefore, specify that this bit should be set to 0 (1). In reality, normal operation is possible when this bit is 0 (1).
However, the behavior in the case of 1 (0) depends on the implementation.
exist and are different. "The behavior is not guaranteed in the event of a violation" means that the architecture
Although it is not very desirable on the
Instruction bit pattern assignment, high-speed execution of instructions
There are cases where it is unavoidable. For example, LDATE, MU
LX(7) 1st halfword <7)'! R' is attached to this
Inferred. Al0-1. bit allocation by format for bit 4
Notes on address assignment] - The device of this invention has only a few addressing modes that can be used.
Each command is quite different and needs to be checked.
There is. Allowed addresses are listed for ease of checking.
The bit pattern is divided to make it easier to distinguish between the switching modes.
prohibits certain addressing modes that
As a general rule, if the operand is
Now I can understand only half words including pelando.
There is. - In principle, the P bit is set for each operand (register directly).
specification and immediate specification (<), and implicit star
I will write about each explanation separately. instruction pattern
Inside, it is expressed as lpl or "0". However, if it can be covered by a -S type instruction, the same instruction can be used.
The P bit may not be included in the shortened form of . (P.U.S.
Only H, POP, and PUSHA are related to stack references.
) ・Indicated by LV reserved in the bit pattern
These are instruction bits that each manufacturer is free to use.
It is a cut pattern. This instruction bit pattern is similar to
For example, a user interface for interfacing with ICE.
It can be used as an instruction not to release the data. This is shown below in FIG. 368. A10-21, ・The above bit regarding life
The pattern indicated by (RIE) in the pattern is
Bits reserved for expansion
It's a pattern. When I run this instruction bit pattern
, a reserved instruction exception (RIB) occurs. In addition, unimplemented options and support
If you specify the size (including unimplemented <<L2>>),
If you specify an undefined option, the instruction focus pattern
If the ′−° part of the code is set to °l°, the instruction bit pattern
If the °÷° part of the turn is set to 0", the °p in the command
When the bits of l and I Q+ are set to l°, res
erved conditions (cccc) and termination conditions (eeee)
Even if you specify a reserved instruction exception (RIE),
Become. Currently, with exceptions such as LDATE and Ml;LX,
As a general rule, all instruction parameters for the first to fourth bytes are
Check the turn and if the pattern is different,
I'm using RIH. Cheets for the 5th and 6th bytes
Even if the pattern is different, it is not considered an error.
do not have. Among the above bit patterns, especially (RIE-X)
What is shown is that the first IW is in general addressing mode.
If you don't read up to the second IIW, you will know that it is RIE.
It is a bit pattern that is not In this case,
The second IIG (is placed after the extension of Ea. Of the bit patterns not currently used, future functions
Patterns and other methods that are planned to be implemented as the expansion progresses.
Regarding the patterns that seem to differ from the car chip in operation
should be detected particularly actively. This is that
This is to prevent mistakes when executing the instruction pattern of
Ru. Under such policies, exceptions to reservation orders (
+? The check priority of IE) is as follows. ↑High priority (those whose meaning has already been determined) Specification of undefined <<L2>> function Specification of 64-bit size (RR, MM, &JW, SS
= 11) (Highly likely to be used for instruction expansion)
) (RIE) instruction pattern specification BVPA
T NBVSCH (7) I, Xl ノ'+'PST
LB~EXITD: 1-9P of 2nd HW of G group
Bit specification (something that is rarely used for instruction expansion) LDATE~
The 11th W' of the INDEX group! R' 1!1S
TATE~Second I of old NS group (W'+W'°
+゛PSTLB -EX ITD: G (7) Group
The first 〇W'+X'(7)'+'ACB: R, SC
B: 1-1 of the second IIH of R ↓ Low priority The bit pattern to be checked now is the specification as described above.
However, from now on, reservations based on this policy will not be accepted.
The detailed specifications regarding instruction exception detection were adjusted, and some
is subject to change. In addition, I wonder how far into the command the HIT should be activated.
There is no particular provision for this. First) IW.
Even if it is obvious that the BIT will be started by
You can read up to 2HW. Also, just the opcode part is B.
When it is clear to start IT (reserved instruction exception
etc.), it is also possible to process up to the extended part of Ea. ^10-3. Open field U shown in Figure 369
vinegar.・Size relationship Of 16 bit 10 32 bit 11 64 bit ・Addressing mode competition Areg 10 etc. 16 bit relative indirect mode reception 32 bit relative indirect mode ■ Additional mode/register specification competition (special) Kano (SP) 10 abs or 0 11 PC Tsukurikijiro Nioka El<Rx>MS PXXD<d4>-゛ is reset to 0
The bit umbrella car to be saved <Rn> Q main issue XX **** R1 is the index tree
Book - 01 Book - * Principal Principal Inch Fusunashi Kimoto -t
it 2nd rate book rate RC is index xx≠0
Scaling by 0 is not available Chapter Chapter Kimoto Kasamoto Ratio Hon Kasamoto 0<d4> 4 pits
Totei 7! , 7" L/ - Sment Kasa Zero * Rate Kimoto Honmoto * Presiding 1-Of 16 He/
Door'Isla° Racement Book * Book * Kimoto * * Umbrella Book Book 1-10 32 Beats Today
Placement Umbrella Tree Book Book Zero Book Book Book 1-11 64 Heat Tey
Size specification part of spacing <d4> and djsp in MISC mode
:16. The specified part of diSρ=32 is in the same bit position
It has become. Tamaki Tamanigami POOOxxxx MISCP=0:5h0000
(RIE) 0001 (RIB) 0010 (RIB) 0011 (RIE)-aads:64 discharge 00
2SP+ (read: asp+, write: ille
gal. raw:illegal) 0101 2SP+(write:illegal,
read: asp+. r＋＊w:illegal) 0110 (RIE) 0111 (RIE) 1000 (RIB) ・ 1001 1ilads:16 1010 aads:32 ■■ Absolute addition mode 1100 Imm+(read: asp+, evri
te:illegal. rmw:illegal) 1101 a(disp:16.Rn)1110
aRn 1111 a(disp:32.Rn)0001
<Rn> Rn
5h1001 xxxx
(RIE) POIO<Rn> a(disp:
16. Rn) P-0:5hPo
ll <Rn> aRn
P=0:5hP100<R
n>a(disp:32.Rn)Plot
<d4> a (disp:4.FP) <<
L2>>PIIQ<Rn> Register relative addition mode
Pill <d4> 1i (disp:4.
SP) <<L2>>・Rei Kurumamoto 1 Kimoto Kurumamoto's putter
The extension part will not be attached when it is turned on.・Aads: 64 allocation is irregular, but 64 bit
The cut extensions probably have special internal circuitry as well.
(For example, even with the device of the present invention,
a(-disp:64.Rn) can be realized in basic mode.
Since it's Kina G Rin, it doesn't seem to be that much of a problem. insect
The relationship with the additional mode has been made uniform. If an undefined addressing mode is specified (during EA)
(including the P bit 1) is reserved instruction exception (RIE)
becomes. Specifically, in the following pattern, RIE and
Become. (Ea) (
Sh) oooo oo book*
oo oo Ningmoto 000
0 011$
00 011 Umbrella 0101 *Main Umbrella Umbrella (<<L
2>> Only when not installed) otii *Umbrella* (<<L2
>>Only when not implemented) 11*rate **Even if you specify a reserve pattern in Honkimotoka mode,
This results in a reserved instruction exception (RIE). <Rn>≠0 in M and l
In the case of 000.0001, <d4>≠0001 in D・1
,0010, P=1, XX=11
This also includes cases. At a stage with additional mode, ×2, ×4, × for PC
If you specify a scaling other than 8, the end of the
An implementation-dependent variable is used as an intermediate value after completion processing.
A fixed value is entered. It will not become an EIT. <<L2>> Undefined, specify additional mode of 5 or more stages.
Even in this case, a reserved instruction exception (RIB) occurs.
During maintenance, there is a possibility that a reservation function exception RFE will occur. 〕order
Addressing mode combinations not available due to
(JMP #imm-data, CM
P#0. Ill, etc.), reserved instruction exception CRI E
). <<L2>> Combinations that cannot be executed because they are not implemented
This also includes if specified. (This applies to
These are bit field instructions that specify registers. ) AIO-5, instruction option bit
In this case, the one described first (option value is 0.00
．． ,) is the default in the assembler. cccc Bcc, condition specification in TRAP/ccee
ee Termination condition specification for string instruction and QSCH instruction
constant ρ+Q,, P bit specification (Q3. is the required P bit
When there are multiple operands) b /F=O, /B=l (BSCIl, BVSCI
l, BVMAP, BVCPY, SCMP. 5M0V, QSCII) r/F=0. /R-1(SSCH)C=O+
/S-1 (CIIK) -CIIK, change 1
ndex value "c' d 10J, /bl (BSCI, BVSCII) -
1d1m of data/NM=0. /MRd(QS
CII)-mask 1.1p/AS=0. /S
S・1 (PTLB, PSTLB, LDATE) - PTL
B, 1pIttt of 5specific 5pace
/PT・000. /5T-001, /AT・110.
(RIE) =010~101.111(1'5TL
B, LDATE, 5TATE)xx /LS=00
．． /C3J1. (RIE) = 10.11 (LDCT
X. 5TCTX) Δ10-6.8cc command, TRAP/cc command
, (cccc) eCCC value assignment is the 370th
It will look like the figure. ^10-7. The value of 2(eeee)eeec of the termination condition
The assignment is as shown in FIG. 371. For 0000 to 0101, cccc (Bcon
Match the meaning to the bit pattern of the condition specification of the d command.
be. In particular, LTU, G[! U is 5UBX instruction etc.
If you consider the operand as unsigned data,
This is in line with the comparison result being reflected in Lflag.
be. Note that among the termination conditions of <<L2>>, two conditions are:
or. For those bound by
MJlag is used to indicate whether the process is finished or not. As a general rule, MJlag is set according to the ratio with R4.
This is the time when the comparison is completed, specifically in the case shown in Figure 372.
It is. If the condition of MJ1ag=1 is not satisfied, and
If the termination condition is other than this, the MJlag
It becomes 0. Implement the termination condition of <<L2>>
If not, it will always be MJlag・0, but in that case
However, it is said that there will be cases where MJ1ag≠0 in the future.
It is desirable to clearly state this in the manual. Al0-8. BV? lAP life five':2-)'R5's
This is an operation code that contains a value in the lower 4 bits. This is shown in FIG. 373. Δ10-9.7 Dressing mode” Operands of each instruction and prohibited addressing
The correspondence with the modes is shown in FIG. 374. For combinations of O, its addressing mode
mode is available. For the × combinations, if you try to execute them,
A reserved instruction exception (RIE) is generated.・: 1
In the explanation section of each instruction, details of high-function instructions and termination instructions are provided.
Since it is not explicitly stated about the register value at
I will give a summary explanation here. 5m0V / b, SCMP / B, BVMAP / B, B, B VVMAP / B, B, the needle of the furniture of the lehl
VCPY10TE is compatible with @-5P, etc.
The idea of processing in the form of rement and 5M0V
/F, 5SC) Due to consistency with l/R etc.
There is a concept of processing in the form of a ment. example
5NOV/B for the :ge100~H'1ff(7) area
, BC, l: When transferring data, 5NOV/B is pre-transferred.
If the specification is for decrement, the initial value of the register is l+'
200, and 5M0V/B is the post-decrement
If the specification is met, the initial value of the register will be ll'lff. [Disadvantages of post decrement: 5M0V/F and 5M0V/B, SCMP/F and SCMP
The symmetry with /B deteriorates. For example, Hゝ000000
When performing T 5NOV/B on a string occupying an area up to ff, 5M0V/B, Bt
'll'oo0000f as the initial value of the pointer if
Set f, 5NOV/B, if W, initial pointer
Need to set lI'oo0000fc as value
. [Disadvantages of pre-decrement] Compatibility with search commands such as 5SCII and B5Cl
The compatibility deteriorates. If it is 5SCH and the point after the instruction is
If we set a principle that the final value of the vector always points to the element for which the termination condition is met (the element of the search result), depending on the processing direction such as /F, /B, /R,
It will no longer be possible to change the Buri update/Bost update. Therefore, it is not possible to pre-decrement only /B. (
Actually, 5SCH,/B does not exist, but BSCH/B
In TRONCH II', [post-decrement data]
5M0V/B, SCMP/B
Make it a specification for technical decrement. Next, set the 5M0V, SCMP, and 5SC1l power termination conditions.
If the instruction is completed, update the pointer and then execute the command.
or exit the instruction before updating the pointer, or
There is a problem. [Disadvantages of terminating the instruction before updating the pointer] When terminating the instruction depending on the element size, the pointer will be updated and the pointer will move to the next element (in the case of /F, it will not be processed yet).
Since the command ends after it points to the end of the process), it does not match the specification. In other words, whether or not the pointer can be updated depends on whether the termination condition is met, which makes the specification difficult to understand and makes high-speed implementation difficult. Also, in 5SCH, after the search is successful, the next
When performing a search, specify a separate command before the next 5SCII execution.
The pointer needs to be updated in the command. 5M0V, SCMP
But it's the same. [Disadvantages of terminating the instruction after updating the pointer] The pointer value after the instruction is executed is ahead of the element for which the termination condition (search condition) is satisfied, so this is a good specification for a 5SCH instruction.
isn't it. Matches the specifications of BVSCH and B5Cl+ instructions.
do not have. In TPONCHI P, [instruction before updating pointer]
Emphasis is placed on demerit companies that terminate the process, and
In some cases, the instruction terminates after updating the pointer.
I'll do it like that. Therefore, 5M0V/F, SCMP/F,
5SC) The pointer after the l/F, /R command is
to point to the next element after the element for which the condition is true.
Become. In addition, in the case of 5M0V/B and SCMP/B instructions,
The instruction ends because the pointer is updated by pre-decrement.
The subsequent pointer points to the element for which the termination condition has been met.
It becomes. 5M0V/B, SSCMP/B(7) Specifications't
BVMAP/B, B
In the case of VCPY/B, the bit fi eld that is the target of the operation is
Specify the maximum offset +l of the field using R1 and R4. However, for BVSCH and B5Cl+, the instruction ends.
The later bit offset directly points to the bit to be searched.
/F and /FJ because it is considered more convenient to
Make the specifications like that. Also, regarding QSCII,
Since the pointer is updated, 5SCH, B5
The pointer update timing is different from Cl+. After all, BSCH/F (BVSC) l/F), 5SCII
/F, QSC) I/F search pattern is summarized.
, becomes as follows. BSC) I/F From what the pointer is currently pointing to
Search. After the search is complete, the pointer points to the found data. 5SCH/F Search from what the pointer currently points to.
Search. After the search is complete, the pointer points to the next data found. QS (Jl/F The next item currently pointed to by the pointer
Search from. After the search is complete, the pointer points to the found data. For string instructions, the number of elements R2 is unsigned
treated as a number. This means that R2 can be considered unsigned.
By specifying R2=0, the number of elements is set to I+
' Interpreted as 100000000, depending on the number of elements.
This is because it is possible to prevent the termination from occurring. This feature
can be used to implement the strcmp function of the C language, etc.
. Also, in implementation, R2 is considered unsigned.
Although it is easier to judge the end based on the number of elements,
The width of the field instruction is determined by the following reasons.
Fixed length bit field instructions, arbitrary length bit field instructions
We will treat both the field instruction and the command as signed.・When executing the instruction, the width of the bit field instruction is o.
It is added to ffset, but offset is a sign.
It is numbered. If width is unsigned, signed
It ends up adding unsigned numbers, which doesn't look neat.
. In the case of the element size of a string instruction, it is natural to use an unsigned value because it is multiplied by the size and then added to the pointer.・Differences between signed and unsigned instructions appear when executing instructions.
The arbitrary length pit field command t'width is H'8000000.
This is a case of 0 to H'ffffffff. Pledge 1dth
If it is signed, when width is this value, VJI
The instruction ends simply by setting ag, but if the width is unsigned, the width
Bit field operations will also be performed when the value is . However, suppose the width is H'80000000~1geffffffHf
and the value of offset + width is signed.
If you treat it as
set + width to unsigned or 33 bits
Even if it is handled as (signed), overflow may occur depending on the value of offset. For overflow, roffset +wi
Operation is not guaranteed if dth overflows.
”, so a similar implementation is possible.
If you want to do this, even if ν1clth is unsigned,
“The number of J cases where operation is not guaranteed will only increase.
'If you want to guarantee the operation in case of 80000000
, with a hardware burden.・For string instructions, the instruction is terminated by the termination condition.
O when you do not want to terminate depending on the element size.
There is a way to use it by setting . 0 is infinity (H' 1
00000000), it is necessary to use an element
It was necessary to treat the client size as unsigned. to this
Engrave, BVMAP, BVCPYI? is other than width
Since there is no instruction end element in
A meaningful value must be set as dth. In that case, ``The value in the register is, in principle, signed.''
It is more natural to follow the principle of "consider it as the number of [Basics of string instructions and arbitrary length bit field instructions
Summary of principles In co-search type instructions, the timing of pointer updates is
Independent of the direction of the path. B5Cl and BVSC1l't' are both /F and IB.
After completing the search, the pointer points to the found bit. For 5SCH, both /F and lR are pointers after the search is completed.
points to the next element after the one found.・In the case of /F, the command that actually manipulates data is
increment, pre-decrement in case of IB
Processing is performed in the form of This applies to 5M0V and SCMP. There are BVMAP and BVCPY. 5STR, BVPAT only has /F(7), but still
The same principle applies.・For string instructions, the element size is unsigned.
In case of '09, H' 10000000
Represents 0. On the other hand, for arbitrary length bit field instructions,
width th is treated as signed, and width
I+'00000001~ll'7ffffffff
Actual bit field operations are performed only in rows Al1-2
．． goose ゝ ro Δ no 萱, -shadow
The operation of 10V SMOV is summarized as follows.
Ru. However, if the final result is the same, the memory access
It does not matter if the order of the processes is different from the one below (other
The same applies to high-function instructions). Also, SrC and dest are
When the bar is overlapping, select the incorrect option.
When used (when /F is used with src< dest)
and when /B is used with SrC>dest)
The operation does not have to be as described below. [Operation of 5M0V/F] 0 ==> VJlag epeat R2-1 ==> R2 mem[Ro] ==> mem[R1] ==>te
mp RO+ 5ize ==> RO Rl + 5ize ===> Rlcompa
re temp with R3, R4 and set
Fjlag, M-flagaccording
Lo eeee/If the termination condition is satisfied, Fjlag: 1/if (FJIag = 1) thenxit chec3interrupt until (R2= O) 1 ==> VJIag [Operation of 5NOV/B] 0 ==> VJIag epeat R2 − 1 ==> R2 RO-5ize ==> RO Rl -5ize ==> Rl mem[RO] ==> mem[R1] ==>te
mp compare temp with R3,R4an
d set FJIag, M-flagaccord
ing to eeee /If the termination condition is satisfied, FJIag = 1 / if (FJIag = 1) thenxit check-1interrupt until (R2 = O) 1 ===>,, V-flag In SNOV, the initial value of R2 No matter what, it is always
One or more elements are processed. The reasons for the termination of 5NOV are summarized as follows. 1. End element by number of elements (data) (R2)
When the instruction is terminated by the number of entries, VJIag=1. 20 cases at the same time
It doesn't happen. 2. Termination based on termination conditions At this time, FJ! ag=1. Satisfied the termination conditions
Transfer of elements also takes place. ≦2 Tsuji In SCMP, the end of the command and the end condition according to the number of elements
In addition to terminating an instruction due to a mismatch in comparison data,
may end the command. Data loss with SCMP
Even if the instruction is terminated due to a match, the instruction is terminated due to the termination condition.
The pointer is updated in the same way as when the instruction is finished.
Then the command ends. In SCMP, the number of elements
and other termination factors occur at the same time.
However, if the termination condition and the termination factor of data matching are at the same time
There is a possibility that it will be fulfilled. If SCMP finishes due to the number of elements, then
The following elements are not compared, and the next element is different.
Even if the condition or termination condition is satisfied, VJIag=0. F
-fIag=0. Finish the command with Z-flag=1
do. The SCMP operation can be summarized as follows.
Ru. However, if the final result is the same, the memory access
It doesn't matter if the sequence order is different from the one below. child
All you have to do is perform an operation equivalent to that. [SCMP/F operation] 0 =:> V-flag epeat R2-1 ==> R2 mem[Ro] ==> temp1 meo+[R1] ==> temp2RO+ 5i
ze ==> RO Rl + 5ize ==> Rlcompar
e templ with temp2and set
ZJlag.し-flag,
nd set FJIag. -fla3 according to eeee /*If the termination condition is satisfied, Fjla8=1 *l if (Fjlag = 1, or. ZJlag = O) then xit /*termination due to termination condition or data matching check-interrupt until (R2= O ) 1 ==> V-flag [SCMP/B operation code 0 ==> VJIag epeat R2-1 ==> R2 RO-5ize ==> RO Rl -5ize ==> Rl mem[Ro] ==> tempt mem[R1co ==> temp2compare
temp with temp2and set
Zjlag. Ljlag, X-flag / If the data does not match, Zjlag = 0.
nd set FJIag. Gate-flag accordin8to eeee /*If the termination condition is met, Fjlag = 1*l if (Fjlag = 1, or. Z-flag = O) then xit /Terminates due to termination condition or data matching */ chec31nterrupt until (R2 = 0) 1 ==> V-flag The causes of termination of SCMP are summarized as follows. 1. End according to the number of elements (data) (R2) at this time
,Z,,flag=1. F-flag=0. V-f
lag=1. 2 or 30 cases do not occur at the same time.
do not have. 2. Termination based on termination conditions At this time, FJlag=1. Satisfied the termination conditions
Comparison of elements is also performed, and the comparison results are jflag and L-flag. Set to XJIag. If the comparison is inconsistent,
This corresponds to the two termination factors 2 and 3 being met at the same time.
do. 3. Termination due to mismatch of elements being compared In this case,
The comparison results of elements with mismatches are Z-flag (=0) and L-flag. Set to X-flag. V-flag becomes 0. 8. If 5SC11 is terminated according to the termination conditions (search conditions)
For both /F and /R, the pointer ends after the instruction is executed.
Points to the next element after the element for which the condition was met. Ma
In addition, when 5SCI+ ends depending on the number of elements,
Also, after the instruction is executed, the pointer points to the next element. The operation of 5SCII can be summarized as follows.
Ru. [Operation of 5SCIl/F] 0 ==> VJlag epeat ・R2-1 ==> R2 mem[Ro] ==> temp RO+ 5ize ==> RO compare temp with R3, R4a
ndset FJlaH, way Flag according to eeee /If zero exit condition is met, Fjlag = 1*/ if (FJIag = 1) then exit/
Termination according to termination condition (search condition), t/chec31interrupt until (R2=O) 1 ==> VJlag [Operation of 5SCI/R] 0 ==> Vjlag epeat R2-1 ==> R2 mem [Roco == > temp RO+ R5==> RO compare temp with R3, R4a
ndset Fjla3. Town flag according to eeee/ne termination condition formation
If it is set, jflag = 1 */ if (Fjlag = 1) then exit/
*Termination based on termination condition (search condition)*/ check-1interrupt until (R2=0) 1 ==> The termination factors of VJIag SSCH are summarized as follows. 1. End according to the number of elements (data) (R2) at this time
, V-flag=1. 20 cases occur at the same time.
It doesn't bother me. 2. Termination based on termination condition (search condition) At this time, jflag=1. No flag change occurs in Takuma B 55TR. 5STR operation
The ration can be summarized as follows. [5STR operation code epeat R2-1==> R2 R3==> mem[R1co R1+ 5ize ==> R1 chec3interrupt until (R2=O)
When executing a high-function instruction with P, each register at the end of the instruction
The value of the star is as follows. Note that RXinit returns the value of register Rx before executing the instruction.
show. Also, RXend is the register RX after the instruction is executed.
Show value. [:BVSC11] When /F, the offset is R11nit to R11nit
Search the range +R21nit-1. /B, the offset is R1ini t~R1ini
Search the range t-R21nit+1. If R21nit(width)≦O, Vjla
Set g to end the command. R1 and R2 remain unchanged. If one search is successful, RO (base address): unchanged R1 (off
set): Bit offset of the bit found in the search result. R2 (enemy 1dth): Not yet serviced
The length of the bit field including the bit field and the found bit, that is, if /F, R21ntt+R11nit-Rlend. /B, it becomes R21nit-R11nit+R1end. - If the search fails, RO (base address): unchanged R1 (off
set): Next to the last searched bit
bit offset of . In other words, if /F is R11nit + R21nit, if /B is R11nit
It becomes t-R2init. This is the same idea as BSCH. R2 (width): 0 [BVMAP] [BVCPY] When /F, R11nit ~ R11nit + R21n
The area having a bit offset of it-1 is src, and the area having a bit offset of R41nit to R41nit+R21nit-1 is dest. /8, Rf tnit ~R11nit-R21
The area with a bit offset of nit+1 has a bit offset of src, R41nit-1 to R41nit-R2init.
The area becomes dest. If R21nit(width)≦0, do nothing
ends the instruction. R1, R2, and R4 remain unchanged. RO (src base): unchanged R1 (src
offset): /F if R11nit+R1
1nit, /B becomes R11nit-R2init. R2 (width): 0 R3 (dest base) unchanged R4 (dest
offset) /F if R41nit+R2
1 nit, /B becomes R41 nit-R2 init. R5 (operation type gl) Unchanged (only 8VMAP(7))
[BVPATkoR41nit ~R41nit+R21nit-1(7
) The area with the bit offset becomes dest. If R2init(width,)≦0, do nothing
ends the instruction. R2 and R4 remain unchanged. RO (pattern): Unchanged R2 (widt
h): 0 R3(dest base): Unchanged R4(des
offset): R41nit+R21nit
R5 (Type of calculation) Unchanged [When 5M0V/F, ROinit-S-ROinit+R21nit
The area with address 1 is src. R11nit ~R11nit+R21nit*eleme
The area with the address of the client size minus 1 becomes the dest. When 1B, ROiniL-1 to ROinit-R2init
The area with the address size is src, R11nit-1 to R11nit-R2init
The area with the address of the ment size becomes the dest. For example, if the string from H'0000 to H'00ff is
'5M0 when transferring to 0300~ll'03ff
V/F, Wte: ff Bee, RO=ll'0000
．． R1=H'0300. R2=l+'0040SMOV
/B, W1? :12 peas then RO=)l'o10
0. R1=)I'0400. R2=)l'0040
That's fine. However, if the termination condition is met, the process is interrupted midway.
be cut to pieces. Data for which the termination condition is satisfied is also transferred to the dest side. - If it ends depending on the number of elements (Lrlag=1) RO (src address): /F then R
Oinit+R21nitl: Instrument size, 1B if ROinit-R2init*element size R1(dest address): /F if R
11nit+R2init*element size, if 1B, R11nit-R2init element size R2 (number of elements) 20R3 (termination condition 1): Unchanged R4 (termination condition 2): Unchanged 1 Termination condition was met and the process ended. Case (jflag=l) RO (src address): End clause when /F
Address R1 (dest address) of the element of src where the termination condition was satisfied when the address 1B of the element next to the element of SrC where the condition was satisfied: Termination condition when /F
When the dest address lB is where the next element of the src element for which the condition has been satisfied is to be transferred, the dest address /F and lB are both R11nit+ ROend -ROin it. . R2 (number of elements): Elements that have not been transferred yet
Number of points/F when R21nit-(ROend-ROinit)
/ When the number of elements is 1B, R21nit-(ROinit, -ROen
d)/element size. R3 (end condition 1): Unchanged R4 (end condition 2): Unchanged (:SCMP] When /F, ROinit ~ ROinit + R21nit new element
The area with address size - 1 is 5rcl. R11nit~R11nit+R21nit*Element
The area having the address size -1 is 5rc2. When 1B, ROinit-1 to ROinit-R2init
The area with address size is 5rcl, R11nit-1 to R11nit-R2init
The area having an address of the same size as 5rc2 is 5rc2. For example, the string Il'0O00-)1'00ff
and the string H'0300-H'03ff.
When comparing with SCMP/F, %+I, RO=H'0000. RI=l'0300. R2=l+
Comparing with '0040SCMP/B and %Il, RO=H'0100. R1=ll'0400. R2=1
It may be set to 1'0040. However, if the termination condition is met, the process is interrupted midway.
be cut to pieces. Comparisons are also performed for elements for which the termination condition is met, and the
The results are Ljlag and X-flag. Set to Zjlag. Also, if there are any mismatched errors during the comparison,
Even if an element is found, processing is aborted midway.
It will be done. - If it ends depending on the number of elements (VJlag=1) RO (srcl address): /F then R
Oinit + R21nit element size, if 1B then ROinit - R2init * element size However, if R21nit<O, no change R1 (src2 address): /F if R
11 nit + R21 nit element size, if 1B, R11 nit - R2 init element size R2 (number of elements) 20 R3 (termination condition 1): Unchanged R4 (termination condition 2): unchanged - If the termination condition is met or the element values do not match Okay
(Fjlag=I, or, Z-flag==0)
RO (srcl address): End clause when /F
When the end condition is met (or mismatched) when address lB of the next element of the srcl element is met (or mismatched) When the end condition is met (or mismatched) Address R1 of the srcl element (src2 address): /F termination clause
The condition was met (or there was a mismatch). The end condition was met (or there was a mismatch) when the address of the 5rc2 element corresponding to the next element of the srcl element was met (or there was a mismatch). The element addresses /F and 1B are both RIinit+ROend-ROinit. R2 (number of elements): Elements that have not been compared yet
Number of points/F when R21nit-(ROend-ROinit)
/z element size, when it is 1B, it becomes R21nit (ROinit - ROend)/element size. R3 (End condition 1): Unchanged R4 ($? End condition 2): Unchanged [5SCH] When /F, ROinit, ~ROinit + R21nit * Element
Search for the area with address size - 1. /R, ROinit-ROinit+R5neR21nit-1
The area having the address of R5H is searched intermittently. However, if the termination condition (search condition) is satisfied, the process is aborted midway. - When finished depending on the number of elements (VJIag=1) RO (src address): /F if R
Oinit÷R21nitl: Element size, /R if ROiniL+ R2in it * R5 R2 (number of elements) 20 R3 (termination condition l): Unchanged R4 (termination condition 2): Unchanged R5 (*”inter update value): Unchanged - When the termination condition (search condition) is satisfied and the termination occurs (FJ
lag=1) RO (src address): Termination condition met
Address R2 of element of SrC (number of elements): Element for which termination condition was met
and the total number of elements that have not yet been searched/F, then R21nit-(ROend-ROinit)
/Number of elements is, /R when R21nit-(ROend-ROinit)
/R5. R3 (end condition 1): Unchanged R4 (end condition 2): Unchanged R50°inter update value): Unchanged [5STR] R11nit-R1init+R21niL*element
The data specified by R3 is repeatedly written into the area having the address size -1. Unlike other string instructions, the specified name of the termination condition is not specified. Also, no flags are set. If R2init(width)≦O, the command is immediately executed.
end. R1 and R2 remain unchanged. R1 (dest address): R11nit+
R21nit*Element size R2 (number of elements): 0 R3 (write data): Unchanged [QSC) I] - When terminated by queue end value (R2) (V-f
lag=1) RO (entry address): R21nitR
1 (Privious entry): Indicated by ROend.
Address R2 (queue end value) of the entry immediately before (in the case of /F) or immediately after (in the case of /B) the entry to be executed: Unchanged R3 (end condition 1): Unchanged R4 (end condition 2): Unchanged R5 (offset) ): Unchanged R6 (mask): Unchanged - When the termination condition (search condition) is met and the operation ends (FJ
Iag=1) RO (entry address): Termination condition satisfied
Address R1 (priorious entry) of the queue entry: ROend
Address R2 (queue end value) of the entry immediately before (for /F) or immediately after (for /H) the indicated entry: Unchanged R3 (end condition 1): Unchanged R4 (end condition 2): Unchanged R5 (offset) ): Immutable seal-IAj2. -Ogo Kazuhisa - 1 power 51] In case of no interference
Operation - An instruction has multiple operands, among which:
dsP, 1-St' mode and mode referring to S11
When used together with
When will the SP value changed by °C be reflected?
What you say becomes a problem. Thinking about this problem more generally
clearly specifies the behavior when the operands cross ζ.
This means that all you have to do is set it. This sample is a device of the present invention, and the operands in the command interfere with each other.
It is important to clearly define the behavior when something happens.
This is the purpose. This issue is addressed early in the document.
We explain the concept of
It specifies the operation of lighting equipment. A12-1. In order to sort out the problem of Meido Inuoka ±1 gray operand interference, first, each command
``ead, w'' performed on memory and registers from
ri to, rttad-s+odiry-wri
Basics of La °r access: A hypothetical that includes all i works
Consider a command pattern and model it as shown below.
do. RAl, first read operand (IJOI)
Effective address calculation ■ RRl, -th read operand (Rot) reading
Dashi RA2. Second read operand (RO2) execution
Address calculation ↓ RR2, read second read operand (R02) ↓ R^3. Third read operand (RO3) effective address
Dress calculation ↓ R1?3. Second read operand (RO3) reading
Midashi AAl, -th address operand (AOI
) Effective address calculation ^^2. First address operand (AO2
) Effective address calculation ↓ WAl, th. = wriLe operand (Hot)
Effective address calculation? IA1. No.-read1odify-write
e operand (Question 1) Effective address calculation MRl, read-modify-wri
Read te operand (MOI) ↓! Xi wn, execution of instructions (1 to n) ↓ MWl, read-modify-write
e operand (Mol)-7 entry 541. First -riLe operand (interval 1) writing
Each element of RAI-Ml that constitutes the model is
Call it 1.・Specify the addressing mode of asp+, 1-5ll.
If the SLL value is updated, one effective address calculation j is performed.
Step (RA1, R to 2. R to 3.? IAl, -81
).・Each step uses resources in one of the following patterns.
“?Access, but 1 resource” means memory or
refers to registers visible to the program. one resource access one one read from one or more resources -- one
wriLe ([X1~1EXn, MW
I. only) - read-modify-wriLe of resource SP
(R^1.R^2゜k^3.MAl, -^l, Kahachi2
・If the resource value is updated in each step,
The updated value will be reflected from the next step.・In general instructions, only some of these steps exist.
do.・F! The steps Xl, ~hXn are actually instructions
Depending on the type of uXl, EX2. How many Eχ3...
It is divided into steps. In the above model, the resource that writes at each step is
The source is at most, Sll's r l! a
Except for the case of dmodify-write, one
In the case where read and wriLe are mixed in a step,
Otherwise, the stale values in the resource will be removed from the next step.
We have clarified the conditions for it to be reflected.
, when accessing common operands between steps
The behavior is also clearly defined. Therefore, the behavior of each instruction
If we can successfully fit the above model, we can
It also stipulates that the behavior when the pellands overlap is also prohibited.
be able to. The operations of most of the commands of the device of the present invention are 1. The above effective parameters
A subset of turns and t/-ζ become 1γ°ζ. However, which action corresponds to which step?
As for the command operation, there are various kinds depending on the α seasoning.
Can be interpreted. For example, ACO: G asl'+', sP, 1sP), n
In the case of ewpc, it is natural to interpret the following ■.
It's natural. In other words, each action step or operation of the ACB instruction
The correspondence between Rand and the models in 1 and 2 is as follows:
It is normal to do this, and in fact, this is the correct TR0M.
It is a specification. ■＾CB's 5TEP operands correspond to the model's ROI
ACB's LIMIT operand corresponds to model's RO2
The xreg operand is EXI-1! Handled only in X3
, Run, MOnJOn. RAl, 5P=->roladdr: SP+5i
ze==>5PRR1, aroladrr=>5te
pRA2. 5P==>ro2addrHSP+5iz
e==>5PRR2, aro2addr*=>11m1
tR83~M)+1. None EXI, 5PY->xreg 1! X2. xreg)sLep=-->xreHi
f(xreg<Ii+wiL)jump to new
pcend if EX3. xreg-=>SP MWI~gaW1. None roaddr, ro2addr, 5tep, l1
m1L xrel is an internal variable and cannot be used in the model.
In this case, if the SP value before instruction execution is 1 nitsP,
, 5tep: a (inlet S1xr
eRne sword μsu 1i 1%: 1niLsr'+5i
ze*211m1L: d(iniLsl'1
greR after sixtri BX: 1niLsP4si
zt+$21ij (initslυ jump condition: 1
niLsl') size*2+d(iniLsl<1
(iniLsI'+5iza) S11 final value: 1nitsP+5ize*24a
(initsl') However, the actual behavior of the ACB instruction and
It is also impossible to correspond with the model as shown in the following ■.
There isn't. The operation of (①) is not the same as O) in terms of tuna. ■＾CB's 5Lep operand corresponds to model's ROl
When the ACH's Xl"0g operand is read, it becomes P()2.
, the Ii@iL operand of eight COs corresponds to the old time -01, and corresponds to the model RO3.
RA1. 5P-=>roladdrHSP+5ize
-=>5PRR1, aroladdr==>sLepR
A2. RR2,5PF that does not refer to anything =>xreB RAJ, Sl'=,>ro:bidtlrHSl
'4size-I->Sl'RR3, aro3addr
==>11m1t88l~MH1, None EX, xreg+sLep==)xreHif
(xrttg<l1m1L) jump LOne
wpcndif between 1. None WWl, xreH==>5P roladdr, ro3addr+ 5tep li
*it+ xreg is an internal variable and is not used in the model.
In this case, Sl'(/i /cini L
Assuming SP, 5tep: a(initsP
)xreg first 7133 value: 1niLsP+s'iz
e1iw+it: a(initsP+5iz
e) xrag after Ex: 1niLsl'+5iza
4d (iniLsI rejump condition: 1nitsP+
5ize+a(initsP)<1j(initsP+
5ize) S11 Saihiragi: 1niLsI'+5iz(!1
2j (iniLsl) This is a different operation from
Since it is not strictly known whether ■ is correct, °
There are cases where the correspondence between ζ and the model is ambiguous. Mo
If the correspondence with Dell is different, small movements may occur as in the example in
The production may vary. In this document, the instructions for the device of the present invention are as follows.
Determine the correspondence between the method C command movement I1 and the model.
This clarifies the behavior when operands overlap.
It is L1-like to specify this. beast? 72 Rainbow A Reli Additional Rules Before considering the instructions individually, let us consider the interference of the operands.
We will explain the basic principles of (Principle 1) The contraction and general forms must perform exactly the same actions.
Of course, the difference in instruction format is
The shortened form is completely
Should be a subset of the ship shape and have different shortenings of behavior
Shape is confusing. The instruction execution model is based on implementation dependencies and
Because it is not designed with the convenience of
ζ may not be implemented as specified.
For example, 800:L 1jsl'+, Sl"
ADD: GasP+, when it operates differently from SP
This is an example of a case where there is a coincidence. Case like this
Regarding °ζ, leave the power of the instruction execution model as is (
and treated as exceptions depending on the situation. (Principle 2) Basically, the operation in the instruction bit pattern is
The operands of the instruction and
The read operand (ROI) in the model,
-T, read operand (RO2) Pair with ”...
decide how to respond. If this is done, the implementation method is generally
No contradiction. The instruction execution model is based on the behavior and bit pattern of each instruction.
Think about it and make sure that the eel has a natural shape. Abbreviation and -・
For instructions with a shell shape, the instruction execution model and actual instruction behavior are
The question of whether or not it will correspond naturally with the
Instruction bit pattern! 1. It depends on whether
However, in this case, the -.m type is used as the standard for deceleration. Regarding the correspondence between command behavior and model,
Although the bit pattern is convenient, it is the capital of implementation.
I don't really think about it. <trtt! ! 13 > Even with principle 2, general-purpose applications
Non-dressing operands (e.g. 8CR xreg)
), the nth read operand in the model (
ROn), the a+- write operand (Woe
), but only in the Ex step.
This is P. (Principle 4) Also, 1111 is implicitly included in the alpha flavor of the command.
Memory access (PUSH, 1) with 01'
tuck operation t (do) - no (also, nth in the model,
read operand (ROn), n+-wriLe
The operand (WoIll) does not smoke °C, and the liX
'tY' is handled only during the step. In addition, there may be special circumstances for each command, or there may be a large number of
If the operand is (1, IIM, STl'1)
), these principles may not apply. Details will be discussed for each command. ＾－■、? Nuji 9 Yumashi Order - Rei 2 ζ! ≦p2noζ
. The commands of the device of the present invention are divided into 1r1 patterns.
1ζ model and the operands are buffered.
We clearly explain the behavior when (November 91),
When operands interfere even if the instruction formats are different
The operation is the same, so the difference in instruction format
There is no need to differentiate between cases. Note that 1niLsl' that appears in the operation example is the instruction execution
This is the meaning of SP before the line. In addition, the life that appears in the operation example
The operand size of command is ``ζ3'' unless otherwise specified.
It is assumed to be 2 bits.゛・〜〉” indicates value assignment, ゛(〜〕゛
does not show any comments, and the step of RAI-WWl,
Ura, there is one step in the step that is not used in that command.
(Explanation is omitted. Applicable command: OII ++ 1 Is village TS RRNt; RAP R1!IT TCTX II T L Is 11VSCII BVM8P to vcpv VFAT NOV CMII 5C11 STR 5C11 The operation of the command is 1- With only 14X steps of the model
is carried out, and no other part exists, therefore,
Operand interference is not a particular problem. With high-performance instructions, the number of HX steps is not finite.
This model cannot accurately represent
Sometimes. However, this is a problem of 1-interval of operands.
Since it does not directly affect the government, it will not be discussed here. [Correspondence between instruction execution model and operand] EX,
Operation with instruction 161 [-oヱχ''] execute (±1-the relevant instruction: [IRA newpc 11cc newpc BSRnewpc TRAI) 8 vector WAIT igask Operands are present, but the value of the operand is the same as the instruction command.
Because it is specified directly in the code, there is no need to worry about the
°ζ is not a problem. netvpCl vector
. imask is I! You can tell by operating in x steps. [Correspondence between instruction execution model and operand] EX,
Instruction-specific operations (newpc, vecLor+ima
sk reference] L±gojno5-rley-1J-edge and the ¥1 instruction: 1'Usll src. LDl'S11 src LDPSM 5rc JRNG vector For this pattern of instructions, srt:, ve<two to
r is the first -read operand of the model' (ROI)
treated as If 5rc=ijsl'+, Q total 1/rl(+ operation
By the time step ii is performed, SP has already been incremented.
It means that [Correspondence between instruction execution model and operand] RA1.
src, vector address calculation = s>rol
addr RRl, aroladdr-->5rc-+
vectorEX, instruction-specific behavior (depending on the instruction)
In PIjSII, 5rc=->PSIILDPSB
Then, op, (PSB, 5rc)->PSBl, Kano
In SM, op, (PSM, 5rc)−=>PS
MFor example, apply this model to Pt1SllaSP+
and [1111 S II instruction specific operation (src
=s>a-5lυ Before performing 5rc in RAl,
It can be seen that sr' is updated by -4jsI'+.
Karu. However, to prevent mistakes, pusoasp+ is
It is prohibited (RIB) (see Figure 375). 1 f-=S run j' address (A) Applicable order
Order: 1'UsIIA 5rcaddr PSTLB prgaddr LDCTX cLxaddr AC5chkaddr JMP newpc JSRnewpc Src, addr+ prgaddr, cLxaddr
, cllkaddr+ newpc as the first t of the model
hddrt! Treated as ss operand (8()1),
In addition, in AAI, the mode of asP+ and 1il-SP is
Not available. [Correspondence between instruction execution model and operand] AA1.
5rcaddr+prgaddr, cLxadd
Address calculation of r+2I+kaddr+newpc=
=>, Ioladdr14X, instruction fixed (+ operation
(Including implicit stack operations by instructions) In PUS11^ aoIacltlr=, >1-sr
'In JSR, PC==>a-Sl': aol+
ddrll Tomi〉PC PUSIIA asP and JSR1jsP operation is 37th
As shown in Figure 6. t, -i-shira, ndo r, j je-(,0) applicable
Instruction: 1) 01g desL STPSB dest STPSM dest desL as the -rite operand (set) 1)
°ζ In this case, the WAI before the EX step
In step, the effective address calculation of dt+sL is performed,
Only write the value in the 4l step after Ex.
It becomes every time. [Correspondence between instruction execution model and operand] -^1.
effective degree of desL, 11 calculation r, ->wola
ddrBX, instruction-specific behavior (implicit
(including stack operations) 1) In the OP aSP+=, > desL2STPS
In B, op, (PSB) -=>das t2
In STPSM, op, (PSM) =->de
s t2M1. dest2==>awoladd
rFor example, apply this model to IjOP&,,sP
and EX, the operation specific to the pop instruction (asP+==>
-A1. And already dasshi 1
It can be seen that the SP is updated by j-5P. Also, POII d (d, SP) d, L, no model
When applied, Il,X. The operation specific to the pop instruction (aSP+->deal2) is
Before doing this, set the address of dest=i(d,SP) in WAl.
Address calculation is performed, and 1 is used for dost address calculation.
nits! ' is used. However, to avoid mistakes, it is actually 1101) 1j
sp is prohibited (RIB), and pop a
For (d, SP), the address of tj (d, peer n) is
Prohibiting execution only when Rn*SP in single mode is
It is unreasonable, stack operation °ζPOP a(
disp, sP) can also be considered.
Rather, it is not prohibited. An example of the operation of the pop instruction is shown in FIG. l Opera Z do rmw (M) Applicable command: Nt! G dest NOT desk SIIXL desk SIIXRdeal dest is made to correspond to Mol. In this case, MAL
dsl'+, a-5t' cannot be specified.
. [Correspondence between instruction execution model and operands] MAL,
DesL effective address calculation ==>soladdrM
Rl, amoladdr==> das口EX,
Instruction-specific operation, op, (dastl) ==> dest2MW1.
desL2 ==> amoladdrL operation
read ~ write (RW) - applicable order
Order: MOV sre, desL MOVII src, des LRVIIY
srt:, desLRVBI src,
dest PACKss src, destUNPKs
ROI s src, dest, adjsrc
, dest corresponds to interval 1. Therefore, sr
The effective address calculation on the c side and the associated SLL update should be performed.
After completing the process, fetch src, and then
Des is used to calculate the effective address, and finally the instruction is
Performs a specific operation and sets the result to dest. The adj of UNPKss is handled in the HX step, and the nth
-Do not use as read operand. [Correspondence between instruction execution model and operands] RAI,
Effective atlus calculation of src ==) roladdrR
Rl, aroladdr==> 5rclWA1
．． Effective degree metres calculation of desL ==> wol
addrOX, instruction-specific operation, op, (srcl) ==> desL2IJNPKs
See adj in s! ! ((Ml, desL2-
〉An example of the operation of 1wol+oldrNOV is shown in Figure 378.
Street. An example of the operation of UNPK in PAC is shown in Figure 379. Lti Kuotori Kikurikurigoichichoj'' 0p Lee applicable commands: STCsrc, dest STP src, dest M (IVA 5rcaddr, +11!SLMO
VPA 5rcaddr, destSTATI4
5rcaddr, city! ! 1 [(101 mm L
queue, dest control space, physical space, etc.
For instructions that read from a special space, the special space
The effective address SrC, 5rcaddr on the side is set as AOI.
The actual access to the special space is done in the Ex step.
The QDEI command also creates a queue entry.
Set the effective address queue of the specifying side to 801.
The actual operation of the cue link is done in steps F and X.
Let's do it. By doing this, the instruction bit pattern and input
It also corresponds well to the supplement method. In 18l, ds
l'l, 77 Sll cannot be specified. dest is treated as ζ. AAl, src, 5rcaddr, queue
Effective address calculation of e ==> aoladdr Satoshi 1. Calculating the effective address of dest...>woladd
rEX, instruction-specific operation, op, (aoladdr)-=>desL2WW1
．． desL2==>cjwoladdrSTC,
The correspondence with the operation example of N0VA is as shown in Fig. 380. IIIova dSP, for 1j-5l', 5rc
Addr effective address calculation (A^1) step
S11 is already referenced in the application, and the effective application of dest is
The update of S+3 in the dress calculation (WAI) step is
5rcaddr, whereas STC
Assuming that 1ispO and a-5P operate according to the model.
Considering that the effective address calculation (AAI) of S
Sll is not yet referenced in the step, and the control register is
The address (11'0124) of Sl) as a star is
It is only calculated. S11 is referenced in [X's
step, which is the effective address calculation of desL (
This is after updating the SP in step ga^l). death
Therefore, 1niLsP-4 is transferred to dest
It turns out. However, the operation of STCaspo and a-5P is
It is important to check whether the model behaves as shown in , h, and h.
I'm addicted to it.・) Mari, model expert
When transferring 1nitsP-4,
ζ is treated as an exception, but when transferring 1 nitsP
There is a coincidence. - Murant' rc2adヱI Wataru [Kuni 1 Sen - Heshi applicable life
Order: LDC5rC1desL LDP src, dest LDATt! SrC+ destaddrl
lTST offseL baseusF,'r
offseL+ baseRCI, Ro[s(!L
, bastr BNOT offset, basells [ET
i offsat+ baseBCI, R1offs
et, baseBFEXT offset, wi
dth, base+ desL liver uXTII o[
st+L, widLh, hase, desLBP
INS 5rC1offset, widLh+b
ase old 'lN5U srt:, o[seLlwid
Lh, basLIBFCMP src+ offse
t, width, base11PcMl'U 5
rC1offseL, widLh, bastICI
IK bound, 1ndex+ xreg control
An instruction that writes to a special space such as space or physical space.
In the order LDC, l, Kano, I, DATE, the special space side
Effective address '1. L desLaddr^01. Treat src as ROI. Actual access to special spaces
is performed with OX. In the bit manipulation instruction, the effective address of base is set to 801.
Treat s offset as ROI @base
and offset, and select the bit to be manipulated.
The actual access is done within IiX. Even fixed-length bit field manipulation instructions can be used as human manipulation instructions.
Similarly, the effective address of b 13 S e is AOI
s offset? ol and °C, off
Operands other than set and base, i.e. width,
For src and dest, arc only in Ex
The -th read operand (ROn), the m-th
It is not treated as a raad operand (WOm). In the case of C11, from the relationship with the bit pattern, 1n
dex ;f! -ROI, bound as AOI
handling, b. The reading of (upper limit value 2 upper limit value) which is the content of und and
Writing to xreg will be performed at εX. Below, the correspondence between the behavior of each instruction and the model is shown in the form I:.
If you attach the command focus pattern and implementation
It is consistent with the method. AAI Te cannot specify aSP+, a-5P.
Not possible, src, offset, 1ndex = 1
If jsI'+, des Ldestaddr, b
Referenced in ase+ hound's effective address calculation
The value after increment is used for Sl+(, Hetoshi °ζ
will be done. In the case of a command to CH, this is
Please note that the order is reversed from the bra notation.
be. Also, offset with fixed length bit field instruction
Specify L・dsl'+ and set src, width, etc.
When specifying the same SP, the SP value is still
The value after the increment will be used. assembler
In the notation, in the case of BFINS, BFCMfl, it is off.
srt: is now written before set.
(However, in reality, the effective address calculation of offset is
Please note that this will be reflected in the updated S quotient'src.
It is. RAl, src, offset, 1ndex
Effective address calculation = +-> rolxddr RRl, aroladdr ==> 5rcl8
81. dasL, destaldr+
Base, bound effective address calculation ==
> aoladdrEX, instruction-specific operation, op, (srcL aoladdr) In C11, op, (srcl, aoladdr) =->reH bdoINs, np+Nsu, IIPcMP, liver CMl'
1 in ll, op, (srcl, aoladdr, width
. 5rc) BFEXT, [1FPXT(I Te is 1, op, (s
rcl, aoladdr, width)y, =)
dI! An example of the operation of 5L BFINS and BPEXT is shown in Figure 381.
the law of nature. 2 operands raaj ~read (RR) applicable instruction
: CMP 5rc1. src2 CMPU 5rcl+ 5rc21NDt! X
1ndexsize, 5ubscript+
xreg＾CB 5tep, xreg,
1isit, newpcSCB 5te
p, xreg* 11mft, newpcC
MIl, CM circle 1, 5rcl to P old, 5rc2
correspond to RO2. INI) UX, 1ndaxsixo 4:ROl
, 5ubscriptL corresponds to RO2. xreg
is handled in [Ni]. A to B, SCB to 5tep4:ROl, 11m1
Let t correspond to RO2. Xregl ne'114
pc, ha! Therefore, 5rcL 1nd
ex+ize, 5Lep-aSP+, 5rc2*
5ubscript, l1m1t effective address meter
The SP referenced in the calculation is the value after the increment.
used. Also, INDEX, Act(, 5(II
1ndexsize+stepg&sP+ or
5ubscript. In the case of 11m1t-aSP+, Xr(!lj and °ζ reference
The SP to be compared is the value after the increment.
used. Ken ^1. 5rcl+1ndt+xsfu++5Le
Address calculation of p we>roladdr RRl, 1jroladdr==>5rcl
lRA2. 5rc2.5ubscript, Ji*
jt effective address calculation, > ro2addr RR2, aro2addrvt=> 5rc21EX,
Instruction-specific operations, op, (srclL 5rc21) In INIII'X, op, (Srcl, 5rc21.xre#ri*z
) Xreg 800, SCB', op, (srcll-+ src2Lxreg+ne
eipc) ==> xreg An example of CMP operation is shown in FIG. 382. An example of the operation of IN0E is shown in FIG. 383. However, for [NDIEX instructions, the implementation
Due to the constraint, 5ubscripL=isPl +
In the case of xreg/SP, it does not necessarily work as per the model.
There are cases where it is not possible. For details, see 2.1-Tori ≦ Rensu Four Pestilences
(Refer to the section ``1 bout''. An example of the operation of ACB and SCB is shown in Figure 384.)
: A mouth D src, destADDIJ
src, dest Yaguchi l X sr
c, dasLSOB src, dest SUIIU Src, deSLSIJ[l
X srr,, destMOL src,
dest MOLD src, dest DJV 3rC+ dest DIVU src, dest REM src, dest REMII src, desL^NO3rC1
dest ORsrc, dasL XORsrc, desL SOL count+ desLSOL
counL, desLRO↑ counL,
desL ＾DDDX src, dasLSUBDX
src, destBSCII data,
offsetM[jLX Src1 dest,
tapDfV has src+ desk,
Ls+psrc, counL, dataJttR
Make Ol correspond to dest and offset to MOI
. In the case of 5rc-ijsP4, the effective address of dest
The S11 referenced in the response calculation is the increment
The later value is used. For H^1, specify asP+ and a-5P modes.
It is not possible. 1'1tll, X, in the case of old VX, src is RO Otori, d
est corresponds to MOI, tap is processed in Ex.
Therefore, if 5rc=asI'+,
5P referenced in the effective address calculation of dest
(tff, and the Sll value referenced by L town ν °ζ
, the incremented value is used. Also, ts+
If p and desL specify the same register, tI
Ip's clump disappeared and finally lb! The SL value remains
Become. Effective address of RAl, src, count, daLa
Dress calculation ==> roladdr RRl, arlladdr ==> srclMA
l, dest, offset effective address counter
Sanji ~> s+oladdr MRl, aa+oladdr==> destl
! Mi
>des L2 In MIILX, op, (destL 5rcl) ==>des t
2 + Ltsp In mouth IVX, op, (desLl, 5rcl* Lap) ==>
dest2, Lsp MWl, dest2 =-> ijmoladd
An example of the operation of r800 is shown in Figure 385. Among these, in one heart word, register designation R
flR+ RRM and general addressing specification EaR,l
! In an instruction that includes both aW, ShR, and Sh-, Ra
R, Ear, ShR, ShW asP+, 1i-3
Specified the mode of P and specified sp with RgR and RgM
If [aR. Ea%1. The update of SP value by ShR, Sh- is Rg
Because it affects the readout value of SP as R, RgM,
There is an opinion that pipeline implementation is difficult. Specifically, the following commands are problematic. ^0 mouth: l, asI'+, 5PSOB:
L asl'+, SP CMP: L asP+, 5P INDI! X books, aSP+, SP (MOV:L
) Therefore, the behavior of these instructions is
It depends on the In other words, 800:L asP
4. The sp value after SP execution depends on the implementation.
Let's say it takes an undefined value. It is difficult to detect BIT, so it is not considered BIT. These instructions assume that the abbreviated form has the same behavior as the general form.
This would violate the principle of 'Lt <'t 7 F ad-dress-…, He
, 5s (71A) - Applicable instruction: (IINS enLr3'+ quoII. entry to ^O1, q tl e II e to A
Compatible with O2. The actual operation of the cue link is done in the IjX step.
It will be done. ^^1. anLry effective address calculation 〉ao
laddr A^2. Queue effective address calculation...>a
o2addr MAI-MHl, None EX, instruction-specific operation, op, (aoladdr, ao2addr), z
:C;Yo upper 2-n, upper,-! 14%gsz-7. ．． t
37Jld, (to 1 law applicable instruction: C5I (:0llPI updaLa, dt+
In 5LCSItl, from the relationship with the bit pattern, d
os t corresponds to AOI, update Le corresponds to ROI.
Seru c. The actual operation of SAP access, comparison, and exchange is done in EX.
It is done. What is the assembler notation for C5I instruction operand processing?
Differently, the effective address calculation of update, dest
In this order, calculate the effective address of , and refer to the comp value.
It is done. In dest, asP+, 1-Sl' are used.
cannot be used, but dsI'+ is used in update L (!)
Therefore, when referring to SP with c, o s + p,
caution is required. k^1. updaLe's effective address meter 'm'!
, ->roladdr RRl, 2jroladdr==>updaL
elAAl, effective address calculation of dest...>
aoladdr EX, instruction specific operation, op, 1o1+ddr, updaLel. comp) 7> comp An example of the operation of C81 is shown in FIG. 386. l open read ~ reglisL (R welcome - corresponding order
Order: )', NT! R1ocal, reRIisL[XITD
reglisL, adjspP, NTI! R, [
In XITD, 1oca1. adjsp 'a-ROI
correspond to reglist references and stack frames
System operations are included in the EX step. Therefore, 1
oca1. Referenced when calculating the effective address of adjsp
511. I'11. RO~R13 are stack
It is not the value from the first time when creating a frame of 1m, but it is
The value before the instruction is executed will be used. r, X In ITII, operand in assembler notation
Please note that effective addresses are evaluated in reverse order.
is necessary. (However, due to instruction re-execution, 1oca1.adjs
p is register direct Rn and immediate Ii++ve-
effective address of data mode (unavailable) RAl, 1ocal, adjsp
Calculation ==> roladdr (Actually, only Rn and Iimm-clnLa modes are used.
Since it cannot be used, nothing is accessed in this step.) RRl, 1iroladdr==> 5rc
l[X, reglisL reference and stack frame
In operation ENTER, op, (srcl, RO~R13+ l'P,
SP. realist) ==>PI',Sl', 5Lac
In kEχITO, op, (srcl+FI', SI', 5Lack. reFXIisL), -=> RO~Old 3. Fll. SP, PC l operaf F addre Shujiho L' Nitm,)-9
Applicable commands: LDM src, reglistSTM r
eglisL, desLl, 1) M, in STM
, src, and desL are made to correspond to ^il+. r
eglist reference and actual register transfer are performed using 14X
Include in step. Therefore, “ζ, src, desL”
Sl), l'P referred to during effective address calculation. 4 to R13 are not the values from the start of register transfer.
, the value before the execution of the ζ instruction will be used. LDM reg I ist, asI'4 and STM
Regarding regliSL, 1-5t', there are multiple SPs.
Since it is updated twice, asP+, a-5P in -m instruction
need to be treated differently. i.e. the model
isI'+, d in the "effective address calculation" step of
, s +14 by sl'. ; instead of dealing with updates of
, handle 5ll (Nao no history 1) r in the liX step.
Make it. Therefore, Sl' corresponds to M(+1. (If motes other than ijsl'+, ii, and sl' are used)
If] AA1. Effectiveness of src,, dest
°r address AIIγ==> aoladdr 1iX, re(HIisL reference and register transfer iX
In LDM, d(aolJoldr 〜...) =・>RE[
+(realist) In STM, RP, G(reglist)==>1j(aoladd
r～...) (When using ijsP+, dSl' mode)
MR1, 5P ==> tamaddr EX, reglisL reference and register transfer Ll)
In M, a (tmpaddr~”・) ==>RIEG(te
alist) Lmpaddr Number of registers transferred in 1, >Lmpaddr In STM, Lmpaddr - 1 transfer register failure =->LII
lpaddr anal G (regl ist) = =>iil (t
mpaddr~...) [In actual implementation, the order of register transfer is arbitrary. All you have to do is perform an operation equivalent to this,] MWl, La1IpadtJr = >Sl'
For LDM iiSP+, reglisL, re
Even if a meter is specified during gHsL, the last MWI
Lmpaddr is overwritten by sp in step
As a result, the SP value loaded from memory is deleted.
You will end up with a lot of money. Examples of LDM and STH operation are
As shown in Figure 387. What 3j13. Cache and TLB's fleet @ @ & stem attached
Regarding ensuring the consistency of cache and TLB,
This is explained in the related instructions, but it is not organized.
Then it will look like this: [Consistency when AT is changed: ・TLB, a = physical cache (data cache) alignment
Synthesis - LDC, LDCTX, EIT, RErT p
If AT in sw is changed, TLr (, logical data
The integrity of tag cache 1 is guaranteed. (There is no LSID
If so, it will be purged. If there is LS[D, AT・00
A special 1. Think of it as giving the SID.
If so, it is not necessarily necessary to purge. ) ・Instruction pipeline, instruction cache consistency - instruction code
The state of code integrity remains unchanged. ) Even if T is changed, instruction code consistency is guaranteed.
Not only. (Consistency when operating UATB, 5ATB)
TLBj# Logical cache (data cache) consistency - UATB based on LDC, LDCTX, 5ATFlt
7) Consistency of operation technology, TLB, and logical data cache
is guaranteed. (If there is no LSID, - generally:
・Instruction pipeline, instruction cache consistency - LDC
, LDCTX! ,: UATB, 5ATII 1 mulberry
(However, the state of instruction code integrity does not change. Depending on the implementation, the instruction cache purge may be
Therefore, instruction code consistency may improve in some cases, but
is not guaranteed. For example, in Logic II A, the instruction code for logical space B is
After rewriting each, execute the PIB instruction in the logical space
Then, instruction code consistency in the logical space is guaranteed.
. After this, operate UATB with LDC or LDCTX,
Even if you switch to logical space B, the instruction in logical space B
Code integrity is not guaranteed and cannot be guaranteed.
It is necessary to execute the PIB instruction again in physical space B. However, even if the PTB instruction is executed in logical space 8 (
Also, if you operate UATB again and return to logical space A,
In this case, the consistency of the instruction code is guaranteed. In fact, by purging the logical instruction key,
After T B operation, instruction code consistency is automatically guaranteed.
However, programming does not require this function.
Don't let it happen. In the future, we will introduce LSID and purge.
Considering the avoidance, -i requires operating UATn.
It must be assumed that the instruction code consistency remains the same.
stomach. :, 1TH Consistency when operating H]・TLB, theory
Management cache (data cache) consistency - LDATE operation of ATE; TLB, logic
Data cache consistency is guaranteed. (The affected part will be purged) -1, Do not use DATE, use general memory access instruction
If you can rewrite the memory area used for ATH,
,ru, the consistency of the logical data cache is not guaranteed.
.・Instruction pipeline, instruction cache 1 consistency - ATE
If the ATE is updated, the address will be translated by that ATE.
The area's instruction code integrity is lost.
Even if you execute the memory contents of the area as a program, it will not work.
work is not guaranteed. Does this use the LDATE command?
It doesn't matter what. Restore instruction code integrity
If necessary, execute a separate PIB instruction. [Consistency when performing memory operations] - Consistency of logical cache (data cache) - When accessing memory by logical address
, the consistency of the logical data cache is guaranteed. (Ca
- memory access by physical address using LDP instruction
When accessing the logical data cache, the consistency of the logical data cache is maintained.
Not proven.・Instruction pipeline, instruction cache consistency - memory
If you change the contents, check the "Instruction code consistency" for that area.
- is lost. Is this access by logical address?
It doesn't matter whether the access is by physical address or not.
stomach. Execute the modified memory as a program
To do this, execute the PIB instruction and restore the integrity of the instruction code.
Is there a need to do that? [Effects of the Invention] As described above, according to the present invention, E1'F processing requests are not accepted.
The start address of the EIT processing handler is externally recorded.
At the same time as reading from the storage device, information indicating the internal state is also retrieved.
After entering the EIT processing process, the processor at startup
The internal state of can be set freely. In addition, multiple EIT processing
EIT processing with high priority is processed by EIT with low priority.
Easy to program to prohibit processing
The EIT processing method is also subject to the program creator's own responsibility.
Improved flexibility and ease of use. -C'□'Beast 7 Mortar)

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the register set of the device of the present invention. FIG. 2 is an explanatory diagram of data types for bits of the device of the present invention. FIG. 3 is an explanatory diagram of data types for bit fields of the device of the present invention. FIG. 5 is an explanatory diagram of data types for unsigned bit fields of the device of the present invention. FIG. 6 is an explanatory diagram of data types for decimal numbers of the device of the present invention. FIG. 8 is an explanatory diagram of data types for strings in the device of the present invention. FIG. 9 is an explanatory diagram showing a description example of the command format of the device of the present invention. Figures 11 to 21 are bit pattern diagrams. Figures 11 to 21 are instruction format diagrams of the device of the present invention. Figures 22 to 33 are format diagrams of addressing modes of the device of the present invention. Figure 34 is an example of local variable arrangement of the device of the present invention. 35-38 are addressing mode format diagrams of the device of the present invention. FIG. 39 is an explanatory diagram of precautions for instruction NOV. FIG. 40 is a PSW format diagram. FIG. 41 is a PSS format diagram. FIG. 42 is a format diagram of PSH. FIG. 43 is a format diagram showing an example of instruction set description. FIG. 44 (a) is a format diagram of instruction MOV.
FIG. 45 is a format diagram of the instruction MOVU. FIG. 46 is an explanatory diagram of the flag change. FIG. 47 is a format diagram of the instruction PUSH. FIG. 48 is a diagram of the flag. Figure 49 is an explanatory diagram of changes, and Figure 50 is a format diagram of the instruction POP.
FIG. 51 is an explanatory diagram of the flag change, and FIG. 52 is a format diagram of the instruction LDM.
FIG. 53 is an explanatory diagram of bitmap designation. FIG. 54 is an instruction STM format diagram. FIG. 55 is an explanatory diagram of flag change. FIG. 58 is a format diagram of the instruction MOVA. FIG. 59 is an explanatory diagram of its flag changes. FIG. 60 is a format diagram of the instruction PUSHA. FIG. 61 is an explanatory diagram of its flag changes. Figure 63 is
FIG. 64 is an explanatory diagram of the flag change. FIG. 65 is an explanatory diagram of the flag change. FIG. 66 is a format diagram of the instruction C) IK. FIG. 67 is an explanatory diagram of the flag change. FIG. 68 is an explanatory diagram of the operation of instruction CIIK. FIG. 69 is a format diagram of instruction ADD. FIG. 70 is an explanatory diagram of its flag changes. FIG. 71 is a format diagram of instruction ADDU. An explanatory diagram of changes FIG. 73 is a format diagram of the instruction ADDX FIG. 74 is an explanatory diagram of its flag changes FIG. 75 is a format diagram of the instruction SUB
FIG. 77 is an explanatory diagram of the flag change. FIG. 78 is an explanatory diagram of the flag change. FIG. 79 is a format diagram of the instruction 5UBX. FIG. 80 is an explanatory diagram of the flag change. The figure shows the format of the instruction MUL.
FIG. 83 is an explanatory diagram of the flag change. FIG. 84 is an explanatory diagram of the flag change. FIG. 85 is a format diagram of the instruction MULX. FIG. 86 is an explanatory diagram of the flag change. The figure shows the format of the instruction DIV.
FIG. 89 is an explanatory diagram of the flag change. FIG. 90 is an explanatory diagram of the flag change. FIG. 91 is a format diagram of the instruction DIVX. FIG. 92 is an explanatory diagram of the flag change. The figure shows the format of the instruction REM.
FIG. 96 is an explanatory diagram of the flag change. FIG. 96 is an explanatory diagram of the flag change. FIG. 97 is a format diagram of the instruction NEC.
FIG. 99 is an explanatory diagram of the flag changes, and FIG. 100 is a format diagram of the instruction INDEX.
The figure is an explanatory diagram of the flag change.
102 is an explanatory diagram of the flag change. FIG. 103 is a format diagram of the instruction OR.
FIG. 4 is an explanatory diagram of the flag change. FIG. 105 is an explanation of the flag change.
FIG. 106 is an explanatory diagram of the flag change. FIG. 107 is a format diagram of the instruction NOT.
08 is an explanatory diagram of the flag change. FIG. 109 is a format diagram of the instruction 5t-IA. FIG. 110 is an explanatory diagram of the flag change. FIG. 111 is an explanatory diagram of the left shift. 113 is an explanatory diagram of instruction 5) IL format diagram 114
Figure 115 is an explanatory diagram of the flag change. Figure 116 is an explanatory diagram of the right shift. Figure 117 is a format diagram of the instruction ROT. Figure 118 is an explanatory diagram of the flag change. FIG. 119 is an explanatory diagram of left rotation. FIG. 120 is an explanatory diagram of right rotation. FIG. 121 is a format diagram of instruction 5HXL.
Figure 123 is an explanatory diagram of the flag change.
FIG. 124 is a format diagram of instruction XHXR. FIG. 125 is an explanatory diagram of its flag changes. FIG.
FIG. 7 is a format diagram of the instruction RVBY. FIG. 128 is a format diagram of the instruction RVBY.
FIG. 129, an explanatory diagram of the flag change, shows the instruction RVB +
FIG. 130 is an explanatory diagram of the flag change. FIGS. 131 and 132 are an explanatory diagram of the bit manipulation instruction. FIG. 133 (ffl) is a format diagram of the instruction BTST. FIG. 135 is a format diagram of the instruction BSET FIG. 136 is an explanatory diagram of its flag changes FIG. 137 is a format diagram of the instruction BCLR FIG. 138 is an explanatory diagram of its flag changes FIG. 139 is a format of the instruction BNOT FIG. 140 is an explanatory diagram of the flag change. FIG. 141 is a format diagram of the instruction BSCH. FIG. 142 is an explanatory diagram of the flag change.
FIG. 43 is an explanatory diagram of a fixed-length bit field manipulation instruction. FIG. 144 is a format diagram of a bit field instruction. FIG. 145 is a format diagram of the instruction BFEXT.
FIG. 6 is an explanatory diagram of the flag change. FIG. 147 is an explanation of the flag change.
A format diagram of FEXTU (FIG. 148) is an explanatory diagram of its flag changes.FIG. 149 is an explanatory diagram of its flag changes.FIG. 150 is an explanatory diagram of its flag changes.
Figure 51 is the first format diagram of the instruction BF I NSυ.
FIG. 52 is an explanatory diagram of the flag change. FIG. 153 is a format diagram of the instruction BFCMP. FIG. 154 is an explanatory diagram of the flag change. FIG. 155 is a format diagram of the instruction BFCMPU. Explanatory diagram No. 15
FIG. 7 is a format diagram of the instruction BVSCH. FIG. 158 is an explanatory diagram of its flag changes. FIG. 159 is an instruction 8VMA
160 is an explanatory diagram of the flag changes. FIG. 161 to 163 are the format diagram of the instruction BVMAP(7). FIG. 164 is a format diagram of the instruction BVCPY.
FIG. 5 is an explanatory diagram of the flag change. FIG. 166 is an explanation of the flag change.
A format diagram of VFAT Figure 167 is an explanatory diagram of the flag changes. Figure 168 is a format diagram of the instruction ADDDX. Figure 169 is an explanatory diagram of the flag changes. Figure 170 is a format diagram of the instruction 5IJ80X. ,
FIG. 172, an explanatory diagram of the flag change, shows the instruction PACKs
173 is a format diagram of ss. FIG. 174 is a format diagram of ss for the instruction UNP. FIG. 175 is an explanatory diagram of flag changes.
FIG. 177 is an explanatory diagram of the instruction UNPKss.
FIG. 178 is an explanatory diagram of the flag change. FIG. 179 is an explanatory diagram of the instruction SCMP. FIGS. 180 and 181 are explanatory diagrams of the flag change.
Figure 184 is an explanatory diagram of the flag change.
A format diagram of TR (FIG. 185) is an explanatory diagram of its flag changes. FIG. 186 is a format diagram of the instruction QINS. FIG. 187 is an explanatory diagram of its flag changes.
Figure 191 is an explanatory diagram of the instruction QINS.
FIG. 192 is an explanatory diagram of the flag change, and FIG. 193 is an explanatory diagram of the instruction QDEL.
FIG. 96 is a format diagram of the instruction QSCH. FIG. 197 is an explanatory diagram of its flag changes. FIGS. 198 to 200 are explanatory diagrams of the instruction QSCH. FIG. 201 is a format diagram of the instruction BRA. Explanatory diagram No. 203
204 is an explanatory diagram of the flag change. FIG. 205 is a format diagram of the instruction BSR. FIG. 206 is an explanatory diagram of the flag change.
FIG. 7 is a format diagram of the instruction JMP. FIG. 208 is an explanatory diagram of its plug changes. FIG. 209 is a format diagram of the instruction JSR. FIG. 210 is an explanatory diagram of its flag changes.
11 shows the format of the instruction ACB. FIG. 212 shows an explanation of its flag changes. FIG. 213 shows an explanation of the instruction ACB. FIG. 214 shows the format of the instruction SCB. Figure 216 shows the instruction ENT
217 is an explanatory diagram of the format of ER, and FIG. 218 is an explanatory diagram of the instruction ENTER.
FIG. 220 is an explanatory diagram of the instruction EX I TD. FIG. 220 is an explanatory diagram of its flag change. FIG. 221 is an explanatory diagram of the instruction EX I TO.
FIG. 222 is an explanatory diagram of the format of the instruction RTS. FIG. 223 is an explanatory diagram of its flag changes. FIG. 224 is a format diagram of the instruction NOP. FIG. 225 is an explanatory diagram of its flag changes. FIG. 227 is a format diagram of the instruction PIB, and FIG. 228 is an explanatory diagram of flag changes.
A format diagram of the instruction BSET+ FIG. 229 is an explanatory diagram of its flag changes. FIG. 230 is a format diagram of the instruction BCLRI. FIG. 231 is an explanatory diagram of its flag changes.
FIG. 32 is a format diagram of instruction C51. FIG. 233 is a format diagram of instruction C51.
FIG. 234 is an explanatory diagram of the flag change. FIG. 235 is an explanatory diagram of the flag change. FIG. 236 is a format diagram of the instruction STC. FIG. 237 is an explanatory diagram of the flag change. The figure shows the instruction LDPS
B format diagram FIG. 239 is an explanatory diagram of the flag change. FIG. 240 is a format diagram of the instruction LDPSM. FIG. 241 is an explanatory diagram of the flag change. FIG. 242 is a format diagram of the instruction 5TPSB. , FIG. 244 is an explanatory diagram of the flag change. FIG. 245 is an explanatory diagram of the flag change.
FIG. 6 is a format diagram of the instruction LDP. FIG. 247 is an explanatory diagram of its flag changes. FIG. 248 is a format diagram of the instruction STP. FIG. 249 is an explanatory diagram of its flag changes.
FIG. 50 is a format diagram of the instruction JRNG. FIG. 251 is an explanatory diagram of its flag changes. FIGS. 252 to 257 are format diagrams of the instruction JRNG.
Figures 260-262 are explanatory diagrams of the flag changes.
FIG. 263 is an explanatory diagram of the instruction RRNG. FIG. 264 is an explanatory diagram of its flag changes. FIG. 265 is a format diagram of the instruction TRAP.
FIG. 267 is an explanatory diagram of the flag change.
FIG. 269 is a format diagram of the instruction REIT. FIG. 270 is a format diagram of the instruction WAIT. FIG. 271 is an explanatory diagram of the flag change. , instruction LDC
TX format diagram FIG. 273 is an explanatory diagram of its flag changes. FIG. 274 is a format diagram of instruction 5TCTX. FIG. 275 is an explanatory diagram of its flag changes.
277 is a format diagram of the instruction AC5. FIG. 278 is a format diagram of the instruction MOVPA. FIG. 279 is an explanatory diagram of the flag changes.
, 281 shows the instruction MOVPA(7)
Figure 282 is an explanatory diagram of the command LDATE, Figures 283 and 28.
Figure 4 is an explanatory diagram of the flag change. Figure 285 is a format diagram of the instruction 5TATE.
6,287 is an explanatory diagram of the flag change. FIG. 288 is a format diagram of the instruction PTLB.
Figure 290 is an explanatory diagram of the flag change.
TLB format diagram Figure 291 is an explanatory diagram of its flag changes. Figure 292 is an explanatory diagram of the AT field.
Figure 3 is an explanatory diagram of logical addresses. Figure 294 is an explanatory diagram of page addresses. Figure 295 is an explanatory diagram of logical addresses.
FIG. 296 is an explanatory diagram of the multiplexed logical space. FIG. 297 is an explanatory diagram of the UATB format. FIG. 298 is an explanatory diagram of SX restrictions. Figure 303 is an explanatory diagram showing Px restrictions. Figure 304 is an explanatory diagram of STE. Figure 305 is an explanatory diagram of logical addresses. Figure 306 is a PTE format diagram. teeth,
FIG. 308 is an explanatory diagram showing the relationship between each value of PTE and an accessible ring. FIGS. 309 and 310 are an explanatory diagram of PTE. FIG. Fig. 312 is an explanatory diagram of flag changes in comparison test instructions. Fig. 313 is an explanatory diagram of flag changes in arithmetic operation instructions. Fig. 314 is an explanatory diagram of flag changes in logical operation instructions. is an explanatory diagram of flag changes in a shift instruction. Figure 316 is an explanatory diagram of flag changes in a bit manipulation instruction. Figures 317 and 318 are explanatory diagrams of flag changes in a fixed table bit field instruction. Figure 319 is an illustration of an arbitrary table bit Fig. 320 is an explanatory diagram of flag changes in decimal operation instructions. Fig. 321 is an explanatory diagram of flag changes in string instructions. Fig. 322 is an explanatory diagram of flag changes in queue operation instructions. FIG. 323 is an explanatory diagram of a flag change of a jump instruction. FIG. 324 is an explanatory diagram of a flag change of a multiprocessor instruction. FIG. 325 is an explanatory diagram of a flag change of a control space and physical space manipulation instruction. FIG. 327 is an explanatory diagram of flag changes of related instructions. FIG. 328 is an explanatory diagram of subroutine calls. FIG. 329 is an explanatory diagram of staff complaints.
FIG. 332 is an explanatory diagram of an instruction sequence. FIG. 333 is an explanatory diagram of a subroutine call. FIG. 334 is an explanatory diagram of a control space. FIG. 335 is a PSW format diagram.
Format diagram Figure 337 for IMAs is SMRNG
338 is a format diagram of CTXBB, 339 is a format diagram of Dl, 340 is a format diagram of C5W, 341 is a format diagram of C5W,
[) CE format diagram Figure 342 is CTXBFM
Figure 343 is the format diagram of EITVB. Figure 344 is the format diagram of JRNGVB (7) Fut-Matsu). Figure 345 is the format diagram of spo~SP3. Figure 346 is the format diagram of SP+. Figure 347 is the format diagram of SP+. , l0ADDR, IOMAS format diagram No. 34
Figure 8 is a UATB format diagram. Figure 349 is 5A.
The TB format diagram (Figure 350) is the LSI0 format diagram (Figure 351) is the CTXB format diagram (Figure 3).
Figure 52 is a CTXBFM format diagram. Figure 353 is an EITVTE format diagram. Figure 354 is a staff claim explanatory diagram. Figures 355 and 356 are EIT stack format diagrams. Figure 359 shows the EIT vector table.
Figures 360 and 361 are explanatory diagrams of EIT, and Figure 362 is an explanatory diagram of EIT.
An explanatory diagram of IMAS Figures 363 and 364 are an explanatory diagram of system calls. Figure 365 is an explanatory diagram of DCE. Figure 366 is a comparison whistle of DCE, DI, and El. Figure 368 is a bit allocation diagram Figure 369 is an operand field name index diagram Figure 370
371: cccc assignment whistle 371: eeee assignment whistle: 372: Mflag explanatory diagram: 373: BVMAP instruction operation code diagram: 374
Figure 376 is a correspondence diagram of the addressing mode with operands. Figure 376 is an explanatory diagram of Pu5) IA @ SP, etc.
Figure 77 is an explanatory diagram of the POP command. Figure 378 is an explanatory diagram of the MOV command. Figure 379 is an explanatory diagram of the PAC command, etc..
FIG. 381 is an explanatory diagram of the STC command, etc. FIG. 382 is an explanatory diagram of the CMP command. Fig. 383 is an explanatory diagram of the IN[)EX instruction Fig. 384 is an explanatory diagram of the Ace instruction etc. Fig. 385 is an explanatory diagram of the ADD instruction Fig. 386 is an explanatory diagram of the CS+ instruction Fig. 387 is an explanatory diagram of the LDM Explanatory diagrams of commands, etc. FIG. 388 is a flowchart 1 of the EIT processing startup method in the conventional data processing device, FIG. 389 is a flowchart of the EIT processing startup method in the data processing device of the present invention, and FIG. FIG. 391 is a diagram showing the format of EITVTE that includes the start address of the EIT processing handler fetched from the external storage device and part of the internal state variables of the data processing device when EIT processing occurs in the data processing device. FIG. 392 is a diagram showing a stack format formed when EIT processing is started in a data processing device according to the present invention. FIG. 393 is a diagram showing a stack format according to the type of EIT processing in a data processing device according to the present invention. Data processing device has multiple EI
FIG. 3 is a diagram showing a stack format formed when performing T processing, and data of PC and PSW. 1001-1006... Processing details of each step of EIT processing in the device of the present invention 1007-1011... Processing details of each step of EIT processing in the conventional data processing device 1020... Stack pointer usage mode after EIT processing 1-bit data 1021 indicating the designation of the address conversion mode after EIT processing 1-bit data 1022 ... indicating whether the data size of the context after EIT processing is 32 bits or 64 bits 2 indicating the specification of the address conversion mode after EIT processing Bit data 1023...Indicates the presence or absence of debug mode after EIT processing 1-bit data 1024...4-bit data 1027 that specifies the interrupt acceptance priority level after EIT processing... 1-byte data 102B indicating the type of stack format according to the type 1-byte data 1029 indicating the type of EIT processing 10 indicating the EIT vector number
Bit data 1030...Value of the PC of the data processing device at the time EIT processing occurred 1031...Several byte area to store various additional information depending on the type of EIT processing! 032~! 035...Stack format formed by various EIT processes of the data processing device in one embodiment of the present invention 1036...Final PC value when multiple single EIT occurs 1037...Multiple EIT Final P at the time of occurrence
SW value 1038 to 1044...Stack format formed when multiple EIT processing occurs

Claims (1)

[Scope of Claims] 1. In a data processing device that processes a program consisting of a plurality of instructions, means for detecting interrupt processing by receiving an interrupt request signal from the outside at the boundary between each instruction processing; and an instruction exception event. and a means for detecting trap processing, which is the execution of an internal interrupt instruction, and a plurality of E
Each IT process has its own priority and processing method.
A means for selecting whether to start an IT process, and an internal state including a first information group that is the state at the time when the selected EIT process is started and is to be rewritten when the EIT process is started, to an external storage device. storage means, and an address of the external storage device in which the start address of the EIT processing handler that is to execute a series of processes corresponding to the selected EIT processing is stored on a one-to-one basis for each of the selected EIT processing. and means for generating the EIT at the address of the generated external storage device.
Along with the start address of the processing handler, the second information group that is a candidate to become part or all of the new internal state at the start of execution of the upper EIT processing handler is added to the selected EI.
A data processing device characterized in that a part or all of T processes are stored one-to-one. 2. A means for reading out the second information group in the selected EIT process, and comparing the first information group and the second information group to determine the third information group that is part or all of the new internal state. 2. The data processing apparatus according to claim 1, further comprising means for determining the value of part or all of the information group. 3. means for reading a second information group in the selected EIT process; a first interrupt priority indicated in the interrupt request signal and a second interrupt priority that is part of the second information group; and determining a third interrupt priority that is part of a third information group that is part or all of the new internal state. Device. 4. When the data processing device is in a certain first internal state and at least two EIT processes are detected simultaneously, the first EIT process with the higher priority is started according to the inherent priority, and the first EIT process is activated. A patent claim for making a new judgment as to whether or not to detect a second EIT process with a lower priority that is simultaneously detected in a second internal state before executing the first instruction of a processing program for EIT processing. The data processing device according to scope 1. 5. It has a dedicated return instruction that returns the EIT processing handler to the program that was being executed when the EIT processing handler was started, and the EIT processing detection conditions are different between immediately after execution of the above dedicated return instruction and immediately after execution of other instructions. 2. A data processing device according to claim 1, characterized in that: