JPH0191665A - Controlling circuit of pwm system inverter - Google Patents
Controlling circuit of pwm system inverterInfo
- Publication number
- JPH0191665A JPH0191665A JP62247028A JP24702887A JPH0191665A JP H0191665 A JPH0191665 A JP H0191665A JP 62247028 A JP62247028 A JP 62247028A JP 24702887 A JP24702887 A JP 24702887A JP H0191665 A JPH0191665 A JP H0191665A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- amplitude
- value
- inverter
- pwm
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000009499 grossing Methods 0.000 abstract description 2
- 239000003990 capacitor Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229920006395 saturated elastomer Polymers 0.000 description 2
- 239000013256 coordination polymer Substances 0.000 description 1
Landscapes
- Inverter Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、パルス幅変調方式インバータの制御回路に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control circuit for a pulse width modulation type inverter.
パルス幅変ＸＩ（ＰＷＭ）方式のインバータの出力電圧
は、インバータ主回路の直流電圧と、インバータ主回路
を構成するスイッチング素子のオン。The output voltage of a pulse width variable XI (PWM) type inverter is the DC voltage of the inverter main circuit and the ON state of the switching elements that make up the inverter main circuit.
／オフ時間比との積に比例するので、上記直流電圧が変
動すると上記出力電圧も変動する。この直流電圧は、通
常、受電電圧（商用電源電圧）を整流装置で直流変換し
て得るので、リップル変動分があり、そのままでは、出
力電圧の変動は避けられず、従来、何らかの補正もしく
は修正手段を設けて交流出力電圧の変動を抑制している
。/OFF time ratio, so when the DC voltage fluctuates, the output voltage also fluctuates. This DC voltage is usually obtained by converting the received voltage (commercial power supply voltage) into DC using a rectifier, so there is a ripple fluctuation. is installed to suppress fluctuations in the AC output voltage.
第２図は、この種の補正手段を設けた従来のＰＷＭ方式
単相インバータの１例を示したものである。同図におい
て、１は商用電源、２は全波整流装置、３は平滑用コン
デンサ（電解コンデンサ）、４は正弦波変ＩＰＷＭ方式
の単相トランジスタインバータ（以下、ＰＷＭインバー
タという）、５はインバータ負荷、例えば；電磁振動機
の駆動コイルである。FIG. 2 shows an example of a conventional PWM single-phase inverter equipped with this type of correction means. In the figure, 1 is a commercial power supply, 2 is a full-wave rectifier, 3 is a smoothing capacitor (electrolytic capacitor), 4 is a sine wave variable IPWM type single-phase transistor inverter (hereinafter referred to as PWM inverter), and 5 is an inverter load. , for example; a drive coil for an electromagnetic vibrator.
６はＰＷＭインバータ４の直流回路の電圧を検出する直
流電圧検出器であって、コンデンサ３の両端の直流電圧
ＥＤを検出する。７はゲイン設定器（但し、この例では
、ゲインに＝１とする）、８は乗算器、９は三角波信号
発生器である。三角波信号発生器９は定振幅の三角波信
号ｖｃｏを発生し、乗算器８からは振幅がＥＤである可
変振幅の三角波信号（搬送波となる）ｖｃ （第３図に
実線で示す）が取り出される。１０は電圧指令Ｖ″を作
成する電圧指令器、１１は周波数指令Ｆ”を作成する周
波数指令器、１２は正弦波信号発生器、１３は乗算器で
ある。正弦波信号発生器１２は周波数指令Ｆ′″に相当
する周波数の正弦波信号Ｖ。A DC voltage detector 6 detects the voltage of the DC circuit of the PWM inverter 4, and detects the DC voltage ED across the capacitor 3. 7 is a gain setter (however, in this example, the gain is set to 1), 8 is a multiplier, and 9 is a triangular wave signal generator. A triangular wave signal generator 9 generates a constant amplitude triangular wave signal vco, and a variable amplitude triangular wave signal (to be a carrier wave) vc (shown by a solid line in FIG. 3) having an amplitude ED is taken out from a multiplier 8. 10 is a voltage command device that creates a voltage command V'', 11 is a frequency command device that creates a frequency command F'', 12 is a sine wave signal generator, and 13 is a multiplier. The sine wave signal generator 12 generates a sine wave signal V having a frequency corresponding to the frequency command F'''.
を作成し、乗算器１３からは、振幅が電圧指令Ｖ“の大
きさに比例する電圧信号（変調波となる。第３図に実線
で示す）ｖｌが取り出される。, and the multiplier 13 takes out a voltage signal vl (which becomes a modulated wave, shown by a solid line in FIG. 3) whose amplitude is proportional to the magnitude of the voltage command V".
１４はＰＷＭ信号を作成する比較器であって、電圧信号
■１と三角波信号■。とを比較して、ｐｗＭ信号を作成
する。このＰＷＭ信号を受けてトランジスタドライバ１
５がＰＷＭインバータ４の各トランジスタをオン・オフ
駆動する。14 is a comparator for creating a PWM signal, which is a voltage signal (1) and a triangular wave signal (2). A pwM signal is created by comparing the Transistor driver 1 receives this PWM signal.
5 turns each transistor of the PWM inverter 4 on and off.
この構成では、三角波信号Ｖｃの振幅を直流電圧ＥＤに
追随させて、直流電圧Ｅ０の電圧リップルによるインバ
ータ出力電圧の変動や、受電電圧の小中の変動によるイ
ンバータ出力電圧の変動を防止しているが、客先が要求
する受電電圧許容変動幅が大きくなると（例えば、２０
０ボルト系統受電の場合、２００ｖ−１５％〜２００＋
１０％）、受電電圧が大きく変動して直流電圧ＥＤが大
幅に低下し、第３図に点線で示すように、三角波信号Ｖ
ｃのピーク値Ｖ。、が電圧信号Ｖ′″より小さくなるモ
ードが生ずる場合がある。このようなモードが生ずると
、ＰＷＭインバータ４の出力電圧波形が飽和波形となっ
て歪むので、インバータ負荷５が電磁振動機の駆動コイ
ルである場合には、騒音が発生し、また、交流電動機で
ある場合にはトルクリップルが発生する。In this configuration, the amplitude of the triangular wave signal Vc is made to follow the DC voltage ED, thereby preventing fluctuations in the inverter output voltage due to voltage ripples in the DC voltage E0 and fluctuations in the inverter output voltage due to small to medium fluctuations in the receiving voltage. However, if the permissible fluctuation range of the received power voltage requested by the customer becomes large (for example, 20
In the case of 0 volt system power reception, 200v-15% ~ 200+
10%), the received voltage fluctuates greatly and the DC voltage ED drops significantly, causing the triangular wave signal V to drop as shown by the dotted line in Figure 3.
The peak value V of c. , may be smaller than the voltage signal V'''. When such a mode occurs, the output voltage waveform of the PWM inverter 4 becomes a saturated waveform and is distorted, so that the inverter load 5 is forced to drive the electromagnetic vibrator. If it is a coil, noise will be generated, and if it is an AC motor, torque ripple will be generated.
この発明は上記問題を解消するためになされたもので、
受電電圧が大幅に低下しても、インバータ出力波形を歪
ませることなく、しかも出力の電圧変動を防止してイン
バータを運転することができるＰＷＭ方式インバータの
制御回路を提供することを目的とする。This invention was made to solve the above problem.
To provide a control circuit for a PWM type inverter capable of operating an inverter without distorting an inverter output waveform and preventing output voltage fluctuations even if the received power voltage is significantly reduced.
この発明は上記目的を達成するため、搬送波を、その振
幅がインバータ主回路の直流電圧値に比例する可変振幅
の搬送波としてインバータ出力電圧を制御する場合に、
上記搬送波の上記振幅が変調波の振幅を指令する電圧指
令値より小さくなると、該電圧指令値に代えて上記搬送
波の振幅を用いる構成としたものである。In order to achieve the above object, the present invention controls an inverter output voltage by using a carrier wave as a variable amplitude carrier wave whose amplitude is proportional to the DC voltage value of the inverter main circuit.
When the amplitude of the carrier wave becomes smaller than the voltage command value that commands the amplitude of the modulated wave, the amplitude of the carrier wave is used instead of the voltage command value.
この発明では、可変振幅搬送波の振幅が変調波の振幅に
比して小さくなると、電圧指令値として上記搬送波の振
幅値が用いられるので、主回路直流電圧が低くても、電
圧指令値に対して主回路直流電圧が不足せず、インバー
タ出力波形が飽和波形となって歪むことはない。In this invention, when the amplitude of the variable amplitude carrier wave becomes smaller than the amplitude of the modulated wave, the amplitude value of the carrier wave is used as the voltage command value, so even if the main circuit DC voltage is low, the voltage command value The main circuit DC voltage will not be insufficient, and the inverter output waveform will not become a saturated waveform and be distorted.
以下、本発明の一実施例を図面を参照して説明する。 Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
第１図において、１６は最少値選択器であって、ゲイン
設定器７の出力ＥＤ ＸＫ＝ＶＣＰと電圧指令■２を取
り込んで、両者のうち値の小さい方を選択して出力する
。この最少値選択器１６の出力が正弦波信号Ｖ、に乗ぜ
られて電圧信号ｖ９が作成され、該電圧信号ｖ９が比較
器１４で三角波信号Ｖ、と比較される。他の構成は第２
図のものと同じであるので、同一構成要素には同一符号
を付しである。In FIG. 1, 16 is a minimum value selector which takes in the output EDXK=VCP of the gain setter 7 and the voltage command 2, selects the smaller value of the two, and outputs the selected value. The output of the minimum value selector 16 is multiplied by the sine wave signal V to create a voltage signal v9, and the voltage signal v9 is compared with the triangular wave signal V by the comparator 14. Other configurations are second
Since it is the same as that in the figure, the same components are given the same reference numerals.
この構成においては、今、ゲイン設定器７のゲインに＝
１とすると、電圧指令ｖ９の値が直流電圧Ｅ、の値より
小さい場合は、最少値選択器１６が電圧指令Ｖ′の値を
選択するＱで、電圧信号ｖ”のピーク値は従来の場合と
同様に■４の大きさとなる。逆に、電圧指令Ｖ“の値が
直流電圧ＥＤの値より大きい場合は、最少値選択器１６
が直流電圧Ｅ０の値を選択するので、電圧信号ｖ１の振
幅はＥ、となる。In this configuration, the gain of gain setter 7 is now =
1, when the value of the voltage command v9 is smaller than the value of the DC voltage E, the minimum value selector 16 selects the value of the voltage command V'. Similarly, it becomes the magnitude of ■4. Conversely, if the value of the voltage command V" is larger than the value of the DC voltage ED, the minimum value selector 16
selects the value of the DC voltage E0, so the amplitude of the voltage signal v1 becomes E.
即ち、本実施例では、可変振幅の三角波信号Ｖ、の振幅
Ｖｅｒ＝ＫＸＥｎが、直流電圧Ｅ、の大幅な下降変動に
より、電圧信号Ｖ″′の振幅（電圧指令ｖ″の大きさ）
より低下し、三角波信号■。That is, in this embodiment, the amplitude Ver=KXEn of the variable amplitude triangular wave signal V, changes to the amplitude of the voltage signal V''' (the magnitude of the voltage command v'') due to the large downward fluctuation of the DC voltage E.
■ The triangle wave signal drops more.
が第３図に実線で示す波形から同図に点線で示す波形に
変化した場合には、電圧指令がＶ“からＶＣＰに切換わ
って、電圧信号ｖ８の振幅が”ＣＰに絞られ、電圧信号
ｖｌｌが第３図に鎖線で示す波形に変化するので、ＰＷ
Ｍインバータ４は振幅を電圧指令値ＶＣＰの大きさとす
る歪のない交流出力電圧を送出する。When the waveform shown by the solid line in Figure 3 changes to the waveform shown by the dotted line in the same figure, the voltage command switches from V to VCP, the amplitude of the voltage signal v8 is narrowed to CP, and the voltage signal Since vll changes to the waveform shown by the chain line in Figure 3, PW
The M inverter 4 sends out a distortion-free AC output voltage whose amplitude is equal to the voltage command value VCP.
なお、この発明はＰＷＭ方式の多相インバータに適用し
て同様の効果を得ることができる。Note that the present invention can be applied to a PWM type multiphase inverter to obtain similar effects.
この発明は以上説明した通り、振幅がインパーク直流入
力電圧に比例して変化する可変振幅搬送波の該振幅が、
変調波の振幅より低下した場合には、該変調波の振幅を
可搬送波の振幅値と同じ値まで絞るので、インバータ主
回路の受電電圧が大幅に下降変動しても、歪がなく、し
かも電圧変動のないインバータ出力電圧を確保すること
ができる。As explained above, in this invention, the amplitude of a variable amplitude carrier wave whose amplitude changes in proportion to the impark DC input voltage is
When the amplitude of the modulated wave is lower than the amplitude of the modulated wave, the amplitude of the modulated wave is narrowed down to the same value as the amplitude of the carrier wave, so even if the receiving voltage of the inverter main circuit fluctuates significantly, there is no distortion and the voltage remains constant. It is possible to ensure an inverter output voltage that does not fluctuate.
第１図はこの発明の実施例を示すブロック図、第２図は
ＰＷＭインバータの従来の制御回路を示すブロック図、
第３図は波形図である。
４−・ＰＷＭインバータ、６−・直流電圧検出器、９・
−・三角波信号発生器、１０・−電圧指令器、１１−周
波数指令器、１２−・・正弦波信号発生器、１４−比較
器、１６−・最少値選択器。FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a conventional control circuit for a PWM inverter,
FIG. 3 is a waveform diagram. 4-・PWM inverter, 6-・DC voltage detector, 9・
- Triangular wave signal generator, 10 - Voltage command unit, 11 - Frequency command unit, 12 - Sine wave signal generator, 14 - Comparator, 16 - Minimum value selector.
Claims (1)
比例する可変振幅の搬送波としてインバータ出力電圧を
制御するＰＷＭ方式インバータの制御回路において、上
記搬送波の上記振幅が変調波の振幅を指令する電圧指令
値より小さい場合には、該電圧指令値に代えて上記搬送
波の振幅を用いることを特徴とするＰＷＭ方式インバー
タの制御回路。In a control circuit for a PWM inverter that controls an inverter output voltage by using a carrier wave as a variable amplitude carrier wave whose amplitude is proportional to a DC voltage value of an inverter main circuit, the amplitude of the carrier wave is a voltage command that commands the amplitude of a modulated wave. A control circuit for a PWM inverter, characterized in that when the voltage command value is smaller than the voltage command value, the amplitude of the carrier wave is used instead of the voltage command value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62247028A JPH0813189B2 (en) | 1987-09-30 | 1987-09-30 | PWM inverter control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62247028A JPH0813189B2 (en) | 1987-09-30 | 1987-09-30 | PWM inverter control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0191665A true JPH0191665A (en) | 1989-04-11 |
| JPH0813189B2 JPH0813189B2 (en) | 1996-02-07 |
Family
ID=17157329
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62247028A Expired - Fee Related JPH0813189B2 (en) | 1987-09-30 | 1987-09-30 | PWM inverter control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0813189B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008022636A (en) * | 2006-07-13 | 2008-01-31 | Fuji Electric Holdings Co Ltd | Pulse-width modulating method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5740372A (en) * | 1980-08-22 | 1982-03-05 | Fuji Electric Co Ltd | Control system for voltage type pulse width modulation inverter |
| JPS62203567A (en) * | 1986-02-28 | 1987-09-08 | Mitsubishi Electric Corp | Control circuit for inverter apparatus |
-
1987
- 1987-09-30 JP JP62247028A patent/JPH0813189B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5740372A (en) * | 1980-08-22 | 1982-03-05 | Fuji Electric Co Ltd | Control system for voltage type pulse width modulation inverter |
| JPS62203567A (en) * | 1986-02-28 | 1987-09-08 | Mitsubishi Electric Corp | Control circuit for inverter apparatus |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008022636A (en) * | 2006-07-13 | 2008-01-31 | Fuji Electric Holdings Co Ltd | Pulse-width modulating method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0813189B2 (en) | 1996-02-07 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |