JPH01844A - C/N measurement circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a C/N measuring circuit that measures carrier power to noise power ratio (C/' N ), and is particularly applicable to digital communications employing error correction control. This invention relates to a C/N measurement circuit suitable for the system.

(Prior Art) In digital communication systems, in order to evaluate the performance of a demodulator or the entire transmission path including the demodulator, transmission information 1 is used as a figure of merit for the bit error rate (BER) of the code decoded by the demodulator. The ratio of energy per bit to noise power density (Eb/No) is defined, and this is obtained by calculation as shown in the following equation (1).

Danshi=Tachi・JL −・−・−−−−−−−
--------・(1) N, NR where C/N is the carrier power to noise power ratio, B is the equivalent noise bandwidth of the demodulator, R is the data transmission rate, and 2-PSK
The modulation method matches the symbol rate, but 4-PSK
It is well known that the modulation method is twice the symbol rate.

By the way, as is clear from equation (1), it is necessary to measure C/N in order to obtain Eb/No. Therefore, for example, in the case of determining E 11 /' N 6 in a satellite link, the conventional C/N measurement method uses a band in front of the demodulator 21, which has a narrower band than the satellite repeater, as shown in FIG. A pass filter 20 is arranged to measure the C/N in the IF band of the input of the demodulator 21 into which the received f-p modulation signal is input.

The measurement procedure is first to transmit an unmodulated wave or a modulated wave to the center of the band of the bandpass filter 20, measure the output power of the bandpass filter 20, and obtain C+N. next,
The bandpass filter 20 is configured by stopping the transmission of unmodulated waves or modulated waves, or by shifting the transmission carrier frequency so that the received signal is outside the band of the bandpass filter 20.
Measure the output power of and find N. Then, C is found by subtracting N from the previously found C+N, and C/N is found from both. Note that B in this case is the equivalent noise bandwidth of the bandpass filter 20.

(Problems to be Solved by the Invention) However, the conventional C/N measurement method described above has the following various problems.

First, a bandpass filter whose accurate equivalent noise bandwidth is known is required for measurement, and a separate measuring device such as a power meter is required.

In addition, in C/N measurement, an unmodulated wave or a modulated wave is transmitted, and operations to stop it or shift the frequency are performed in the IF band, which not only makes the operation complicated, but also makes C/N measurement difficult during operation. Difficult to do.

Therefore, in order to solve this problem, the applicant proposed the fourth
We have developed and applied for a C/N measurement circuit as shown in the figure (unpublished). In Figure 4, 1 is an A/I) converter, 6 (9)
) is the first (second) averaging circuit, and 7 (8) is the first (second) averaging circuit.
), 10 is a subtraction circuit, 11 is a C/N conversion circuit, and 12 is an absolute value manipulation circuit.

The operation of this C/N measuring circuit is roughly as follows. That is, the demodulated signal (analog signal forming an eye pattern) received and demodulated becomes time series data that is digitally quantized by the A/D converter 1, and this is transmitted to the absolute value manipulation circuit 12 and the first averaging circuit 6. , the absolute value of each is taken in the first squaring circuit 7, the average is taken over a sufficiently long N (an integer of Neo) symbols, and then the value is squared.

Here, the output value of the first square operation circuit 7 can be expressed by the following equation (2), which represents the power S of the demodulated signal when there is no noise.

S=(+-redundant1dil)2 −・・・−・−・(
2) Here, d+ (i=0.1, 2, . . . ) is time series data digitally converted by the A/D converter 1.

On the other hand, the time series data digitally quantized by the A/D converter 1 is sent to a second square operation circuit 8, a second averaging circuit 9,
In the subtraction circuit 10, each squared, sufficiently long N
After being averaged over (N>O integer) symbols, the output value of the first squaring circuit 7 is subtracted. The output value of this subtraction circuit 10 can be expressed by the following equation (3), which has noise power 62 added to the demodulated signal.

As a result, in the C/N conversion circuit 11, the output of the first square operation circuit 7 (the power S of the demodulated signal when there is no noise) and the output of the subtraction circuit 10 (the noise power σ2 added to the demodulated signal
), a measured value of C/N can be obtained.

In this way, the C/N measurement circuit developed by the applicant is
Since the measured C/N can be obtained by performing digital numerical calculations on the demodulated signal, the C/N can be easily measured during operation. However, this C/N measuring circuit has a problem in that accurate measured values cannot be obtained under low C/N conditions. This problem will be explained below using a binary digital demodulated signal as an example.

In FIG. 5, under high C/N conditions, the probability density distribution of the amplitude value of the demodulated signal exhibits a Gaussian distribution as shown by a curve 14 centered on the signal imaginary point WA. Even if the demodulated signal is returned to the signal point position A side, a distribution similar to curve 14 will be obtained. In this case, the average amplitude of the demodulated signal sequence is approximately equal to the amplitude at signal point position A. However, under low C/N conditions,
The noise power added to the received signal, that is, the variance σ in the Gaussian distribution increases, and the probability density distribution becomes wider as shown by curve 15.

Then, when the absolute value manipulation circuit 12 performs an operation to return the demodulated signal at the signal point position -A to the signal point position A side, the probability density distribution of the amplitude value of the demodulated signal is centered around the signal imaginary point iA as shown by the curve 16. As a result, the average amplitude of the demodulated signal sequence is larger than the signal point position A', which is asymmetrical.
The amplitude will be at . This error becomes larger as the C/N becomes lower.

That is, assuming that the amplitude at the signal imaginary IA is A, as shown in FIG.
A2, which provides the signal power S, shows a gradual increase, and the noise power σ2 increases at a fast rate. As a result, as shown in Fig. 7, the measured value Eb/No and the theoretical value Eb
/ No is 8 dB from the high value of Eb/No on the horizontal axis
Although they almost match up to about 8 dB, an error occurs between the two, and the error becomes larger as E b / No on the horizontal axis becomes a lower value of 8 dB or less, that is, as the C/N becomes lower. I will go.

The present invention has been made in view of these problems, and an object thereof is to provide a C/N measurement circuit that can accurately measure C/N even under low C/N conditions.

(Means for Solving the Problems) In order to achieve the above object, the C/N measuring circuit of the present invention has the following configuration.

That is, the C/N measuring circuit of the present invention measures the carrier power to noise power ratio (C/N) on the receiving side of a digital communication system that transmits a signal obtained by digitally modulating an error correction encoded digital signal. A C/N measurement circuit that samples a demodulated signal received and demodulated at the timing of a symbol clock reproduced during demodulation, and converts each sample value into digital time series data consisting of n quantized bits. an A/D converter; an error correction decoding circuit that performs error correction decoding processing on the output of the A/D converter; and an error correction encoding circuit that performs error correction encoding processing on the output of the error correction decoding circuit. circuit; said A/
a delay circuit that performs delay processing for the output of the D converter by a time corresponding to a decoding delay in the error correction decoding circuit and a coding delay in the error correction encoding circuit;
The signal point position of the output signal of the error correction encoding circuit is determined, and if it is not a signal at a predetermined signal point position, the output of the delay circuit is output after converting its code polarity, and it is converted into a predetermined signal. A code conversion circuit that outputs the output of the delay circuit as it is when the signal is a point position signal, and a first averaging process that performs averaging processing on the output of the code conversion circuit between N (an integer of N>O) symbols. a first squaring operation (j circuit) that performs a squaring operation on the output of the first averaging circuit; an output of the A/D converter, an output of the delay circuit, or an output of the code conversion circuit; a second square operation circuit that performs a square operation on any of the outputs;
(N>O integer) a second averaging circuit that performs averaging processing on the output of the second square operation circuit between symbols;
a subtraction circuit that subtracts the output value of the square operation circuit; a C/N conversion circuit that receives each output of the first square operation circuit and the subtraction circuit and outputs the ratio (C/N); It is characterized by the fact that it is equipped with

(Function) Next, the function of the C/N measuring circuit of the present invention configured as described above will be explained.

An A/D converter receives and demodulates a demodulated signal (
An analog signal forming an eye pattern) is sampled at the timing of a symbol clock reproduced during demodulation, and each sample value is converted into digital time series data consisting of n quantized bits. The output of this A/D converter is sent to an error correction decoding circuit, a delay circuit, and, for example, a second square operation circuit, respectively.

First, the error correction decoding circuit performs error correction decoding processing on the output of the A/D converter, and performs error correction decoding processing on the output of the A/D converter, and corrects transmission before error correction coding with a probability specific to the error correction method adopted in the communication system. Restore data. This restored data is subjected to the same error correction encoding process as that on the transmitting side in the error correction encoding circuit, and becomes one input of the code conversion circuit. Here, the output data of the error correction encoding circuit is a data sequence that is close to the transmission data sequence that has been error correction encoded on the transmitting side, and the degree of approximation is determined by
It can be said that it is higher than the modulated demodulated signal.

On the other hand, the delay circuit performs delay processing on the output of the A/D converter by a time corresponding to the decoding delay in the error correction decoding circuit and the encoding delay in the error correction encoding circuit, and converts the output into code. to the other input of the circuit.

In the code conversion circuit, for example, when the demodulated signal is related to a binary digital signal, the signal point position is determined from the output signal of the error correction encoding circuit by "A" and '' in FIG.
-AJ), and if the signal point position is A, the output of the delay circuit is output as is, and the signal point position is -A.
When this is the case, the polarity of the sign of the output of the delay circuit is converted and outputted, that is, the operation is performed to fold back the value of the probability density distribution based on the signal point position A. As a result of this operation, even under low C/N conditions, the probability density distribution of the demodulated signal gathered around the signal point position A can maintain the shape of the curve 14 shown in FIG. The average of the amplitude values is approximately equal to that at the signal imaginary w,A. One output of this code conversion circuit is averaged over a sufficiently long period of N (N>0 integer) symbols in the first averaging circuit, and then squared in the first square operation circuit. is the signal power S when there is no noise, and the subtraction circuit and C
/N conversion circuit.

On the other hand, the output of the A/D converter is subjected to squaring operation in a second squaring operation circuit, and then averaged for a sufficiently long period of N (an integer with N>0) symbols in a second averaging circuit. will be taken. Then, in the subtraction circuit, the output value of the first square operation circuit is subtracted from the output value of the second averaging circuit.

The output value of this subtraction circuit is the noise power σ2 added to the demodulated signal.

In this way, in the C/N conversion circuit, the C/N measurement value is obtained by taking the ratio of the output power (signal power S) of the first square operation circuit and the output (noise power σ2) of the subtraction circuit. Obtainable.

Note that it is clear from the above description that the input of the second square conversion circuit may be the output of the code conversion circuit.

In addition, if the C/N condition is not constant and fluctuates, the second
It is preferable that the input of the square conversion circuit is obtained from the output of the delay circuit.

As explained above, according to the C/N measuring circuit of the present invention, focusing on the fact that error correction control is performed in the communication system, the C/N measuring circuit approximates the transmitted data before error correction coding is performed on the transmitting side. Since the data string is restored by decoding the demodulated signal and used as data to determine the reference signal point position, C/N can be estimated very accurately even under low C/N conditions. effective.

(Example> Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a C/N measuring circuit according to an embodiment of the present invention. Components that are the same as those in FIG. 4 are given the same names and symbols, and their explanations will be omitted.

This C/Nm constant circuit includes a delay circuit 2 receiving the output of the A/D converter 1, an error correction decoding circuit 3, and an error correction decoding circuit in place of the absolute value manipulation circuit 12 shown in FIG. An error suppression code 1-hi circuit 4 receives the output of 3, and a code conversion circuit 5 receives the outputs of the error correction coding circuit 4 and the delay circuit 2. The signal is supplied to the circuit 6.

In the above configuration, the A/D converter 1 receives and demodulates a demodulated signal (forming an eye pattern) on the receiving side of a digital communication system that transmits a signal obtained by digitally modulating an error correction encoded digital signal. Analog signal) is sampled at the timing of the symbol clock reproduced during demodulation, and each sample value is quantized with the number of bits n.
Convert to digital time series data consisting of

The output of this A/D converter 1 is sent to an error correction decoding circuit 3, a delay circuit 2, and a second square operation circuit 8, respectively.

Next, the error correction decoding circuit 3 performs error correction decoding processing on the output of the A/D converter 1, and performs error correction decoding processing on the output of the A/D converter 1, and correctly performs error correction decoding with a probability specific to the error correction method adopted in the communication system. Restore sent data. This restored data is subjected to the same error correction encoding process as that on the transmitting side in the error correction encoding circuit 4, and becomes one input of the code conversion circuit 5. Here, the output data of the error correction encoding circuit 4 is a data sequence close to the transmission data sequence that has been error correction encoded on the transmitting side, and it can be said that the degree of approximation is higher than that of the received demodulated signal. .

On the other hand, the delay circuit 2 performs delay processing on the output of the A/D converter 1 for a time corresponding to the decoding delay in the error correction decoding circuit 3 and the encoding delay in the error correction encoding circuit 4, and encodes the output. It is applied to the other input of the conversion circuit 5.

In the code conversion circuit 5, for example, when the demodulated signal is related to a binary digital signal, the signal imaginary W (the above-mentioned "A" and "-AJ)" in FIG. The polarity of the sign of the output is converted and outputted. That is, the operation is performed to fold back the value of the probability density distribution based on the signal point position A.

As a result of this operation, even under low C/N conditions, the probability density distribution of the demodulated signal centered around signal point position A is
The shape of the curve 14 shown in the figure can be maintained, and the average amplitude value of the demodulated signal sequence becomes approximately equal to that at the signal imaginary position ffA. This code conversion circuit 5 is configured as shown in FIG. 2, for example.

In FIG. 2, 17 is a NOT circuit, 18 is an exclusive OR circuit, and 19 is an adder circuit. Now, the demodulated signal data that has passed through the delay circuit 2 is expressed as a two's complement quantized by n (an integer where n>O) bits, and the judgment data that is the output of the error correction encoding circuit 4 has the signal point position A. When indicating “1”
'', and when indicating the signal point position -A, it is expressed as "0". If the judgment data is "0", the sign polarity of the demodulated signal data is output from the exclusive OR circuit 18. Since a completely inverted version is obtained, the adding circuit 19 adds °°1'' to this, thereby inverting the polarity of the data expressed in two's complement. Note that when the determination data is 1'', the demodulated signal data is output as is.

The subsequent operation is the same as in the case of FIG. 4, so it will be omitted, but the signal power S obtained at the output of the first square operation circuit 7 converts the judgment data indicating the predetermined signal point position into 5GN(d, )
It can be expressed as .

FIG. 3 shows the relationship between <Eb/No and the theoretical value Eb/No based on the C/N measured by the C/N measurement circuit of the present invention as explained above. Even under /N conditions, it can be estimated very accurately.

By the way, in order to perform this estimation more accurately, it is necessary to correctly decode the data decoded by the error correction decoding circuit 3 so that it is equal to the transmitted data, so an error correction method with a high coding gain is used. This means that we have to adopt. In this regard, in recent years, convolutional codes with high coding gains such as soft-decision Viterbi decoding and sequential decoding have become popular, so the C/N measurement circuit according to the present invention enables sufficiently accurate C/N measurement. becomes.

(Effects of the Invention) As explained above, according to the C/N measurement circuit of the present invention, focusing on the fact that error correction control is performed in the communication system, By decoding the demodulated signal and restoring a data string that approximates the transmitted data, we use it as data to determine the reference signal point position, so even under low C/N conditions, C/N can be calculated very accurately. /N can be estimated.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the configuration of the C/N measuring circuit of the present invention, Figure 2 is a block diagram of the code conversion circuit, Figure 3 is a characteristic comparison diagram of the C/N measuring circuit of the present invention, and Figure 4 is a block diagram of the configuration of the C/N measuring circuit of the present invention. A block diagram of the configuration of the C/N measuring circuit developed by the present applicant. Figure 5 is a diagram showing the probability density distribution of the demodulated signal amplitude value when Gaussian noise is added. Figure 6 is the diagram shown in Figure 4. FIG. 7 is a characteristic comparison diagram of the C/N measuring circuit shown in FIG. 4, and FIG. 8 is a block diagram of a conventional C/N measuring circuit. 1... A/D converter, 2... Delay circuit, 3... Error correction decoding circuit, 4...
...error correction encoding circuit, 5 ... code conversion circuit, 6 (9) ... first (second) averaging circuit, 7 (8) ... First (second) square operation circuit, 10...subtraction circuit, 11...C/
N conversion circuit, 12... Absolute value manipulation circuit, 1
7...Negation circuit, 18...Exclusive OR circuit, 19...Addition circuit, 20...
... Band pass filter, 21 ... Demodulator. Agent Patent attorney Yoshi Yahata Hiroki Kusho's c/N;w-circuit 0-circuit 0-hebunbanari-1 Figure/7--@ Fixed circuit, 18-・excluding #! , 9 bribes to carry interference
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Claims (1)

[Claims] A C/N measurement circuit that measures carrier power to noise power ratio (C/N) on the receiving side of a digital communication system that transmits a signal obtained by digitally modulating an error correction encoded digital signal; an A/D converter that samples a demodulated signal at the timing of a symbol clock reproduced during demodulation and converts each sample value into digital time series data having a number of quantized bits n;
an error correction decoding circuit that performs error correction decoding processing on the output of the /D converter; an error correction encoding circuit that performs error correction encoding processing on the output of the error correction decoding circuit; and the A/D converter. a delay circuit that performs delay processing for a time corresponding to the decoding delay in the error correction decoding circuit and the encoding delay in the error correction encoding circuit for the output; a signal point position of the output signal of the error correction encoding circuit; If it is not a signal at a predetermined signal point position, the output of the delay circuit is output after converting its sign polarity, and if it is a signal at a predetermined signal point position, the output of the delay circuit is output. A code conversion circuit that outputs it as is; N (N>0
a first averaging circuit that performs averaging processing on the output of the code conversion circuit between symbols (an integer of ); a first averaging circuit that performs a squaring operation on the output of the first averaging circuit;
a multiplication operation circuit; a second squaring operation circuit that performs a squaring operation on any one of the output of the A/D converter, the output of the delay circuit, or the output of the code conversion circuit;
a second averaging circuit that performs averaging processing on the output of the second square operation circuit between symbols (integer >0); a subtraction circuit that subtracts the output value of the operation circuit; receiving each output of the first square operation circuit and the subtraction circuit;
1. A C/N measurement circuit comprising: a C/N conversion circuit that outputs a C/N (C/N);