JPH0179141U - - Google Patents
Info
- Publication number
- JPH0179141U JPH0179141U JP1987176294U JP17629487U JPH0179141U JP H0179141 U JPH0179141 U JP H0179141U JP 1987176294 U JP1987176294 U JP 1987176294U JP 17629487 U JP17629487 U JP 17629487U JP H0179141 U JPH0179141 U JP H0179141U
- Authority
- JP
- Japan
- Prior art keywords
- latch
- electronic circuit
- signal
- power supply
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 4
- 230000002401 inhibitory effect Effects 0.000 claims 2
- 238000011084 recovery Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
- H02H7/20—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electronic Switches (AREA)
- Manipulation Of Pulses (AREA)
- Logic Circuits (AREA)
- Power Sources (AREA)
- Microcomputers (AREA)
- Measurement Of Current Or Voltage (AREA)
Description
第1図は、本考案の一実施例を示すブロツク図
、第2図は、第1図の回路の動作を示す波形図、
第3図及び第4図は、本考案の他の実施例を示す
ブロツク図、第5図は、本考案の更に他の実施例
を示す回路図、第6図及び第7図は、第5図の回
路の動作を示す波形図、第8図は、ラツチアツプ
を防止する従来の方法を示す回路図である。 主要部分の符号の説明3……ラツチアツプ検出
回路、Q1……トランジスタ。
、第2図は、第1図の回路の動作を示す波形図、
第3図及び第4図は、本考案の他の実施例を示す
ブロツク図、第5図は、本考案の更に他の実施例
を示す回路図、第6図及び第7図は、第5図の回
路の動作を示す波形図、第8図は、ラツチアツプ
を防止する従来の方法を示す回路図である。 主要部分の符号の説明3……ラツチアツプ検出
回路、Q1……トランジスタ。
Claims (1)
- 所定周波数の信号を出力する電子回路のラツチ
アツプ復旧回路であつて、前記電子回路から出力
される信号の周波数が所定帯域内にないことを検
知してラツチアツプ検出信号を発生するラツチア
ツプ検出手段と、前記ラツチアツプ検出信号に応
じて前記電子回路への電源供給を所定時間だけ禁
止する電源供給禁止手段とからなるラツチアツプ
復旧回路。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987176294U JPH0179141U (ja) | 1987-11-18 | 1987-11-18 | |
DE3839077A DE3839077A1 (de) | 1987-11-18 | 1988-11-18 | Heilungsschaltung fuer latch-up-zustand (unerwuenschtes sperren) bei halbleiter-elektronikschaltungen |
US07/273,372 US4900951A (en) | 1987-11-18 | 1988-11-18 | Latch-up restoration circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987176294U JPH0179141U (ja) | 1987-11-18 | 1987-11-18 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0179141U true JPH0179141U (ja) | 1989-05-26 |
Family
ID=16011071
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1987176294U Pending JPH0179141U (ja) | 1987-11-18 | 1987-11-18 |
Country Status (3)
Country | Link |
---|---|
US (1) | US4900951A (ja) |
JP (1) | JPH0179141U (ja) |
DE (1) | DE3839077A1 (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5140177A (en) * | 1988-12-02 | 1992-08-18 | Mitsubishi Denki Kabushiki Kaisha | Complementary circuit device returnable to normal operation from latch-up phenomenon |
US5065047A (en) * | 1989-03-27 | 1991-11-12 | Nissan Motor Co., Ltd. | Digital circuit including fail-safe circuit |
US5180934A (en) * | 1991-05-28 | 1993-01-19 | Thomson Consumer Electronics, Inc. | Self-enabling data-collision avoidance arrangement using a peak detector |
US5229926A (en) * | 1992-04-01 | 1993-07-20 | Digital Equipment Corporation | Power supply interlock for a distributed power system |
EP0724209A1 (en) * | 1995-01-25 | 1996-07-31 | International Business Machines Corporation | Power management system for integrated circuits |
KR0182041B1 (ko) * | 1995-08-11 | 1999-05-15 | 김광호 | 단전원에서의 파워 트랜지스터의 구동 회로 |
DE19540169C1 (de) * | 1995-10-27 | 1996-11-28 | Texas Instruments Deutschland | Integrierte CMOS-Schaltung mit Schaltung zur Latch-up-Verhinderung sowie Status-Speicher |
US5874854A (en) * | 1997-03-28 | 1999-02-23 | International Business Machines Corporation | Control scheme for on-chip capacitor degating |
US5990723A (en) * | 1998-01-09 | 1999-11-23 | Maxim Integrated Products, Inc. | Filter circuits for protecting against transient electrical pulses |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4266145A (en) * | 1979-05-09 | 1981-05-05 | Ncr Corporation | Time dependent master reset |
DE2946081C3 (de) * | 1979-11-15 | 1995-09-21 | Wabco Vermoegensverwaltung | Schaltungsanordnung zur Überwachung der Funktion eines Mikroprozessors |
DE3040326C1 (de) * | 1980-10-25 | 1981-10-08 | Eurosil GmbH, 8000 München | Mikroprozessor mit Ruecksetz-Schaltanordnung |
JPS57208733A (en) * | 1981-06-18 | 1982-12-21 | Fujitsu Ltd | Preventing circuit for malfunction |
US4434403A (en) * | 1981-08-24 | 1984-02-28 | Burroughs Corporation | Universal reset circuit for digital circuitry |
US4520418A (en) * | 1983-04-25 | 1985-05-28 | Susi Roger E | Reset circuit |
US4572966A (en) * | 1983-12-22 | 1986-02-25 | Rockwell International Corporation | Activity monitor, power-on clear circuit |
US4618953A (en) * | 1984-05-01 | 1986-10-21 | Pitney Bowes Inc. | Watchdog circuit |
US4627060A (en) * | 1984-11-29 | 1986-12-02 | Baxter Travenol Laboratories, Inc. | Watchdog timer |
US4698829A (en) * | 1985-03-12 | 1987-10-06 | Pitney Bowes Inc. | Monitoring system for verifying that an input signal is toggling at a minimum frequency |
US4791317A (en) * | 1986-09-26 | 1988-12-13 | Siemens Aktiengesellschaft | Latch-up protection circuit for integrated circuits using complementary mos circuit technology |
-
1987
- 1987-11-18 JP JP1987176294U patent/JPH0179141U/ja active Pending
-
1988
- 1988-11-18 DE DE3839077A patent/DE3839077A1/de active Granted
- 1988-11-18 US US07/273,372 patent/US4900951A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE3839077A1 (de) | 1989-06-01 |
US4900951A (en) | 1990-02-13 |
DE3839077C2 (ja) | 1990-07-26 |
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