JPH0172720U - - Google Patents
Info
- Publication number
- JPH0172720U JPH0172720U JP1987168767U JP16876787U JPH0172720U JP H0172720 U JPH0172720 U JP H0172720U JP 1987168767 U JP1987168767 U JP 1987168767U JP 16876787 U JP16876787 U JP 16876787U JP H0172720 U JPH0172720 U JP H0172720U
- Authority
- JP
- Japan
- Prior art keywords
- control circuit
- gain control
- output
- gain
- receives
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003321 amplification Effects 0.000 claims 1
- 238000003199 nucleic acid amplification method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Control Of Amplification And Gain Control (AREA)
Description
第１図は本考案の一実施例のブロツク図、第２
図は従来の利得制御回路ブロツク図である。
１……利得制御回路、２……振幅検波器、３…
…低域炉波器、４……利得制御回路、５……分配
制御回路。
Figure 1 is a block diagram of one embodiment of the present invention;
The figure is a block diagram of a conventional gain control circuit. 1...gain control circuit, 2...amplitude detector, 3...
...Low range wave generator, 4...Gain control circuit, 5...Distribution control circuit.
Claims (1)
力信号を得る利得制御回路と、この利得制御回路
の出力を受けて前記入力信号に含まれるレベル変
動を検出する振幅検波器と、この振幅検波器の出
力を受けて前記利得制御回路の利得制御用の制御
電圧を出力する低域波器とを備えて雑音がシス
テムノイズに依存する受信装置の利得を自動的に
制御する自動利得制御回路において、前記利得制
御回路と前記振幅検波器の間に追加挿入した利得
制御回路と、前記低域波器の出力を受けつつこ
れとあらかじめ設定した低入力信号対システムノ
イズ比におけるシステムノシズに対する前記低域
波器の出力ならびに回路特性にもとづいて発生
する雑音の影響を排除した制御電圧によつて前記
追加挿入した利得制御回路の利得を制御しつつ前
記追加挿入した利得制御回路の入力として得られ
る出力信号に含まれる信号成分のレベルを一定に
保持せしめる分配制御回路とを備えて成ることを
特徴とする自動利得制御回路。 A gain control circuit that controls amplification gain for an input signal to obtain a constant output signal; an amplitude detector that receives the output of the gain control circuit and detects level fluctuations included in the input signal; an automatic gain control circuit that automatically controls the gain of a receiving device whose noise depends on system noise, the automatic gain control circuit comprising: a low frequency generator that receives an output and outputs a control voltage for gain control of the gain control circuit; A gain control circuit additionally inserted between a gain control circuit and the amplitude detector, and a gain control circuit that receives the output of the low frequency detector and generates a low frequency signal corresponding to the system noise at a preset low input signal to system noise ratio. The gain of the additionally inserted gain control circuit is controlled by a control voltage that eliminates the influence of noise generated based on the output of the device and the circuit characteristics, and the output signal obtained as the input of the additionally inserted gain control circuit is controlled. An automatic gain control circuit comprising: a distribution control circuit that maintains the level of the included signal components constant.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987168767U JPH0172720U (en) | 1987-11-02 | 1987-11-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987168767U JPH0172720U (en) | 1987-11-02 | 1987-11-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0172720U true JPH0172720U (en) | 1989-05-16 |
Family
ID=31458234
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987168767U Pending JPH0172720U (en) | 1987-11-02 | 1987-11-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0172720U (en) |
-
1987
- 1987-11-02 JP JP1987168767U patent/JPH0172720U/ja active Pending