JPH0170445U

JPH0170445U -

Info

Publication number: JPH0170445U
Application number: JP16617087U
Authority: JP
Priority date: 1987-10-28
Filing date: 1987-10-28
Publication date: 1989-05-10

Description

[Brief explanation of the drawing]

第１図は本考案の構成ブロツク図、第２図は本
考案に用いた回路図例、第３図は本考案の内部図
例、第４図は信号ミキサー回路を本考案に用いた
時の回路一部図例、第５図はトグルスイツチをケ
ースに取り付けた図、第６図は基板をケースに取
り付けた図、第７図はジヤツクをケースに取り付
けた図、第８図は音電気信号回路を復調回路で構
成した本考案に用いた回路図例である。図において、１はジヤツク、２はプラグ、３は
コンセントプラグ、４はケース、５は基板、６は
トランス、７はトグルスイツチ、８と９と２５と
２８と２９はビス、１０〜２０は電線、２１と６
３〜７３は抵抗素子、２２は音電気信号制御回路
のブロツク図、２３と２４はコードブツシユ、２
６と５６と７８はナツト、２７は音電気信号回路
のブロツク、３０と３１はスペーサ、３２は信号
処理回路のブロツク、３３は受信回路のブロツク
、３４はダイオード、３５と３６はスピーカー、
３７はアンテナ、３８〜４０はコイル、４１はス
テレオヘツドホン、４２は判別回路のブロツク、
４４と４７は演算増幅器、４５は整流、平滑回路
のブロツク、４６は安定化電圧回路のブロツク、
５１〜５４は可変抵抗器、５５はインバータ、４
３と４８〜５０と５７〜６２はコンデンサ、７４
〜７７はアナログスイツチ、７８は復調回路のブ
ロツクである。 Figure 1 is a configuration block diagram of the present invention, Figure 2 is an example of a circuit diagram used in this invention, Figure 3 is an example of an internal diagram of this invention, and Figure 4 is a signal mixer circuit when used in this invention. Examples of partial circuit diagrams: Figure 5 shows the toggle switch attached to the case, Figure 6 shows the board attached to the case, Figure 7 shows the jack attached to the case, and Figure 8 shows the sound and electrical signals. This is an example of a circuit diagram used in the present invention in which the circuit is composed of a demodulation circuit. In the figure, 1 is a jack, 2 is a plug, 3 is an outlet plug, 4 is a case, 5 is a board, 6 is a transformer, 7 is a toggle switch, 8, 9, 25, 28, and 29 are screws, and 10 to 20 are electric wires. , 21 and 6
3 to 73 are resistive elements, 22 is a block diagram of an audio and electrical signal control circuit, 23 and 24 are code bushes, 2
6, 56 and 78 are nuts, 27 is an audio/electrical signal circuit block, 30 and 31 are spacers, 32 is a signal processing circuit block, 33 is a receiving circuit block, 34 is a diode, 35 and 36 are speakers,
37 is an antenna, 38 to 40 are coils, 41 is a stereo headphone, 42 is a discrimination circuit block,
44 and 47 are operational amplifiers, 45 is a rectifier and smoothing circuit block, 46 is a stabilizing voltage circuit block,
51 to 54 are variable resistors, 55 is an inverter, 4
3, 48-50 and 57-62 are capacitors, 74
-77 are analog switches, and 78 is a demodulation circuit block.

Claims

[Claims for Utility Model Registration] When a radio wave for calling is emitted, whether there is a frequency of an effective intermediate frequency signal output from the output terminal J of the superheterodyne receiving circuit 33 that receives the radio wave for calling. The output j terminal of the superheterodyne type receiving circuit 33 is connected to the input k terminal of the discriminating circuit 42 which discriminates whether or not the signal is received. The superheterodyne receiving circuit 33
Then, the discrimination circuit 42 is attached to the case 4. The superheterodyne receiving circuit 33
When the signal output from the output terminal j of the output terminal e of the discriminating circuit 42 when not called is input to the b terminal controlled by the signal processing circuit 32, the analog signal input to the input a terminal. The signal processing circuit 32 has a configuration in which the signal is output from the output c terminal without any analog signal change, and the superheterodyne type receiving circuit 33
When the valid signal outputted from the output terminal e of the discrimination circuit 42 during calling is inputted to the b terminal controlled by the signal processing circuit 32, the analog signal inputted to the input a terminal is inputted from the output j terminal of . At the signal,
A signal processing circuit 32 is attached to the case 4, which has a configuration in which a signal is outputted from an output c terminal with changes similar to an analog signal. The output e terminal of the discrimination circuit 42 is connected to the b terminal of the signal processing circuit 32. A device comprising the above.