JPH0165523U - - Google Patents
Info
- Publication number
- JPH0165523U JPH0165523U JP1987160645U JP16064587U JPH0165523U JP H0165523 U JPH0165523 U JP H0165523U JP 1987160645 U JP1987160645 U JP 1987160645U JP 16064587 U JP16064587 U JP 16064587U JP H0165523 U JPH0165523 U JP H0165523U
- Authority
- JP
- Japan
- Prior art keywords
- channel mos
- fet
- input buffer
- current capacity
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manipulation Of Pulses (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987160645U JPH0165523U (enExample) | 1987-10-20 | 1987-10-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987160645U JPH0165523U (enExample) | 1987-10-20 | 1987-10-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0165523U true JPH0165523U (enExample) | 1989-04-26 |
Family
ID=31442892
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987160645U Pending JPH0165523U (enExample) | 1987-10-20 | 1987-10-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0165523U (enExample) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5710533A (en) * | 1980-06-23 | 1982-01-20 | Nec Corp | Logical circuit |
-
1987
- 1987-10-20 JP JP1987160645U patent/JPH0165523U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5710533A (en) * | 1980-06-23 | 1982-01-20 | Nec Corp | Logical circuit |
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