JPH0159928U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the structure of the present invention, FIG. 2 is a cutaway view of the outer case of a cassette-type video tape recorder to show the inside, and FIG. 3 is a view of the board attached to the case. In the figure, 1 is a case, 2 is a board, 3 and 4 are spacers, 5 and 6 are nuts, 7 and 8 are screws, 9 and 10 are shielded wires, 11 to 13 are wires, 14 is an antenna, and 15 is a tuner. 16 is a video intermediate frequency amplification circuit block, 17 is a video detection circuit block, 18 is a video amplification circuit block, 19 is a pre-emphasis circuit block, 2
0 is an FM modulation circuit block, 21 is a video recording circuit block, 22 is a video playback circuit block,
23 is an FM demodulation circuit block, 24 is a de-emphasis circuit block, 25 is a superimpose circuit block, 26 is an insert character information circuit block, 27 is a synchronization signal processing circuit block, 28
29 is a block of the brightness level circuit, 29 is a block of a switch circuit, 30 is a block of a pause state storage control circuit, 31 is a block of a recording state storage control circuit, 32 is a block of a discrimination circuit, 33 and 34 are switches, and 35 is a block of a discrimination circuit. The rotary head 36 is a block of a monochromatic signal conversion circuit.

Claims (1)

[Claims for Utility Model Registration] A p terminal that is a video signal input terminal, an m terminal that is a video signal output terminal of the switch circuit 29, and a j terminal that controls switching of the switch circuit 29.
c, which is a terminal that outputs a signal that controls switching of the switch element of the switch circuit 29;
A superimpose circuit 25 having at least one terminal is attached to a cassette video tape recorder device. When the above-mentioned cassette type video tape recorder device is compatible with video cassette tapes, when it is in the playback state, the processed output signal passes through the video playback circuit 22, and when it is in the recording state,
W is a terminal through which the output signal passes through the video amplification circuit 18.
The terminal is connected to the p terminal which is the video signal input terminal of the superimpose circuit 25 mentioned above. While the video cassette tape is inserted into the cassette video tape recorder and the video cassette tape is in operation, the cassette video tape recorder stops running in response to an external command to pause the video cassette recorder. The video cassette tape has a memory circuit for holding a memory state for possible states, and controls from the memory circuit whether the running state of the video cassette tape is brought into a paused state or not. The pause state storage control circuit 30 outputs a valid signal in the pause state from the output terminal a in response to a command to enter the pause state; and the cassette video tape. When the video cassette tape is inserted into the recorder device and the video cassette tape is in operation, the state of the video cassette tape recorder device changes to the recording state due to an external command to change the video cassette tape to the recording state. The storage circuit has a memory circuit for holding a memory state for the video cassette tape, and controls whether or not the state corresponding to the video cassette tape is to be recorded or not. It has a control circuit, and these recording state storage control circuits 31
In response to the command to enter the recording state, the switch circuit 29 disconnects the K and m terminals and connects the n and m terminals with the valid signal output from the output b terminal in the recording state. When the valid signal is output from the output c terminal and the valid signal is output from the a, b, and c terminals at the same time, the a and d terminals are connected, and the b and e terminals are connected. When the c and f terminals are connected, and the h and j terminals are connected, the k and m terminals are disconnected and the n and m terminals are connected by the valid signal from the output h terminal of the discrimination circuit 32. The output h terminal of the discrimination circuit 32 is connected to the j terminal controlled by the switch circuit 29. Output a of the temporary stop state storage control circuit 30
The terminal is connected to the input d terminal of the discrimination circuit 32. The output terminal b of the recording state storage control circuit 31 is connected to the input terminal e of the discrimination circuit 32. The c terminal, which is a terminal that outputs a signal for controlling switching of the switch element, is connected to the input f terminal of the discrimination circuit 32. A cassette-type video tape recorder device comprising the above.