JPH0155508B2 - - Google Patents
Info
- Publication number
- JPH0155508B2 JPH0155508B2 JP55061288A JP6128880A JPH0155508B2 JP H0155508 B2 JPH0155508 B2 JP H0155508B2 JP 55061288 A JP55061288 A JP 55061288A JP 6128880 A JP6128880 A JP 6128880A JP H0155508 B2 JPH0155508 B2 JP H0155508B2
- Authority
- JP
- Japan
- Prior art keywords
- amplifier
- input terminal
- fet
- inverting input
- logarithmic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000005669 field effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06G—ANALOGUE COMPUTERS
- G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
- G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
- G06G7/24—Arrangements for performing computing operations, e.g. operational amplifiers for evaluating logarithmic or exponential functions, e.g. hyperbolic functions
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Networks Using Active Elements (AREA)
Description
【発明の詳細な説明】
本発明は、入力信号電圧の対数に比例した出力
電圧を得る対数増幅器に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logarithmic amplifier that obtains an output voltage proportional to the logarithm of an input signal voltage.
対数増幅器は、例えば(イ)広範囲にレベルが変化
する入力信号のレベルをモニターするためのデシ
ベル目盛の電圧計、(ロ)制御電圧に対する制御特性
が対数関係になつている制御回路（例えばピンダ
イオードを使用した可変減衰器）の制御電圧に対
する制御特性を直線化するための回路等に用いら
れる。対数増幅器の特性として、入力信号の変化
に対してできるだけ正確で連続的な対数出力が得
られることが必要であることはいうまでもない。
従来の代表的な対数増幅器を第１図を参照しなが
ら説明する。 Logarithmic amplifiers are, for example, (a) a voltmeter with a decibel scale for monitoring the level of an input signal whose level changes over a wide range, and (b) a control circuit whose control characteristics for the control voltage are logarithmically related (for example, a pin diode). It is used in circuits to linearize the control characteristics for the control voltage of variable attenuators (using variable attenuators). It goes without saying that as a characteristic of a logarithmic amplifier, it is necessary to obtain a logarithmic output that is as accurate and continuous as possible in response to changes in the input signal.
A typical conventional logarithmic amplifier will be explained with reference to FIG.
第１図において、１は入力端子、２は出力端
子、３〜５はダイオード、６〜９は利得を決める
抵抗、１０は帰還抵抗、１１は直流増幅器、１２
は電圧源、１３〜１５は前記ダイオード３〜５の
カソードにバイアス電圧を与えるための抵抗であ
る。ここで、ダイオード３〜５のカソードは異つ
た電圧でバイアスされているので、入力信号が
除々に大きくなつていくと、ダイオード３〜５
は、順番に導通してゆく。従つて直流増幅器１１
の入力抵抗は、最初は抵抗９のみであつたもの
が、抵抗８，７，６が次々に並列に入つてゆく事
になるので、この回路の入出力間特性は直線とな
らず折線近似の曲線となる。このダイオードのバ
イアス電圧を調整して入出力間特性を対数特性と
なる様にすれば対数増幅器となる。しかしこの回
路では前述の如く折線近似であるため、良好な対
数特性を得るためには各折線の本数を増やさなけ
ればならなくなり、多くのダイオードと抵抗が必
要となる欠点がある。 In Figure 1, 1 is an input terminal, 2 is an output terminal, 3 to 5 are diodes, 6 to 9 are resistors that determine gain, 10 is a feedback resistor, 11 is a DC amplifier, 12
is a voltage source, and 13 to 15 are resistors for applying a bias voltage to the cathodes of the diodes 3 to 5. Here, since the cathodes of diodes 3 to 5 are biased with different voltages, as the input signal gradually increases, the cathodes of diodes 3 to 5
conduct in order. Therefore, the DC amplifier 11
Initially, the input resistance was only resistor 9, but resistors 8, 7, and 6 are successively connected in parallel, so the input-output characteristic of this circuit is not a straight line but a broken line approximation. It becomes a curve. By adjusting the bias voltage of this diode so that the input-output characteristics become logarithmic, a logarithmic amplifier is obtained. However, since this circuit uses the broken line approximation as described above, in order to obtain good logarithmic characteristics, the number of each broken line must be increased, and there is a drawback that many diodes and resistors are required.
本発明は、このような従来の増幅器の欠点を除
去し、構成部品数を増やすことなく正確な対数特
性を得ることのできる対数増幅器を提供すること
を目的とするものである。 SUMMARY OF THE INVENTION An object of the present invention is to provide a logarithmic amplifier that eliminates the drawbacks of conventional amplifiers and can obtain accurate logarithmic characteristics without increasing the number of components.
この目的のために本発明に係る対数増幅器は、
直流増幅器の反転入力端子とアース間に電界効果
トランジスタ（以下FETと称する）を接続し、
前記FETのドレインを前記直流増幅器の反転入
力端子に、前記FETのソースをアースに、前記
FETのゲートを前記直流増幅器の非反転入力端
子にそれぞれ接続し、前記直流増幅器の出力端子
と反転入力端子との間に帰還抵抗を挿入し、前記
直流増幅器の非反転入力端子に入力信号を加え、
前記増幅器の出力端子から出力信号を得るように
したものである。 For this purpose, the logarithmic amplifier according to the invention comprises:
A field effect transistor (hereinafter referred to as FET) is connected between the inverting input terminal of the DC amplifier and the ground.
The drain of the FET is connected to the inverting input terminal of the DC amplifier, the source of the FET is connected to the ground, and the
The gates of the FETs are connected to the non-inverting input terminals of the DC amplifier, a feedback resistor is inserted between the output terminal and the inverting input terminal of the DC amplifier, and an input signal is applied to the non-inverting input terminal of the DC amplifier. ,
The output signal is obtained from the output terminal of the amplifier.
以下、本発明を、図面を参照しながら、実施例
について説明する。第２図は本発明の１実施例を
示したものであつて、１は入力端子、２は出力端
子、１６は直流増幅器、１８は帰還抵抗、１７は
電界効果トランジスタ（FET）である。直流増
幅器１６の入力端子のうち入出力電圧の位相が反
転する端子を反転入力端子として−の符号を付
し、反転しない端子を非反転入力端子として＋の
符号を付してある。ここで、FET１７のドレイ
ンは直流増幅器１６の反転入力端子に、ソースは
アースに接続される。またFET１７のゲートは
直流増幅器１６の非反転入力端子に接続される。
入力信号はこの非反転入力端子に加えられ、該増
幅器１６の出力端子２から出力信号が取出され
る。 Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 shows one embodiment of the present invention, in which 1 is an input terminal, 2 is an output terminal, 16 is a DC amplifier, 18 is a feedback resistor, and 17 is a field effect transistor (FET). Among the input terminals of the DC amplifier 16, the terminal where the phase of the input/output voltage is inverted is designated as an inverting input terminal and is designated with a minus sign, and the terminal that is not inverted is designated as a non-inverting input terminal and is designated with a plus sign. Here, the drain of the FET 17 is connected to the inverting input terminal of the DC amplifier 16, and the source is connected to the ground. Further, the gate of the FET 17 is connected to the non-inverting input terminal of the DC amplifier 16.
An input signal is applied to this non-inverting input terminal and an output signal is taken from the output terminal 2 of the amplifier 16.
この増幅器の利得Ｇは、FETのドレイン〜ソ
ース間の抵抗をR1、帰還抵抗をR2とすると、Ｇ
＝（１＋R2／R1）……(1)となる。又、FETのドレ
イン〜ソース間の抵抗R1は、ゲート〜ソース間
の電圧に対して対数的に変化するので、ゲート〜
ソース間電圧をVGSとすると、
R1＝ｋ・exp（VGS）……(2)と表わされる。 The gain G of this amplifier is given by R1 being the resistance between the drain and source of the FET and R2 being the feedback resistance
=(1+R 2 /R 1 )...(1). Also, the resistance R1 between the drain and source of the FET changes logarithmically with respect to the voltage between the gate and source.
When the source-to-source voltage is V GS , it is expressed as R 1 =k·exp(V GS ) (2).
ｋは定数である。(2)式を(1)式に代入すると、 Ｇ＝１＋R2／ｋ・exp（VGS） ＝１＋Ｋ／exp（VGS） ……(3) ただしＫ＝R2／ｋである。 k is a constant. Substituting equation (2) into equation (1), G=1+R 2 /k·exp(V GS )=1+K/exp(V GS )...(3) However, K=R 2 /k.
ここで、１＜Ｋ／exp（VGS）となる様にR2を定
めると、(3)式は、Ｇ＝Kexp（VGS）……(4)と近似
できる。VGSは第２図より入力電圧と同一である
ので、入力電圧、出力電圧をそれぞれVio，Vput
とすると、(4)式は
Ｇ＝Vput／Vio＝Ｋ／exp（Vio）
Vput＝Ｋ｛Vio／exp（Vio）｝ ……(5)
(5)式の両辺の対数をとると、
logVput＝logK＋logVio−Vio ……(6)
ここでlog（Ｋ・Vio）＜Vioとなる様にＫ，Vioを
定めると、(6)式は
logVput∽Vio ……(7)
となり、入力電圧、出力電圧は対数関係となる。 Here, if R 2 is determined so that 1<K/exp(V GS ), equation (3) can be approximated as G=Kexp(V GS )...(4). From Figure 2, V GS is the same as the input voltage, so the input voltage and output voltage are V io and V put , respectively.
Then, equation (4) is G = V put /V io = K / exp (V io ) V put = K {V io /exp (V io )} ...(5) Logarithm of both sides of equation (5) Then, logV put = logK + logV io −V io ……(6) Here, if K and V io are determined so that log(K・V io )<V io , equation (6) becomes logV put ∽V io ...(7) The input voltage and output voltage have a logarithmic relationship.
以上説明したように、本発明の対数増幅器は、
FETのドレイン〜ソース間抵抗とゲート〜ソー
ス間電圧が対数間係にある事を利用しているの
で、ダイオードと抵抗を用いた従来の折線近似対
数増幅器に比較して、使用部品数が少くかつ正確
な対数増幅器を得ることができる。なお、第２図
はＰチヤンネルのFETを使用した場合の実施例
であるが、第３図の如くＮチヤンネルのFETを
使用しても上記の効果はそこなわれず、本発明は
このような態様も含むことは勿論である。 As explained above, the logarithmic amplifier of the present invention has
Since it takes advantage of the fact that the FET's drain-source resistance and gate-source voltage have a logarithmic relationship, the number of components used is small compared to the conventional linear approximation logarithmic amplifier that uses diodes and resistors. An accurate logarithmic amplifier can be obtained. Although FIG. 2 shows an example in which a P-channel FET is used, the above-mentioned effect is not impaired even if an N-channel FET is used as shown in FIG. Of course, it also includes aspects.
第１図は従来の折線近似の対数増幅器の回路を
示す図、第２図は本発明の１実施例に係る対数増
幅器の回路図、第３図は本発明の他の実施例を示
す図である。
１…入力端子、２…出力端子、１６…直流増幅
器、１８…帰還抵抗、１７…電界効果トランジス
タ（FET）。
FIG. 1 is a diagram showing a conventional logarithmic amplifier circuit using a broken line approximation, FIG. 2 is a circuit diagram of a logarithmic amplifier according to one embodiment of the present invention, and FIG. 3 is a diagram showing another embodiment of the present invention. be. 1... Input terminal, 2... Output terminal, 16... DC amplifier, 18... Feedback resistor, 17... Field effect transistor (FET).
Claims (1)
て、反転入力端子とアース間に接続されるべき抵
抗の代りに電界効果トランジスタ（以下FETと
する）を接続し、前記FETのドレインを前記直
流増幅器の反転入力端子に、前記FETのソース
をアースに、前記FETのゲートを前記直流増幅
器の非反転入力端子にそれぞれ接続し、前記直流
増幅器の出力端子と反転入力端子の間に帰還回路
を形成し、前記直流増幅器の非反転入力端子に入
力信号を加えるようにしたことを特徴とする対数
増幅器。1 In a non-inverting amplifier circuit using a DC amplifier, a field effect transistor (hereinafter referred to as FET) is connected in place of the resistor that should be connected between the inverting input terminal and the ground, and the drain of the FET is connected to the inverting input terminal of the DC amplifier. The source of the FET is connected to the input terminal, the gate of the FET is connected to the non-inverting input terminal of the DC amplifier, and a feedback circuit is formed between the output terminal and the inverting input terminal of the DC amplifier. A logarithmic amplifier characterized in that an input signal is applied to a non-inverting input terminal of a DC amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6128880A JPS56157569A (en) | 1980-05-09 | 1980-05-09 | Logarithmic amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6128880A JPS56157569A (en) | 1980-05-09 | 1980-05-09 | Logarithmic amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56157569A JPS56157569A (en) | 1981-12-04 |
| JPH0155508B2 true JPH0155508B2 (en) | 1989-11-24 |
Family
ID=13166853
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6128880A Granted JPS56157569A (en) | 1980-05-09 | 1980-05-09 | Logarithmic amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56157569A (en) |
-
1980
- 1980-05-09 JP JP6128880A patent/JPS56157569A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56157569A (en) | 1981-12-04 |
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