JPH0153530B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase lock loop circuit used in a frequency synthesizer or the like, and in particular is designed to reduce jitter in an output signal obtained from the output side of a voltage controlled oscillator.

A phase lock loop circuit conventionally used in a frequency synthesizer is as shown in FIG. That is, in FIG. 1, 1 indicates a phase comparison circuit, and one input terminal of this phase comparison circuit 1 receives a reference signal from a reference signal generation circuit 2, for example, 9KHz.
The output signal of this phase comparison circuit 1 is supplied to the frequency control terminal of the voltage controlled oscillator 4 via the low pass filter 3, and the output signal of this voltage controlled oscillator 4 is supplied to the output terminal 5. At the same time, the output signal of this voltage controlled oscillator 4 is divided at a frequency division ratio of 1/N.
is supplied to a variable frequency divider 6 which can be varied by the channel selection signal supplied to the channel selection signal input terminal 6a, and the output signal of the variable frequency divider 6 is supplied to the other input terminal of the phase comparator circuit 1. When the output signal of the phase lock loop circuit as shown in FIG. This is done so that an oscillation signal of 9KHz of 2052KHz can be obtained.

For example, in a phase lock loop circuit that obtains the local oscillation signal of an AM receiver, the frequency _r of the reference signal
When the frequency is as low as 9KHz, this 9KHz frequency component cannot be removed by the low-pass filter 3, and the voltage-controlled oscillator 4 is angularly modulated by the 9KHz component appearing on the output side of the low-pass filter 3. Therefore, when the signal obtained at the output terminal 5 is observed with a spectrum analyzer, it will have side bands on both sides of the desired frequency _p , as shown in FIG. When the cutoff frequency of the low-pass filter 3 is lowered in order to remove this sideband, the time constant becomes longer, so it takes time for the phase to lock, deteriorating the transient response, and in extreme cases, causing the phase to lock. The operation of the phase lock loop circuit becomes unsatisfactory. For this reason, in the phase lock loop circuit shown in FIG. 1, the cutoff frequency of the low-pass filter 3 cannot be lowered, and when the frequency of the reference signal is low, It was not possible to reduce the band, that is, jitter. Also, although Figure 1 shows a simple case where the reference signal has only a single frequency, when extracting a carrier wave signal for synchronization from a complex wave, such as in a primitive type synthesizer, the phenomenon occurs. It is complicated and often produces large jitter, and it is extremely difficult to remove this jitter without impairing the stability of the phase lock loop circuit.

In view of this, the present invention is designed to reduce jitter in the output signal of a voltage controlled oscillator in a phase locked loop circuit.

An embodiment of the phase lock loop circuit according to the present invention will be explained below with reference to FIG. This third
In the figure, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

In the example shown in FIG. 3, a signal e _i including an unnecessary component as shown in FIG. 2 obtained at the output side of the voltage controlled oscillator 4 shown in FIG. A signal containing this unnecessary component is supplied to one input terminal of the mixing circuit 8. In general, a signal e _i including this unnecessary component is expressed as ei=asinωt+ _N+ 〓 ^n=N- b _o ×sin {(W+P _o )t+θn} (1). Here ω is the angular frequency of the desired signal,
b _o is the level of the n-th interference wave, (ω+p _o ) is the angular frequency of the n-th interference wave, and θn is the initial phase of the interference wave. The output signal of this mixing circuit 8 is supplied to the other input terminal of the adding circuit 7. Further, the output signal of this adder circuit 7 is supplied to one input terminal of a phase comparator circuit 10 via a frequency-characteristic band-pass filter 9 that extracts the difference component term of the output signal of this adder circuit 7. 10 is supplied to a low-pass filter 11, and the output signal of this low-pass filter 11 is supplied to a frequency control terminal of a voltage-controlled oscillator 12.
control the oscillation frequency. In this case, the voltage controlled oscillator 12 is made to oscillate at twice the frequency of the voltage controlled oscillator 4. The output signal of this voltage controlled oscillator 12 is supplied to the other input terminal of the phase comparator circuit 10 via a 1/2 frequency divider 13, and this 1/2
An output terminal 5 is derived from the output side of the frequency divider 13, and the output signal of the voltage-controlled oscillator 12 is supplied to the other input terminal of the mixing circuit 8.

The operation of FIG. 3 will be explained below.
It is assumed that a reference signal e _i including unnecessary components as shown in (1) is supplied. At this time, the phase comparator circuit 10,
low pass filter 11, voltage controlled oscillator 12,
When the phase lock loop circuit constituted by the 1/2 frequency divider 13 is locked, this voltage controlled oscillator 12
The output signal Vo is V ₀ =2×sin(2ωt−π/2) (2). Therefore, the signals of equations (1) and (2) are mixed in the mixer circuit 8, this mixed output signal and the signal of equation (1) are added in the adder circuit 7, and the output signal of the adder circuit 7 is the output signal. As e ₇ , e ₇ = e _i + e _i ×V ₀ is obtained. In this case, sin(β−π/2)=−cosβand−2 sinαcosβ=−{sin(α+β)+sin(α−β
)}=−sin(α+β)+sin(β−α) holds, so e _i ×V ₀ =−e _i ×2cos2ωt=−2asinωt×cos2ωt −2 _N+ 〓 〓 ^n=N- [b _o ×sin{ (ω＋p _o )t＋θ _o ｝cos2ωt〕=−asi
It can be transformed as n3ωt+asinωt _N+ 〓 ^n=N- −b _o ×sin {(3ω+p _o )t+θ _o } _N+ 〓 ^n=N- +b _o ×sin{(ω−p _o )t−θ _o }. The angular frequency of that output signal _e7 is
In order to remove harmonic components in the vicinity of 3ω, the output signal _e7 is passed through a bandpass filter 9 whose center angular frequency is ω.
When passed through the bandpass filter 9, the signal e ₉ obtained at the output side of the bandpass filter 9 is e ₉ =asinωt+ _N+ 〓 ^n=N- bnsin{(ω+pn)t+θn}+asinωt+ _N+ 〓n ^=N- bnsin{(ω −pn)t−θn}=2asinωt+ _N+ 〓 ^n=N- bnsinωtcos(pnt+θn) =2a{1+1/a _N+ 〓 ^n=N- bncos(pnt+θn)}sinωt...(3) So, this bandpass filter Even if an arbitrary composite wave signal is input to one input terminal of each of the adder circuit 7 and the mixer circuit 8, an amplitude modulated wave signal is always obtained on the output side of the adder circuit 9. This bandpass filter 9
The amplitude modulated _wave signal e _{9 obtained} on the output side of A signal of d(t)=e ₉ ×e ₀ ...(5) is obtained on the output side of , and when the signal d(t) of equation (5) is passed through the low-pass filter 11, d( t)=e ₉ ×e ₀ =0. Therefore, the output of the low-pass filter 11 does not contain a low frequency component that modulates the angle of the voltage-controlled oscillator 12, which causes jitter.

Therefore, according to the present invention, it is possible to obtain an oscillation signal with no sidebands, that is, with reduced jitter, on the output side of the voltage controlled oscillator 12, and to output a signal at the desired frequency with reduced jitter at the output terminal 5. can be obtained.

FIG. 4 shows another embodiment of the present invention, in which the present invention is applied to a primitive synthesizer often used in short wave receivers and the like. In FIG. 4, parts corresponding to those in FIG. 3 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

In FIG. 4, reference numeral 14 indicates a variable frequency oscillator, and the output signal of this variable frequency oscillator 14 is supplied to one input terminal of a mixing circuit 15, and the output signal of this mixing circuit 15 is passed through a band pass filter 16. The output signal of the variable frequency divider 6 is supplied to one input terminal of the adding circuit 7, and the output signal of the variable frequency divider 6 is supplied to one input terminal of the mixing circuit 8. A reference signal of frequency _r from the reference signal generation circuit 2 is supplied to the other input terminal of the mixing circuit 8.
The output signal of the adder circuit 7 is supplied to the other input terminal of the adder circuit 7, and the output signal of the adder circuit 7 is supplied to the input terminal of the bandpass filter 9. In this case, a signal obtained by converting the output signal of the variable frequency divider 6 into an amplitude modulation signal is obtained on the output side of the bandpass filter 9 in the same manner as in the example shown in FIG. The output signal of the bandpass filter 9 is supplied to one input terminal of the phase comparison circuit 10, and the reference signal of a single frequency _r from the reference oscillator 17, which generates a stable signal containing no harmonic components, is 1/ The output signal of the phase comparison circuit 10 is supplied to the other input terminal of the phase comparison circuit 10 via a 1/2 frequency divider 13 that divides the frequency by 2, and the output signal of this phase comparison circuit 10 is passed through a low-pass filter 11 to a voltage-controlled oscillator 12. The output signal of the voltage controlled oscillator 12 is supplied to the other input terminal of the mixing circuit 15, and the output terminal 5 is derived from the output side of the voltage controlled oscillator 12. In this case, the frequency _v of the output signal of this voltage-controlled oscillator 12 is _v = N/2 r when the frequency division ratio of the variable frequency divider 6 is 1/N and the frequency of the output signal of the variable frequency oscillator 14 is _{VFO .} Becomes _VFO . Also in FIG. 4, the phase comparator circuit 10
Since one of the signals supplied to the voltage controlled oscillator 12 is converted into an amplitude modulation signal, as in
At the output side, that is, at the output terminal 5, an oscillation signal of a desired frequency with reduced jitter can be obtained as in the example shown in FIG.

Furthermore, according to the example in FIG. 4, the frequency of the output signal of the variable frequency oscillator 14, which tends to include jitter components,
By varying _{the VFO} , it is possible to obtain oscillation signals of various frequencies with reduced jitter components.

It goes without saying that the present invention is not limited to the above-described embodiments, and that various other configurations can be taken without departing from the gist of the present invention.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing an example of a conventional phase lock loop circuit, FIG. 2 is a diagram for explaining FIG. 1,
FIG. 3 is a block diagram showing one embodiment of a phase lock loop circuit according to the present invention, and FIG. 4 is a block diagram showing another embodiment of the present invention. 1 and 10 are phase comparison circuits, 2 is a reference signal generation circuit, 3 and 11 are low-pass filters, respectively.
4 and 12 are voltage controlled oscillators, 5 is an output terminal, 6 is a variable frequency divider, 7 is an adder circuit, 8 is a mixing circuit, 9 is a band pass filter, and 13 is a 1/2 frequency divider.

Claims (1)

[Claims] 1. A first input terminal to which an input signal is supplied to one input terminal.
The output signal of the phase comparison circuit 1 is supplied to the first voltage-controlled oscillator 4 through the first low-pass filter 3, and the output signal of the first voltage-controlled oscillator 4 is frequency-divided. A first phase lock loop circuit is formed by supplying the signal to the other input terminal of the first phase comparison circuit 1, and the output signal of the second phase comparison circuit 10 is passed through the second low-pass filter 11. to the second voltage controlled oscillator 12 via the second voltage controlled oscillator 1.
A second phase lock loop circuit is formed by supplying a signal obtained by frequency-dividing the output signal of the first voltage-controlled oscillator 4 to one input terminal of the second phase comparison circuit 10. A signal obtained by frequency mixing the output signal and the output signal of the second voltage controlled oscillator 12 is added to the output signal of the first voltage controlled oscillator 4, and the signal obtained by the addition is A phase lock loop circuit characterized in that the signal is supplied to the other input terminal of the second phase comparator circuit 10 via a pass filter 9. 2. The output signal of the phase comparison circuit 10 is supplied to the voltage controlled oscillator 12 via the low pass filter 11, and the output signal of the voltage controlled oscillator 12 and the output signal of the variable frequency oscillator 14 are frequency-mixed. The signal is supplied to the variable frequency divider 6 via the bandpass filter 16, and the reference signal containing no harmonic components and the output signal of the variable frequency divider 6 are frequency-mixed to produce a signal. A signal obtained by adding the output signals of 6 and 6 is supplied to one input terminal of the phase comparison circuit 10 through the bandpass filter 9, and a signal obtained by frequency-dividing the reference signal that does not include the harmonic component. is supplied to the other input terminal of the phase comparator circuit 10.