JPH0150999B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to input/output terminals of a CMOS integrated circuit, particularly a RAM (Random Access Memory) operated at a relatively high voltage, and a data line to which a relatively low voltage signal is supplied. to combine
It concerns a CMOS integrated circuit with a RAM input/output control circuit.

CMOS (Complementary Metal Oxide)
In circuit devices that use integrated circuits (Semiconductor), the current consumption is essentially the charging and discharging current flowing through stray capacitances, parasitic capacitances, etc. that exist at various nodes of the circuit, and the current flowing in series between the power supply terminals. Connected P-channel MOSFET and N-channel
It is determined by the through current that flows when the MOSFETs are simultaneously turned on during the signal transition period.

Both the current consumption based on the charging/discharging current and the current consumption based on the through current can be reduced by lowering the power supply voltage.

Therefore, in order to reduce the power consumption of circuit devices such as electronic watches and electronic desk calculators, it is possible to consider, for example, operating the internal circuits of integrated circuits (ICs) at a low power supply voltage.

Figure 8 shows that it is possible to reduce power consumption.
A block of IC is shown. In the same figure,
1 is a logic circuit, and 2 is a RAM (random access) whose address is specified by the logic circuit 1 above.
5 is a display drive circuit for driving a liquid crystal display device (not shown); 6 is a level converter for level-converting the display data output from the RAM 2 and supplying it to the input terminal of the display drive circuit 5; It is a conversion circuit. Note that the RAM 2 is composed of a circuit 3 including a memory array, an address decoder, etc., and an input/output circuit 4.

The circuits 1 to 3 described above are operated with relatively low supply voltages, such as 1.5 volts. In contrast, the display drive circuit 5 is operated at a relatively high supply voltage, for example 3 volts, depending on the signal level required by the liquid crystal display. The level conversion circuit 6 is operated at the same power supply voltage as the display drive circuit in order to convert the 1.5 volt signal outputted from the RAM 2 into a 3 volt signal.

In FIG. 8, the internal circuit 1 of the IC has low power consumption due to its low power supply voltage.

However, in FIG. 8, the number of unit circuits in the level conversion circuit 5 must correspond to the number of terminals of the liquid crystal display device. By significantly increasing the number of unit circuits, the number of circuit elements of the IC increases significantly.

On the other hand, if the RAM 2 can be operated at a relatively high power supply voltage, the level conversion circuit 6 can be omitted, and as a result, the number of circuit elements can be reduced. However, in this case, the data bus DBS to which low-voltage signals are supplied must be coupled to the input/output terminals of the RAM2. Accordingly, level conversion circuits with bidirectional operation are required.

Therefore, an object of the present invention is to provide a CMOS integrated circuit having a level conversion function and having a small number of circuit elements.

Another object of this invention is to provide a low power consumption CMOS
Its purpose is to provide integrated circuits.

Another object of the present invention is to provide a low power consumption input/output circuit for RAM.

The present invention will be explained in detail below with reference to Examples.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

In the figure, 1 is a logic circuit, 2 is a RAM, and 5 is a logic circuit.
6 is a display drive circuit, 6a to 6n are level conversion circuits, 7 is a power supply circuit, and 8 is a liquid crystal display device. The various circuit elements for the illustrated circuits 1, 2, 5, 6a to 6n and 7 are formed on one semiconductor substrate by known CMOS integrated circuit technology.

The power supply circuit 7 receives the voltage V _S output from the battery E.
It outputs a relatively low voltage V _SS1 , a relatively high voltage V _SS2 , and various levels of voltage required by the display drive circuit 5 by receiving the voltage V SS1 . This power supply circuit 7 can have relatively low power consumption by being configured with a circuit such as a step-up or step-down circuit that utilizes the charging voltage of a capacitor.

The logic circuit 1 is operated by a low power supply voltage V _SS1 output from the power supply circuit 7, and the RAM 2 is operated by a high power supply voltage V _SS2 .

The logic circuit 1 has a plurality of address terminals coupled to an address bus ABS, a data input/output terminal coupled to a data bus DBS having a 4-bit configuration, and a control terminal for controlling data input/output operations of the RAM 2. have.

The V _SS1 system, that is, 1.5 volt system address signal outputted from the logic circuit 1 is converted into the V _SS2 system, that is, 3 volt system address signal by the level conversion circuits 6a to 6k, and then Supplied to RAM2.

Further, the read control signal a is directly supplied to the RAM 2, and the write control signal a' is converted by the level conversion circuit 6 into a three-level signal a, and then supplied to the RAM 2.

The RAM 2 is composed of a circuit 3 composed of a memory array, an address decoder, etc., and an input/output circuit 4.

Although not particularly limited, the circuit 3 is configured to have read-only address terminals Aa to Ai and address terminals Al to Ak for data input/output.

As will be better understood from the specific circuit example shown in FIG. 4, which will be described later, one set of 4-bit memory cells in the memory array is controlled by the address signal applied to the data input/output address terminals Al to Ak. is selected. This 4-bit set of memory cells serves as a unit circuit 4 in the input/output circuit 4.
1 to 44, respectively.

The above read-only address terminals Aa or Ai
Memory cells in one row of a plurality of memory cells arranged in rows and columns of the memory array are simultaneously selected by address signals applied to the address signals. The data of the plurality of memory cells in one row is supplied to the display drive circuit 5.

The input/output circuit 4 is configured to have a level conversion function.

As a result, the data signal output from the logic circuit 1 can be written to the RAM 2 via the data bus DBS, and various data to be processed by the logic circuit 1 can be transferred from the RAM 2 to the above data. The bus will be able to supply DBS. Furthermore, the data to be displayed is
It becomes possible to output from RAM2.

The display drive circuit 5 is connected to the RAM 2 on the one hand.
By receiving a V _SS2 system display data signal from the power supply circuit 7 and a multi-value voltage from the power supply circuit 7, a drive signal is outputted to drive the liquid crystal display device 8.

The liquid crystal display device 8 is configured to display one digit of a number using a plurality of display segments arranged in a diagonal pattern, although this is not particularly limited.

FIG. 2 shows a specific circuit example of the level conversion circuits 6a to 6n in FIG. 1. The level conversion circuit is an n-channel as shown in the diagram.
MOSFETQ ₁ , Q ₂ , P channel MOSFEQ ₂ , Q ₄
and an inverter circuit IV operated by a low power supply voltage V _SS1 . The inverter circuit IV consists of complementary MOSFETQ ₅ as shown in Figure 3.
Consists of _Q6 .

In the above level conversion circuit, MOSFETQ ₁ and
Q ₂ and Q ₃ and Q ₄ are mutually switched in a complementary manner by circuit connections as shown. As a result, the
In response to the V _SS1 system signal, a signal that is in phase with the signal at the input terminal and converted to the V _SS2 system is output to the output terminal OUT. The output terminal has
V The opposite phase signal of _{the SS2} system is output.

For example, the voltage V _SS2 is supplied to the power supply terminal of the inverter circuit shown in Fig. 3, and
By appropriately setting the sizes of MOSFETs _Q5 and _Q6 , it is possible to output a V _SS2 system signal from this inverter circuit. However, in this case, since the maximum value of the input signal is limited to the value of the V _SS1 system, it becomes impossible to completely turn off MOSFET _Q5 . As a result, when the input signal is at V _SS1 level, the series connected MOSFETs Q ₅ and Q ₆
are turned on at the same time, forming a current path that causes unnecessary current to flow between the power supply terminals. As a result, it becomes impossible to take advantage of the CMOS circuit's advantage of low power consumption.

FIG. 4 shows a specific circuit example of the circuit 3 in the RAM 2. In the figure, MS ₁ to MS _o are memory cells, and MOSFETQ ₇ to MOSFET Q 7 to constitute a flip-flop circuit as shown in the figure.
Q ₁₀ , transmission gate MOSFETs _{Q 11} and Q ₁₂ , and a clocked inverter circuit CI ₄ .

Memory cells MS ₁ to MS _o arranged in the same row
The clock input terminals of the clocked inverter circuit CI ₄ are commonly connected to the read word line W _H1 , and the gates of the transmission gate MOSFETs Q ₁₁ and Q ₁₂ are commonly connected to the input/output word line W _L1 .

One memory cell, for example _S1 , and a memory cell (not shown) placed in the same column as it, have their input/output terminals commonly connected to the data lines _D10 and _D11 , and the output terminals of their clocked inverter circuits are commonly connected. It is connected.

Each data line D ₁₀ to D _o1 is coupled to common data lines CD ₀ and CD ₁ via column switch MOSFETs _{Q 13} to Q ₁₆ , respectively.

The common data lines CD ₀ and CD ₁ are coupled to the input/output terminal I/O via the input/output circuit 10 .

An address decoder circuit DEC ₁ is provided to drive the read word lines W _H1 to W _Hn ,
Further, an address decoder circuit _DEC2 is provided to drive input/output word lines W _L1 to W _Ln and column switch MOSFETs.

The commonly connected output terminals of the clocked inverter circuits in the memory cells in each column are coupled to the input terminals of the display drive circuit 5 shown in FIG. 1, and the input/output terminals I/O are coupled to the input/output circuit 4. be done.

In FIG. 5, 1 in the input/output circuit 4 of FIG.
A specific circuit diagram of one unit circuit 41 is shown.

In the figure, 41a is a write control circuit for writing. This write control circuit 41a is
Clocked inverters connected in series
inverter) circuits CI ₂ and CI ₃ .
The above clocked inverter circuit requires high power supply voltage.
Level conversion circuit 6n as V _SS2 and clock signal
The write signal b converted to the V _SS2 level by is supplied. 41c is a clocked inverter circuit for reading, and 41b is a level conversion circuit.

The level conversion circuit 41b is composed of an n-channel MOSFET 5A and p-channel MOSFETs 5B and 5C connected in series as shown. The gates of the MOSFETs 5A and 5C are connected to a write signal input terminal. Said
The gate of MOSFET5B is connected to the data bus DBS. The read clocked inverter circuit 41c is connected in parallel with the write control circuit 41a between the input/output terminal I/O of the circuit 3 in the RAM 2 and the bus DBS. Furthermore, the write control circuit 41b for writing includes MOSFETs for the input/output terminal I/O and the level converter 41b.
It is connected to the common connection point A of MOSFET 5A and MOSFET 5B. Note that a capacitor 6 substantially constituted by stray capacitance, parasitic capacitance, etc. of the circuit is disposed at the point A. FIG. 6 shows a specific example of a clocked inverter circuit.

FIG. 7 is a time chart for explaining the operation of the circuit shown in FIG. 5, in which a is a read control signal, b is a write control signal, c is a potential waveform at point A of the write control circuit 5, and d is a This is the waveform of input data.

Next, the operation of the circuit shown in FIG. 5 will be explained.

In FIG. 5, when writing data to the RAM 2, a write signal is input to the input terminal 5D. The signal is high (H) as shown in Figure 7.
When level, MOSFET5A is on, PMOS5
C is turned off. Therefore, capacitor 6 is the power source.
Charged to V _SS2 .

Next, when the MOSFET 5A is set to a low level as shown in FIG. 7B (b), the MOSFET 5A is turned off and the MOFET 5C is turned on. At this time, the data signal on the data bus DBS is
If it is low level as shown in figure d,
This means that MOSFET 5B is also turned on. As a result, the charge in the capacitor 6 is discharged, and the potential at point A is brought to a high level of approximately 0 volts. Clocked inverter circuits CI ₂ and CI ₃
is configured as shown in FIG. 6, so that when the control signal b is set to high level, MOSFETs _Q18 and _Q19 are turned on.
Therefore, the high level signal at the point A is transmitted to the input/output terminal I/O via the write control circuit 41a.
It will be supplied to O.

Contrary to the above, if the data signal on the data bus DBS is at a high level, MOSFET 5B is maintained in the off state, and accordingly, the potential at point A is maintained at the low level of V _SS2 by the capacitor 6. . Therefore, a low level signal is supplied to the input/output terminal I/O from the control circuit 41a.

As a result, data corresponding to the data signal level on the data bus DBS is written into the memory cells in the RAM 2.

When the read control signal a is set to a high level as shown in FIG. 7a, the clocked inverter circuit 41c is activated. As a result, the data signal supplied from the memory cell to the input/output terminal I/O is supplied to the data bus DBS via the clocked inverter circuit 41c.
In the clocked inverter circuit 41c, MOSFETs such as those corresponding to MOSFETs _Q17 and _Q20 in _FIG . The switch operates in a complementary manner. Also, in Figure 6
MOSFETs such as those compatible with MOSFETQ ₁₈ and Q ₁₉
Since the power supply voltage is V _SS1 , the switching operation is sufficiently performed by the read control signal at the level of the V _SS1 system.

As explained above, according to the present invention,
Remove the level converter on the data sending side of RAM,
On the data input/output side of the RAM, when writing, the data level is increased through a level converter and when it is written, the data level is lowered and read out through a clocked inverter. The number of wires required can be reduced. the result,
The power supply can be made smaller.

[Brief explanation of drawings]

Fig. 1 is a circuit block diagram of an embodiment of the present invention, Fig. 2 is a circuit diagram of a level conversion circuit, Fig. 3 is a circuit diagram of an inverter circuit, Fig. 4 is a circuit diagram of a RAM, and Fig. 5 is a circuit diagram of an input circuit. Figure 6 is a circuit diagram of the output terminal, Figure 6 is a circuit diagram of a clocked inverter circuit, Figure 7 is a timing chart for explaining the operation of the circuit in Figure 6, and Figure 8 is a circuit block diagram of the IC. . 2...RAM, 3...Write control circuit, V _SS2 ...Write control circuit power supply, CI ₁ to CI ₃ ...Clocked inverter, DBS...Bus, 41b...Level conversion circuit, 5B, 5C...PMOS, V _SS2 ...Level Transducer power supply.

Claims (1)

[Claims] 1. A RAM that has a relatively small number of first data terminals and address terminals and a relatively large number of second data terminals and is operated at a relatively high voltage, and a RAM that is operated at a relatively low voltage. a logic circuit; and a plurality of circuits that convert a low-voltage address signal output from the logic circuit into a high-voltage address signal to be supplied to the address terminal.
a CMOS level conversion circuit; a plurality of second CMOS level conversion circuits that convert low voltage data signals output from the logic circuit into high voltage data signals supplied to the first data terminal; and a signal supply circuit that supplies the data signal of the terminal to the logic circuit.
CMOS integrated circuit. 2 The address terminals include a first address terminal for coupling the first data terminal and a memory cell in the RAM, and a second address terminal for coupling the second data terminal and a memory cell in the RAM. A CMOS integrated circuit according to claim 1, characterized in that the CMOS integrated circuit comprises: 3. The CMOS integrated circuit of claim 2, wherein the second data terminal is directly coupled to an input terminal of a sign drive circuit operated at a relatively high voltage. 4. The CMOS integrated circuit according to claim 1, wherein the signal supply circuit comprises a clocked inverter having a CMOS configuration.