JPH01502860A - General-purpose processor unit for digital data processing systems including virtual-to-physical address translation circuits - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] A general-purpose processor for digital data processing systems that includes a virtual-to-physical address conversion circuit. SUUNIT Hikari - Medical 12 - Noboruichi 1. Industrial application field FIELD OF THE INVENTION The present invention relates generally to the field of digital data processing systems.

2. Conventional technology A standard digital data processing system has three basic elements: It contains a storage element, a storage element, and an input/output element. Memory element is address Store information in a memory location that can be accessed. This information includes data and Both instructions are included. The processor element may include one or more digital Contains data processing units or "processors," each of which stores information. command or retrieve incoming information from an element to or from it. Interpret it as any data and process that data according to your instructions. the result is then stored at the addressed location within the storage element.

Input/output elements are also used to transfer information into the system and obtain processed data from it. Units containing zero output elements that also communicate with storage elements usually have processor elements that It operates according to the control information supplied to it. Control information describes the operations that an input/output device should perform. Define peration. One of the operations that an input/output device should perform The class contains at least the user information, i.e. the class used by the user program. transfer of information between an input/output device and a storage element. A mark containing input and output elements Examples of quasi-units include printers, teletypewriters, and video display terminals. and may also include disk or tape storage.

In addition to serving as input/output devices, disk storage and sometimes tape storage The device can also function as part of a storage element. In particular, storage elements are standard can access its contents to the processor relatively quickly, but generally at a high cost. It contains one main memory which is a storage device. Modern main memory is typically M It is made using OS or bipolar semiconductor technology and is a fraction of 1 megabyte. It can provide up to tens of megabytes of storage.

Modern data processing systems include arithmetic system programs that are useful for application programs. For example, if the programmer uses a large virtual memory space, Many computing systems support addresses, while the computer's own physical memory Relatively small.

This computing system is used for large-capacity programs such as disks. It stores a large amount of memory space and stores that data physically when a program needs it. transfer to physical memory. This computing system is based on the virtual memory used by programs. The translation between the address and the physical address that indicates the memory location where the data is actually stored. Translate.

In an exemplary system, translation between virtual and physical addresses is performed. In order to Create a table containing the communication between.

To reduce the number of entries in this table, add entries to addressable locations. Rather than obtaining a number of pages, the locations are categorized into pages, and this number of pages is divided into selected numbers (in this example system). (512 bytes per page). And there are many pages of entries. Each entry in a table called the 0-page table given for The high-order part of the virtual address, which is the "number of systems," and the high-order part of the corresponding physical address. Contains. The low-order part of this virtual address is the appropriate high-order part of the apparent physical address. The parts are concatenated together to form the entire physical address.

In this computing system, programs can simultaneously run data on data in memory. ) Multitasking is also possible. With this system, e.g. compiler, assembler, Other functions such as debuggers, communications, etc. are also provided. Data is It is shared among several programs, and -S is used to store data in memory by programs. It is desirable to adjust read and write capabilities. For example, if the application program It is undesirable to write data to a location that is currently being used by a processing system. However, the application program may read data stored in at least some of its locations. It is desirable to have one application program read the data and write the data, but limit it to having another application program write the data one after another. is desirable.

Instead of having multiple copies of the same data, share or duplicate access to the same data The program uses the appropriate error code behind the scenes for programs that must access the data. This can also be achieved through entry. In this way, shared data is shared between both programs. virtual address space, but the virtual address location will be different, but the device The same physical location is identified by translating the data into a physical address. data i.e. to adjust each program's access privileges to that program is only reading data, only writing data, or is reading data Multi-page table entries can be programmed to adjust whether they are Contains a protected field containing a code indicating the RAM's access privileges to the data.

To speed up the translation between virtual and physical addresses, modern processors use , a small cache of table entries for pages that have just been used. It generally includes a translation buffer. This entry is for page frame tables and Contains both code that identifies the program's access privileges. Address translation During the process, the processor first checks whether the page's table entry is in its translation buffer. Check it out. If so, the processor uses the page's table entry in the translation buffer use lee. Does the program access the data to perform the necessary operations? To determine whether the processor decodes the encoded protection field .

However, if the page's table entry is not in the translation buffer, or if the program If the processor does not have the necessary access rights to that data, the processor action must be taken.

The processor must perform other operations as soon as possible to speed up processing. It is desirable to decide whether the

of · The present invention provides a new processor for use in digital data processing systems. .

This processor has a Contains translation buffers for table entries on pages that contain. Entries in this translation buffer The protection code is decrypted before being loaded into the The higher bits of the virtual address and A direct comparison is made between the frame number of the page and the program activity in that buffer. A direct comparison is made between the access rights and the decrypted access rights to ensure that the comparison is successful. A ``bit'' signal is generated to indicate the status.

Since the protected code has been decrypted in its translation buffer, subsequent decryption is required. The comparison is done directly without the need. Therefore, the processor uses the translation buffer It can be immediately determined whether the content of the

Simple i in the drawing The invention is pointed out with particularity in the appended claims.

The above-mentioned and other advantages of the present invention will be apparent from the following description in conjunction with the accompanying drawings. It is believed that it can be better understood by looking at the following. In the diagram: FIG. 1A shows an overall block diagram of a digital data processing system incorporating the present invention. Figure 1B is a diagram of the system used within the system shown in Figure 1A. 1 is an organizational block diagram of a processor.

FIG. 2 includes FIGS. 2A to 2D and is helpful in understanding the present invention. This is a timing diagram.

Figures 3A, 3B and 3C relate specifically to the transmission of information through the data path. Figure 1B is a block diagram of a portion of the processor shown in Figure 1B. Ru.

Figure 4A is a detailed block diagram, Figures 4B-1 and 4B-2. The diagrams are particularly shown in Figure 1 regarding the translation of virtual addresses to physical addresses. 2 is a more detailed circuit diagram of a portion of the ProSensor; FIG.

FIG. 5 is illustrated in FIG. 1B with particular reference to data retrieval from cache storage. 1 is a detailed block diagram of a portion of a processor.

FIG. 6 specifically relates to a circuit for controlling transfers to and from other parts of the system. 1B is a detailed block diagram of a portion of the processor shown in FIG. 1B; Ru.

1, k -thin-' main control Referring to FIG. 1, a data processing system incorporating the present invention has as basic elements Central processing unit CPU101 storage mechanism 11 and one or more input/output subsystems system 12 (one input/output subsystem is shown in Figure 1) . A bus 13 connects the CPU 101 storage unit 11 and input/output subsystem 12 in parallel. interconnected. CPUl0 is an addressable memory within the storage mechanism 11. Execute instructions stored in a location. Instructions are also addressable in storage. identify operations to be performed on operands stored in available locations do. Instructions and operands are fetched by CPU10 as needed and processed data is The data is returned for storage in storage 11. CPU10 also has an input/output sub transmitting control information to system 12 and transmitting data to or from storage 11; These subsystems perform selected operations, such as retrieving data from It can be so. Such data may include instructions or commands that may be transmitted to storage 11. Processed data retrieved from memory 11 for storage or display It is possible that it is included.

The operating keyboard mechanism 14 is used as an operator interface. This is it The operator inspects and deposits the data or stops the operation of CPU10. or step CPU10 through a series of instructions, or in response to The response of CPU10 can be determined. This also allows the operator to Use the bootstrap procedure to initialize the system and complete the data processing system. Various diagnostic tests can also be performed on the body.

Data processing systems include disk and tape secondary storage, teletype printers, computers, video display terminals, line printers, telephones and computer networks. It is assumed that various types of input/output devices 20 are included, including a network unit, etc. available. All these units are connected to the device motherboard through one or more control devices 22. Mother through line 21! I am in contact with 13. control device 22, connected thereto; The input/output device 22 communicating with the device bus 21 and the control device is connected to one input/output sub The system 12 is configured.

Memory mechanism 11 is my mother! *13 and storage directly connected to multiple arrays 17 It includes a control device 15. Array 17 includes an addressable array 17 in which information is stored. Multiple storage locations are included. The storage mechanism control device 15 is CPLIIO or input/output A transfer request is received from the subsystem 12 through the bus 13. through busbar 13 There are several types of transfer requests that can be sent, generally falling into two categories: Can be divided. In one category, the information is written in one memory location or In the other category, information is retrieved or read from a storage location. Ru.

The system shown in FIG. 1 also connects busbar 13 and storage controller 15. and intercepts the write transfer request directed to the storage mechanism 11 by CPU10. It also includes a write buffer 23. In this system, storage mechanism control device 1 5 is transmitted through the bus 13 by either the CPU 10 or the input/output control device 22. In particular, the write buffer 11 does not respond to write requests sent.

Identifying the data to be written and the location within array 17 where the data is to be stored buffer the write information, including both associated addresses. written by storage controller If the write buffer can only accept operations, the write buffer is 24 to transmit the address and accompanying data to the storage mechanism controller 15, and The controller allows array 17 to store data at locations identified by addresses. Do it like this. In this way, the data written by the CPU 10 is transmitted through the bus 13. If the transfer rate becomes too high for storage 11 to accept, write buffer 2 3 can buffer requests until storage 11 can accept them. . The storage mechanism control device receives a read request from the CPU10 or the input/output control device 22. In order to respond to this request and return read data, it is also directly connected to bus 13. Ru.

Those skilled in the art will appreciate that a write buffer can be configured within a uniprocessor system as shown in FIG. One would think it would be advantageous to use a multiprocessor system. Most advantageously, it is used within a stem (not shown). multi-process In a processor system, storage 11 has many CPUs and associated inputs. Read and write requests will be received from the output system 12.

Avoid delaying processing by CPU10 while waiting to perform a write operation. To avoid this, the write buffer 23 takes the write address and data and sends it to the CPU. l0 can resume processing.

The write buffer also monitors read requests from CPU10 through bus 13. Contains circuitry to do so. Buffered by itself and still transferred to storage mechanism 11 Verify that a read request was transmitted over bus 13 that identified data that was not If so, the write buffer 23 is connected to the storage controller through its dedicated bus 24. restrain the company from responding to the request. Instead, the write buffer 23 is 13 to transfer the requested data and complete the read operation.

The system shown in Figure 1 also includes arbitration (optional) under the control of CPU10. When an operation is executed and there is more than one in the system, various changes are made to bus 13. It also includes system control circuitry 25 for regulating access to the input/output subsystems. It is.

CPU10 includes a processor 30 and an optional floating point processor 31. I'm reading. As is standard, floating point processors are CPU or digital data processing system made according to the present invention. The floating point processor, which does not necessarily have to be in system 10, has a type data, i.e. data in floating point format. Contains optimized circuits. Typically, processors 30 use the same data data, but the process takes more time to perform.

Detailed functional block diagram of one processor 30 used in the system The ram is shown in Figure 1B. Referring to FIG. 1B, processor 30 includes: Connect to various control lines of busbar 13 (collectively designated as 13A) and send and receive signals through the various lines of the busbar as described below. A busbar interface circuit 33 is included. This busbar interface The circuit includes a cache 35, a data path 36, a storage management unit 37 and a processor. Also connected to internal IDAL bus 34 for transferring signals to and from control circuit 40 are doing. Busbar Interface Circuit 3 for One Embodiment of Processor 30 3 is described below in conjunction with FIG.

A number of resistors are also connected to this internal TDAL bus 34 and are connected to the bus interface. DAL line 50 of bus m13 and internal IDAL bus 34 under the control of chair circuit 33 Transfer data between. Specifically speaking, the busbar interface unit 33 write data register 250 and write address register 251 under the control of are the write data and the storage mechanism 11 in which the write data is stored, respectively. Receives the address of a location within the input/output device 12. As explained below, At an appropriate time, the busbar interface unit 33 determines the contents of these registers. A write operation is transmitted on DAL line 50 through multiplexer 253. to allow the option to be executed. Similarly, the bus interface unit 33 Under control, the read address register 252 is set to Receive the location address. At an appropriate time, the busbar interface unit 33 The contents of read address register 252 are sent to the DAL register through multiplexer 253. 50 so that read operations can be performed. I will do it. The read data is in input register 253 and is also sent to the bus interface. The busbar interface is latched (held) under the control of the chair unit 33. The input register 254 is the data signal received by the RCV DAT. can be coupled onto the internal IDAL bus 34 as a signal.

The processor control circuit 40 decodes the program instructions retrieved from the storage 11. , in successive processing cycles the data path 36 is required to execute the instruction. to perform arithmetic and logical operations. The data path 36 is A set of registers 255 for storing data to be processed and a set of registers 255 for storing data to be processed. Contains arithmetic logic circuits. For data path 36, see FIGS. 3A and 3B. are explained in more detail below.

One embodiment of processor 30 uses virtual addresses and converts virtual addresses to physical addresses. A virtual address conversion circuit 37 is provided for converting the address into a virtual address. virtual address translation times The virtual address path includes other circuitry within processor 30, particularly the data path 36. A set of primitive registers 257 that receive the translations and a translation buffer containing some translation information. A file 260 is included. Conversion is controlled by the processor control circuit 40 as necessary. It takes place below. The physical address is sent from the conversion circuit 37 through the multiplexer 261. and is coupled onto the internal IDAL mother vA34. Data path 36 also includes a second primitive input for multiplexer 261. provide strength. Processor control circuit 40 controls multiplexer 261.

Cache storage 35 is a conventional information storage circuit within CPU10. Cash Hwang and F. Br1gg5, “Computer Storage Mechanisms” "Architecture and Parallel Processing" (McGraw-Hill, 1984), Section 2.4 , p. 98 et seq., and V.) Lamacher, "Computer Organization" (McGraw-Hill, 1984), Section 8.6, p. 306 et seq.

The data storage 38 is Al1 woven in the form of a plurality of blocks, each block having two Contains storage locations. Each memory location stores one information word, i.e. mother at a time. &113. Stores the amount of information that can be transferred through &113. In one particular embodiment , one information word corresponds to 4 bytes or 3202 binary information. In this way, each blog A block can store 8 bytes of information.

Cache storage, as described in more detail below in conjunction with FIG. The mechanism 35 caches the physical address generated by the virtual address translation circuit. Hit/miss logic circuit that determines when it corresponds to one address in the storage mechanism 35 262, the lowest part of the virtual address from primitive register 257, including That is, in one embodiment, the VA 5RCE (8:3) signal is Multiplex to select one block in the area and 41 associated tags. 264. Hit/miss logic circuit 262 then connects It is determined whether the input contents of the rejected tag 41 match the converted physical address. Set.

If there is such a match, the hit/miss logic generates an asserted BIT signal. , this signal is transmitted to the busbar interface unit 33. busbar interface If the face unit 33 does not receive the asserted BIT signal, it uses the conventional method to one operation through bus 13 to retrieve the contents of the scanned location. make it available for use. If the HIT signal is asserted, the bus interface The bus unit 33 does not enable operation through the bus 13; Data from cache data storage 38 is then routed through internal IDAL bus 34. The signal can be transmitted through multiplexer 263. In general, the data is transmitted to data path 36.

As will be apparent to those skilled in the art, one block within cache storage 35 The stored information is stored in the storage device 11 when it is received from the storage device 11. This is a copy of the information provided. Each block within the cache storage mechanism 35 includes: The bus interface is used to identify the location in storage device 11 from which the information was copied. There is one tag 41 associated with the content created by the face circuit 36. Ru. Additionally, each block has a tag that identifies the content of the block. whether it is in the actual copy of the block, i.e. whether the contents of the block have expired. reset or cleared by the busbar interface circuit to indicate whether A revocation flag 42 is included.

In one embodiment of cache storage 35, data storage 38, tag 41 and Flag 42 is a dynamic storage mechanism. The regeneration counter 262 is connected to the bus interface. Under the control of the control unit 33, a playback address is generated, and this address is stored in dynamic memory. It is coupled through multiplexer 264 to reproduce the mechanism.

One instruction includes identifying the location of an operand in a register within data path 36. or an address that identifies the location of the operand within the virtual address space. may contain multiple operand specifiers.8For example, 19801 “Variable length notice” issued on January 25th to Id, S, 5trecher, etc. U.S. Patent No. 4.236.2 for ``Central Processing Unit for Executing Instructions'' 06, the processor control circuit 40 has a data path as well as a Decode the land specifier to identify the location of the operands, and then We will proceed with the work to obtain what we can from the place. An operand specifier itself contains its operands. (i.e. operand specifiers can be “literal”) ), and operand specifiers are used to specify the data path as containing the operand. One of the registers (not shown) may also be identified.

Alternatively, the operands are located at one location in the program's virtual storage space. The operand specifier may indicate how this location is identified, and the operand specifier may indicate how this location is identified. If the address is in the virtual storage space, the control circuit 40 indicates that the storage management circuit 37 address to a physical address. The physical address of the operand is obtained. After that, the bus interface 33 obtains the operand. This is the operation first. Determine whether the land is in cache storage 35. If the operand is the bus interface stores its operands in data storage. Transfer to route 36. On the other hand, if the operand is not in cache storage 35, The bus interface circuit 33 sends a read request to the storage mechanism 11 through the bus 13. transfer and retrieve its operands. After all operands are obtained, the data path 36 performs the operation control required by the instruction.

The operand specifier also identifies where processed data should be stored. control The circuit 40 and the storage management circuit 37 are similar to those described above for determining the physical address. used in the same way. The processed data must be stored in the storage mechanism 11. If not, the bus interface 33 will host the required write operation. through line 13, and the physical address is placed on the appropriate tag in cache 35. If so, the bus interface 33 stores the data in the cache 35. make it possible for you to do so.

The bus interface unit 33 includes a device that controls data transfer through the bus 13. control state machine 270 as well as the transfer of data through internal IDAL bus 34. An IDAL state machine 271 is included to control the transmission. busbar interface The unit also controls an EPP logic circuit 272, whereas this circuit 272 is a floating point Controls communication with the processor 31. The busbar interface unit 33 is as follows. This is explained in more detail in conjunction with FIG.

Operation using 13 Bus 13 carries signal numbers representing information between the various units connected to it. Contains many lines for transmission. Especially for my mother & 113, D DAL (31:0) data carrying AT data and ADRS address signals Address lines 50 are included. In terms of CPUl01, Prosensor 3 If 0 initiates one transfer and makes it the bus master for that transfer, then The processor 30 first passes through the DAL (31:O) data address line 50. Transmits the ADRS address signal, and the transfer operation reads the operating controller. TRTYPE (2:0) transfer indicating whether it is a write operation or a write operation. type command signals are simultaneously transmitted through line 52. ADRS address signal and TRTYPE (2:0) transfer type command signal can subside. After a short period of time, processor 30 then issues an ADR3STR address on line 51. Assert the rest strobe signal.

When the ADR3STR address strobe signal is asserted, it is connected to bus 13. All other units have ADRS address and TRTYPE (2:O) Receives and decodes the transfer type command signal. At this time, the ADRS address signal The unit containing the location being identified is the responding unit for transfer, i.e. child gW<slave), the transfer operation is a write operation. If the ADRS address signal identifies a location within storage 11, the write buffer The buffer 23 is a child device. The processor 30 uses the ADH3RTR address controller. After asserting the AD signal for a selected period of time, processor 30 RS address signal and TRTYPE (2: O) transfer type command signal respectively. Remove from this line.

Transferred TRTYPE (2:0) Transfer type command signal is write operation The master unit sends the data signal through line 50 if the transmit and then assert the DATA STR data strobe signal on line 53. . At this time, the slave device receives the transmitted data and stores it. data is recorded Once stored, the atranged unit will ensure that the operation completes without error. If completed, the RDY ready signal is sent on line 54, and the memory operation If a medium error occurs, an ERR error signal is asserted on line 55.

On the other hand, the transmitted TRTYPE (2:0) transfer type command signal is read and activated. If operation is specified, the child device is located at the location identified by the address signal. Search for data from DAL (31: O) data address line 5 o and transmits an asserted RDY ready signal through line 54. Ru.

In response, processor 3o receives the data and asserts DATA ST An R data strobe signal is transmitted over line 53.

In either read or write operations, the child device is the RDY ready signal or the ERR error signal if an error occurs during transfer. After asserting, the processor 3 denies the DATA STR data strobe signal. do. The slave device then negates the RDY ready signal or the ERR error signal and then The processor 30 negates the ADR3STR address strobe signal to complete the transfer. Complete.

Units connected to the bus m13 other than the processor 30 constitute a bus master. Through this, transfer with the storage device 11 can be started. input/output sub System 12, particularly its input/output controller 22, can become a bus master.

To become a bus master, I/O controller 22 connects directly to the DMR through line 56. The zero-order processor 3o asserting the direct storage request signal connects the DMG directly on line 57. Asserts a storage permission signal, which signal is received by input/output controller 22. child At this point, the input/output controller is as described above with respect to processor 30. Initiate transfers to and from storage in the same manner. I/O controller completes the transfer The DMR direct storage request signal is maintained asserted until. In this way, input/output system If the controlling device requests a large number of transfers, the device will use DMR until the transfers are complete. The direct store request signal can be kept asserted. DMR direct storage request message While the signal is asserted, processor 30 is in a stalled state, i.e., the processor 30 is The server monitors signals on the various lines of bus 13, but does not give any other commands. Not executed.

If the system includes many input/output subsystems 12, one bus master Separate request signals to become the input/output controller 22 are transmitted to the system controller. Is this system control device D? Asserts the IR direct storage request signal and writes directly to the DMG. Monitor the state of storage permission signal. Processor 30 asserts DMG direct storage permission signal , the system controller assigns one of the input/output devices 22 to an arbitrary priority Make it possible to become a bus master according to the determination method.

Bus 13 also has a number of other lines carrying status and control signals. There is. Line 6o is used to synchronize operations within the system CLK carries the clock signal.

The various signals on bus 13 are timed in response to the CLK clock signal. ing.

Line 61 carries a CCTL cache control signal that has two functions. 19 Paul Rnbinfeld submitted on September 12, 1986 U.S. Special Edition on ``Cache Invalidation Protocols for Digital Data Processing Systems.'' As noted in co-pending application No. 908.825, CCTL CA For example, if the input/output control device is the bus master and the bus control signal is stored in the storage device 11, If a write operation is being performed on the be done. The input/output control bag 222 provides an ADRS signal on the DAL data address line 50. address signal while transmitting the TRTYPE transfer type signal on line 52. , and asserting the ADR5STR address strobe signal on line 51. During this period, the CCTL signal is asserted. CCTL cache control signal is asserted and TRT YPE transfer type signal indicates write operation to storage 11 In this case, the bus interface 33 checks the contents of the tags 41 of all cache inputs. Check. ADR3 signal on DAL data address line 50 of mother 11113 matches the contents of the tag 41, the bus interface 33 caches the cache. Reset the S revocation flag 42 for the block.

The CCTL cache control signal also controls the cache requested during read operations. In order to prevent the processor from storing data in the storage 35, the storage mechanism 11 It is determined by This is true, for example, if the storage is multi-vote storage. That is, it has multiple The data being retrieved is shared by the processors and the data being retrieved is shared by these processors. Used if all are from a set of available addressable storage locations. can be done. It is desirable to store such data in cache 35. No, because other processors may update the contents of the shared location. It is. Also, since updates are not performed through bus 13, they are not detected by processor 30. Processor 30 has used such data from the cache without being aware of it. This may not match the contents of the appropriate location in storage. this In conjunction with the use of CCTL cache control signals, storage 11 stores DAL data. CCTL cache control signals are sent concurrently with the data transmission through address lines 50. This CCTL cache control signal is asserted until the point at which the data is removed. maintain the condition.

Bus line 13 also includes a line that carries CCRWRT BUF erase/write/buffer signals. 62 is also included. CLRWRT BUF Erase Write Buffer Signal is a condition internal to the processor 30 that is not detectable outside the processor 30. 0 asserted by processor 30 in response to when executing an instruction that switches the process context or during a business interruption routine or example. When you start executing an external routine, the CLI? WRT BUF erase/write buffer signal Decide. CLRWRT BUF erase write buffer signal is used by the processor during instruction execution. controlled by fields within the microinstruction generated by the control circuit 40. .

CLRWRT　BUF When the erase write buffer signal is asserted, the write buffer 23 determines whether it contains data to be stored in the storage mechanism 11. Ru. If it does not, do nothing, but add storage to the write buffer 23. If the ll contains data to be stored, this buffer is directly Assert the storage request signal and continue attempting to store the remaining data in storage Let's go. In response to the asserted DMR direct storage request signal, the processor performs a DMG direct storage request signal. The storage permission signal is asserted, but this signal is ignored by write buffer 23. Matatapu The processor also shuts down. The write buffer 23 contains all data The DMR direct storage request signal is asserted until it is properly stored in the storage device II. Keep it in a clean condition. If no errors occur during storage, write buffer The processor 23 negates the DMR direct storage request signal and allows the processor 30 to continue. Ru.

If an error occurs while writing to the storage mechanism 11, the write bumper 23 sends an error signal to the pro-sensor 30, which detects the error in the current context. To be able to process a routine that corrects the offset. error detected If the processor is ready to switch contexts before Determining the context becomes difficult. Error recovery is easier if the context can be identified become. Therefore, the write buffer 23 stores all of the data from the current context. Prevents the prosensor from switching contexts until it is properly stored within the mechanism.

(1) Figure 2A and Indicates the operation to be performed, as described below in association with In order to transfer the instruction code of the floating point instruction to the floating point processor 31, (2) floating for processing as described in connection with Figures 2B and 2C; In order to enable operand data to be transferred to the decimal point processor 31, (3) Floating point processor 3 as described in connection with FIG. 2D. 1 is also connected to a floating point processor 31 to obtain processed data from . The processor 30 and the floating point processor 31 are CP STA (1:O ) floating point status signal carrying line 70 and CP DAT (5:0) floating interconnected by two sets of lines, lines 71 carrying point data signals. It is. Floating point processor 31 also connects DAL data address lines 50 . Line 60 for receiving CLK signal, ADR3STR address strobe signal line 51 for receiving the signal, line 5 for receiving the RDY ready signal. 4. Line 55 for receiving ERR error signal and DMG direct storage permission signal It is also connected to multiple lines of bus bar 13, including line 57 for receiving Ru. CP STA (1:0) floating point status signal and CP DAT (5: O) The floating point data signal is transmitted synchronously with the CLK signal on line 60. Ru.

While in the idle state, floating point processor 31 outputs CLK on line 60. The state of the signals on lines 70 and 71 is sampled synchronously with the signal. Rai floating when at least one of the pins 71 is carrying an asserted level signal. Decimal point processor 31 runs the signals on these lines and the signal on line 70. Ching. Referring to FIG. 2A, processor 30 processes floating point processor 3 1, the processor 30 transmits at least the instruction code of the instruction. also for a period defined by a selected number of continuous tones of the CLK clock signal. CP DAT (5:0) floating point data signal through line 71 during the interval It is transmitted to the floating point processor 31 as follows. During this interval, CLK Kurofuku signal Synchronous with one of the signal sequences, floating point processor 31 launches the signal. Remember. At the end of this interval, the prosensor 30 switches to lines 70 and 71. remove the signal.

The CP DAT (5:00) floating point data signal sent via line 71 is , is sufficient to identify the floating-point operation to be performed, and Also identifies the number of operands used. Information transmission via line 71 and At the same time, other information is sent to the CP5TA (1:00) line as a floating point status signal. 70, which also provides other information regarding floating point processing. It is. That is, floating-point operands have several types called data types. information about the formant of the operand. is sent as a CP5TA (1:00) floating point status signal over line 70. It will be done.

In one embodiment, some of the information about the formants of the operands is also performed. It is sent via line 71 along with calculation information.

Upon receiving the operation code, the floating point arithmetic processing unit 31 decodes it and executes it. Next, the arithmetic processing unit 30 ( (responses to operation code transmission) and floating point arithmetic processing unit 31 (responses to operation code reception) A) is the state in which the operand is sent via the DAL data address line 50. becomes. The data type information is sent to the floating point processor 31 for each of the operands. It is used to determine the formant of each. Regarding the operand format more data than can fit in a single transmission via DAL data address lines 50. A single operand is required because the operand format consists of several bits. Multiple transfers are required to transfer the code. So the data type information is , necessary to transfer each operand, transfer via AL data address line 50. It also shows the number of times it has been sent.

The operands come from three sources: memory 11 (Figure 1), Kersh 35, or any of the processor registers in data path 36 (shown in FIG. 3A). It is stored separately. The various operands required for a single operation are also derived from these three sources. It can be stored anywhere. However, to transfer a single operand, DA If the transfer via the L data address line 50 needs to be performed multiple times, then All transfers are normally made to a vehicular source.

Figure 2B shows the state of the signal sent to retrieve the operand from memory. and FIG. 2B and 2C show the signals sent to transfer the DAL It shows the state of the signal that performs one transfer on the address line 50, It should be understood that multiple transfers may be required for a single operand. It is.

See Figure 2B. If the operand is in the memory 11, the arithmetic processing unit 3 0 starts its collection from memory 11. That is, the arithmetic processing unit 30 Output the address signal to the DAL data address line 50 and read it as described above. performs the address strobe operation and asserts the ADR3STR address strobe signal. that short time After the interval, the arithmetic processing unit 30 converts the CP 5TA (1:00) floating point status signal into binary output to line 70 with value 0, i.e. both CP 5TA (1:00) floating Negates the floating point status signal. Furthermore, the arithmetic processing unit 30 has a CP DAT (5: 00) floating point data signal to line 70 where it is sent to CP DAT (5 :4) Floating point data signals are sent via DAL data address lines 50. An address that indicates how much of the transmitted data is used by this operand. Contains the alignment code.

The operand is a short literal on the DAL (5:O) data address line. If CP DAT (0) floating point data signal is asserted, otherwise C P DAT (1) Floating point data signal is asserted.

The floating point processing unit 31 has already received the calculation information in the procedure described above in connection with FIG. 2A. The device is ready to receive operands. Claimed CP DAT (5: 0) floating point data signal is sent to floating point arithmetic processing unit 31 On the other hand, selected lines of bus 13, in particular the ADR3STR address strobe Instructs to sample the signal on the line 51 carrying the signal.

The floating point arithmetic processing unit 31 uses the ADR3STR address strobe signal. and determines that the operand has been retrieved from memory 11. If so, When it receives an asserted CP DAT(5:0) floating point data signal ADl? S When the STR address strobe signal is asserted, floating point operations The controller 31 responds to the assertion of the RDY ready signal on line 54 by the memory 11. In response, the data signal on DAL data address line 50 is latched. Arithmetic processing The management device 30 responds with the DAT STR data strobe signal and completes the transfer. let

If memory 11 is asserted ERR instead of asserted RDY ready signal If responding to a retrieval request with an error signal, the floating point arithmetic processing unit 31 It is understood that the transmit data on the AL data address line 50 is not latched. The processing unit 30 may perform error recovery actions such as retry that may be required. If an action is requested, it is performed and the operations shown in Figure 2B are repeated.

FIG. 2C shows that whether the operand is in the cache 35 or in the data path 36, The operand is transferred from the processing unit 30 to the floating point FIG. 3A is a timing diagram useful for understanding the transfer to the processing unit 31 (FIGS. 3A and 3A). (described below in connection), in either case, the processing unit The data signal on reply line 50 and the same symbology as described above in connection with FIG. 2B. CP DAT (5:0) floating point data signal and CP 5TA (1:00) Negate both floating point status signals. These signals is maintained by the processor 30 for the duration of a selected number of CLK clock signals. Ru. During that period, the floating point arithmetic processing unit 31 is connected to the DAL data address line 5. The signal above 0 is latched. - DAL data to transfer the entire operand If multiple transfers via address line 50 are required, the The sequence is repeated.

The data type of the operand requires a DAL data access to transfer the entire operand. If the data type requires multiple transfer via the dress line 50, the calculation The processing unit 30, memory 11 and floating point arithmetic processing unit 31 process all operands. Repeat the operations shown in Figures 2B and 2C until the body is transferred.

The operating sequence shown in Figure 2B is identical to that shown in Figure 2C, with the following differences: It will be understood that the sequence of operations shown is similar to that of CP D AT (5:00) ADR3STR address when floating point data signal is asserted If the strobe signal is asserted on line 51, floating point processor 3 1 sends the asserted RDY ready signal to the operand (or part of the operand). ) is currently on the DAL data address line 50. . However, when the CP DAT (5:00) floating point data signal is asserted ADRS STR If address strobe signal is not asserted, floating point operations The processing unit 31 asserts the CP DAT (5:00) floating point data signal as an output signal. The operand (or part of the operand) is then on the DAL data address line 50. Use it as an indication of what is above.

In both cases, the floating point arithmetic processing unit 31 uses the RDY register in the first case. After receiving the Dee signal, the asserted Co DAT (5:00) floats in the second case. After receiving the floating point data signal, in synchronization with the CLK clock signal on line 60. Launch the signal on DAL data address line 50.

After the operands are transferred, the arithmetic processing unit 30 and the floating point arithmetic processing unit 31 is the arithmetic processing when the floating point arithmetic processing unit f31 is processed to send the result. The device 30 is then arranged to receive it. Figure 2D shows the processed In order to transfer data to the processing unit 30, the processing unit 30 and the floating point FIG. 3 is a timing diagram showing in detail an operation sequence used by the calculation processing device 31. FIG.

The processed data indicates whether the result was negative or zero and provides information about the result. status code indicating other selected facts and the floating point arithmetic processing unit 31 and a data signal representing the value of the calculation performed.

See Figure 2D. Initially, processing unit 30 receives signals via lines 70 and 71. code to indicate that it is ready to receive processed data. In the example, both CP5TA(1:OO) floating point status signals negated, CP DAT(3) floating point data signal asserted, others negated . Floating point processor 31 can then transmit via lines 70 and 71. Ru.

Floating point arithmetic processing unit! 31 is the state when the processed data can be transferred. At the same time as the CP DAT (5:0) floating point data signal representing the state code, CPSTA (1:OO) floating point status information representing the code for that effect. send the issue. The floating point arithmetic processing unit 31 executes a selected number of CLK clocks. Keep these signals for the duration of the signal and then transfer the data signal to the DAL data address. output on line 50 and code for that effect on lines 70 and 71. Output to. DAL data address line to transfer processed data signals. When multiple transfers via the link 50 are required, the floating point arithmetic processing unit 31 These are transferred in synchronization with the K Kurofuku signal.

While the floating-point processing unit 31 is processing the operands, the result is sent to the processing unit 31. Before transmitting data to the processor 30, the processing unit 30 inputs and outputs the input/output subsystem 12 from memory. -11, the DMG direct memory permission signal that allows transfer between It can be stretched. The arithmetic processing unit 30 is in a state where it can receive processed data. After the processing unit indicates that the floating point processing unit 31 Monitor the status of 7. Floating point arithmetic processing unit 31 can return processed data If the DMG direct memory grant signal is asserted on line 57 when , the floating point arithmetic processing unit 31 uses the DMG signal to return the processed data. Delay until after is denied.

Also, an error occurs when retrieving an operand from memory 11, for example. Then, the arithmetic processing unit 30 receives the processed data from the floating point arithmetic processing unit I31. The arithmetic processing unit 30 does not indicate that it wishes to believe in the operation of the floating point arithmetic processing unit 31. rather, arithmetic processing unit 30 generates a new opcode in a floating-point operation. When sent to the arithmetic processing unit 31, the floating point arithmetic processing bag fi31 operates with that arithmetic code. make Indicates that the arithmetic processing unit 130 is ready to receive processed data. , CP 5TA( 1:00) Floating point status signal and CP DAT (5:00) Floating point data signal What is the number in order to enable the floating point arithmetic processing unit 31 to distinguish between them? It will be understood that this cannot be achieved if it also corresponds to the operation code.

Eni L-diameter supervisor l The data path 36 of the processing unit 30 will be described in conjunction with FIGS. 3A and 3B. Ru. Referring to FIG. 3A, data path 36 is designated GPO through GP14. A set of 15 general-purpose registers and 16 indicated by TEMPO or TEMP 15 81 primary sisters and 8 working registers designated as WO to W7 -82 sets of registers. Also, the data meridian 36 is It includes an arithmetic logic unit 83, which is connected to the ALU@control circuit 84. The ALU performs arithmetic operations on data from several sources under the control of the CTRL control signal. The ALUwJ controller 884, which performs logic operations and logic operations, is controlled by the control circuit 40 ( Controlled by the ALU OP SEL operation selection signal provided from Figure 2) (Figure 3C). The data used in arithmetic logic unit 83 is stored in register 8. 0.81 and 82, the Q register used in conjunction with multiplication and division (as shown) ), the processing unit 30, memory 11 or required data is stored in the cache. In some cases, from various registers within Karsh 35, as well as in the field of The data may be provided from other sources within the cough data processing system as is well known in the art.

The arithmetic logic unit 83 inputs the data to be processed to two input terminals, namely A IN A from the control microword is received through the input terminal and the B IN input terminal. Process the data according to the LU CTRL control signal and send the processed data to W OUT Send through the light output terminal. All input data sources are wired OR configuration and is connected to the A IN and B IN input terminals. Control circuit 40 (Fig. 1) These control microwords should actually be sent to the A IN and BIN input terminals. Determine the source of the processed data and the storage location where the processed pigs will be stored. That is, one In the example, the source of the data to the A IN input terminal is the set 80.81 and 8 2 and selected miscellaneous registers in the processing unit; Contains memory 11 or Kersh 35, while outputting data to B IN input terminal. The location is set 82 registers and selected other miscellaneous processing unit registers. Processed data containing only data that might otherwise be the source of the data You can write anywhere you want.

Therefore, the general purpose register 80 has two sets of control signals, namely one set A EN GPR'' A' enable general register control signal and -U's W EN GPR write input Receives cable general-purpose register control signals. A IN of arithmetic logic unit 83 If the input should receive the contents of a general-purpose register, A that allows the content to be sent to the A IN input terminal of the arithmetic logic unit 83 EN Corresponding one of the GPR'A' enable general-purpose register control signals is claimed. Similarly, the output of arithmetic logic unit 83 is one of general purpose registers 80. one WEN corresponding to that general-purpose register. The GPR write enable general register control signal is asserted.

The temporary sister set 81 and the working register set 82 receive similar control signals. Ru. That is, the set of temporary registers 81 is such that the contents of the selected temporary register are arithmetic. A set of A EN TEMP A.

Receive an enable temporary control signal. Also, - EN TE of group -? IP light The enable temporary control signal is processed from the WOυT output terminal of arithmetic logic unit 83. The financial data is stored in the selected temporary sister in the temporary sister &u8]. make it possible to

The set of work registers 82 is such that the contents of the selected work register are A IN and B. A set of A EN to enable each to be transferred to the IN input terminal WR “A” and A EN WR “B” enable work register control signal received do. A set of working registers 82 also includes processed data from arithmetic logic unit 83. A set of W to enable data to be stored in the selected working register. EN Receive the WR write enable work register control signal. arithmetic logic unit A IN and B IN input terminals of the unit 83 and for storing processed data. Similar control signals (not shown) may be issued for other sources of data to possible storage locations. be born.

Figure 3B shows the various register control signals shown in Figure 3A and other controls not shown. FIG. 2 is a logic diagram of a circuit that generates a control signal. Initially, the control microword The source of the signal transferred to the A IN and B IN input terminals of the logic unit 83 is Define the signal to control and the signal to control the destination of the signal from the WOUT output terminal It contains three fields. That is, the control signal microword is A5 EL (51) "A" selection control signal and B 5EL (3: 0) "B' selection system control signal, and the DEST (1:0) destination (i.e. write) selection control signal. Contains fields that define

When the control circuit 40 (Fig. 1) starts processing a new command, the control circuit 40 (FIG. 1) N when asserting the command signal and starting decoding each operand specifier. XT Assert SPC Next Specifier signal. See Figure 3B In response to the NEW lN5T new command signal from the control circuit 40, the counter 85 is initialized. Each time the operand specifier is decoded, the control circuit NXT Asserts the SPC next subversifier signal and to enable automatic operation. Counter 85 indicates the operand specifier being decoded. Generates a binary signal SN subspecifier number identifying the ear.

In response to the SN specifier signal, two decoders 86 and 87 detect it. Output signals WX, EN, WSN (X is the order in which the signals are generated from the counter 85) 0, 2.4.7.3.1) and WX EN WSN+1 (X is 1.3. 5.0.4.2). −Finally, the operand is digital data. A digital data processing system is used before an arithmetic or logical operation is performed on the processing system. WX EN WSN and The WX EN WSN+1 signal indicates that the operands are loaded into their respective working registers. related to the order in which they are coded. However, more space than one working register can provide. If a data item requires a source, some of it is The rest is loaded into the work register specified by WXEN WSN+1. is loaded into the specified working register.

For example, when executing a directive consisting of If so, the first operand is transferred to register 0 of working register 82; The second operand is transferred to register 2, and the third operand is transferred to register 4. etc., in the order specified by decoder 86. In the example, up to six operands are used for command execution. If each operand is two , the first operand is determined by decoder 86. Transferred to register 0 determined by decoder 87 and register 1 determined by decoder 87. be done.

The decoder 90 receives the A SEL (5:00) “A” selection control signal and Several A EN XX Enable + J 7 G signals (XX Is it GP RO-14, TE? IPO-TEMP15, WO-W7, WSN, W SN+1, and 0THER, where “0THER” is the Q register mentioned above. related to other selected registers in processing unit 30, including registers). let Similarly, the decoder 91 receives the B5EL(3:O) "B" selection control signal. and several BENXX enabling signals depending on the coding of the control signal. No. (XX refers to -WO-W?, WSN, WSN+1, and 0THER, where 0THER is related to the selected other register in the processing unit 30). generated on each output signal line.

A　EN　WSN enabling signal is the WX　EN　WS from the decoder 90 A set of gate drivers that gates the N enable write basis number signal. A EN WX signal from the decoder 90 ( X is 0.2.4.7.3 and 1) are relayed to the respective signal lines carrying Thus, if A 5EL (5:00) responds to the “A” selection signal Then, the decoder 90 inputs the AEN WSNSN enable register specifier. If the driver 100 asserts the number signal then the driver 100 asserts the energizes the signal line carrying the WXENWSN signal. gate driver -101 is controlled by the AEN WSN+1 signal and is emitted by the decoder 87. Do the same thing for the generated WX EN WSN+1 signal, and also ・Drivers 102 and 103 are BEN WSN and BEN WSN+1 Controlled by Enabling and associated with BENWO-BENW7 Do the same for the XEN WSN and WX EN WSN+1 signals.

In addition, the output signals from decoders 90 and 91 and drivers 10-103 are relayed to channels 92 and 93. Latches 92 and 93 are ALTHHOLD and B When the LTHHOL and D5yf hold signals are negated, the state of the input signal is A　LTHHOLD and B　LTH[l0LD] launches the state of each signal line when the hold signal is asserted . Control circuit 40'4, the signals on each signal line are colored WENXX When stable for use in generating a write enabling signal A LTHHOLD and B Since the LTHHOLD latch hold signal is asserted, the control The control circuit can generate and use new control microinstructions. Otherwise, the outputs of decoders 90 and 91 would be changed to change the signal.

The signals launched into latches 92 and 93 are at the multiplexer 1040 input terminals. It will be relayed to each group. Additionally, the multiplexer 104 receives a signal from the decoder 86. WX EN A third set of input terminals that receives the WSN signal and a level that is negated. a fourth set of input terminals for receiving a signal, and a fourth set of input terminals for receiving a control signal; A DEST (1: O) destination signal is received from the circuit 40 and the DEST (1: O) destination signal is received. 0) The destination signal comes from the control microinstruction. two dests (1:0) Destination signal is one set of four input signals to be relayed to the output Select the required W ENXX (XX is GPR, TEMP, WR, and 0TH ER) provides a write enabling signal. Therefore, the two DEST( 1: O) A write enabling signal is selected depending on the destination signal, but this , much more than would otherwise be required to select multiple destinations for processed data. There are fewer signals.

As mentioned above, the operations performed by the arithmetic logic unit 83 (FIG. 3A) Controlled by the ALU CTRL signal from the Ul#Jfi1 circuit 84, the circuit 8 4 is an ALU OP SE from the control circuit 40 (FIG. 1B) of the arithmetic processing unit 30. Controlled by the L operation selection signal. Referring to Figure 3C, the ALUfi control circuit 84 responds to the ALUOP SEL calculation selection signal and selects 7A LU CT I?　 L　COD　E Is it a programmable logic array circuit that generates a control code signal? In addition, the decoder 86 includes a decoder 85 consisting of an ALUOP SEL operation selection Upon receiving the selection signal, the MU Generates an L multiplication signal or a DIV division signal.

By way of background, the arithmetic logic circuit 83 does not directly perform multiplication or division; In a special embodiment, a known sequential addition shift is used when specified by a program instruction. This embodiment performs multiplication by implementing a multiplication algorithm. When more specific, known sequential shift-subtraction/addition/non-recovery division algorithms Division is performed by implementing the ism.

In the multiplication algorithm, the control circuit 40 causes the arithmetic logic unit 83 to add or pass operation (in pass operation, the data of the single power terminal of the arithmetic logic unit A series of AUL OPs that allows the signal to be sent to the output terminal) Generates an EL operation selection signal and stores the result in the Q register (not shown) mentioned above. will be paid. In this division algorithm, the ALtl OP SEL operation selection signal The code allows the arithmetic logic unit 83 to perform addition or subtraction, and the result is also stored in the Q register.

Which operation is to be done, i.e. an addition or pass operation for a multiplication program command. whether addition or subtraction should be performed for a division program command; That is, based on some of the results of previous operations in the series.

ALU by the control circuit 40 (FIG. 1B) until after the result of the previous operation is determined. OP Lutameni and ALUIIJ control to prevent delay in generation of SEL operation selection signal Path 84 indicates that the ALtJ OP SEL operation selection signal specifies MUL or DIV operation. If so, the ALU generates at least some of the CTRL control signals. Contains circuits. Decoder 85 generates some of these signals. and transmit them as ALU CTRL CODE111m code signals, The signal is relayed to the output of multiplexer 88, whose output signal is sent to an arithmetic logic unit. Configures the Attl CTRL control signal that controls the cut 83.

The second manual of multiplexer 88 is PRESET CTRLCODE preset system Receive control code signal. Regarding the previous paragraph, both multiplication and division are addition steps. PRESETCTRL C0DE precent control code signal is added. Identify operations. If the ALU OP SEL signal specifies the MUL operation , ALU CTRL C0DE code signal specifies the passing function of the arithmetic logic unit. do. On the other hand, if the ALU OP SEL operation selection signal does not specify DIV division, If so, the ALU CTRLCODE @ control code signal specifies the subtraction.

The second decoder 86 also selects ALUOP SEL operation from the control circuit 40 (Figure 1B). receiving signals and asserting the MUL multiplication signal when they identify a MUL multiplication; They assert the DIV unsummer signal to specify DIV division. MUL multiplication and DIV divide signal control multiplexer control circuit 87, which circuit 87 As is known in the art, one of the preceding results determines the operation to be performed. RESULTS signals representing the portion are received from other circuits. RESULTS in response to the MUL multiply and DIV divide signals from decoder 86. The multiplexer control circuit 87 controls the multiplexer 88. Generates a plexer selection signal.

Specifically, if decoder 86 generates the MtJL multiplication signal and the RESU If the LTS signal indicates that an addition should be performed, the multiplexer control The circuit 87 generates the MUX SEL multiplexer selection signal, which is PRESETCTRL C0DE recent control code signal to arithmetic logic unit 83 to enable the unit to perform the addition.

Similarly, if decoder 86 generates the DIV divide signal and the RESULTS signal indicates that addition should be performed, then PRESET CTRL C0 The DE preset control code signal is relayed to the arithmetic logic unit 83 so that the unit Generates a MUX SEL multiplexer selection signal that allows the addition to be performed I am made to do so.

On the other hand, (1) the decoder 86 generates the MUL multiplication signal and the RESULTS signal; indicates that a pass operation should be performed, or (2) decoder 86 indicates that DIV generates a divide signal and the 1iEstlLTs signal indicates that a subtraction should be performed. If the MUX SEL multiplexer selection signal is The ALtJ CTRL C0DE signal from the coder 85 is sent to the arithmetic logic unit 83. The ALU that controls the ALU can be relayed to its output as a CTRL signal.

Even when decoder 86 generates neither the MUL multiply signal nor the DIV divide signal, the MUL The SEL multiplexer selection signal is sent by the multiplexer 88 from the decoder 85. ALU ALU for controlling the CTRLCODE signal to the arithmetic logic unit 83 CTRLl#J? ll signal to its output.

The circuit shown in the third CII includes a decoder 86, a multiplexer 88 and a multiplexer 88. By appropriate selection of the multiplexer control circuit 87, the result of the previous operation can be fully or partially It can also be used in conjunction with other arithmetic and logic unit operations that depend on It will be understood that the control circuit 40 controls the ALU OP SE for the next operation. It is necessary to wait until the result of the operation is determined before generating the L operation selection signal. The circuit facilitates reducing the time between arithmetic and logic operations. be.

Matching verification circuit for translation Buffer 260 of memory circuit 37 In a system that includes a CPUIO (Figure 1), each program uses memory space. The virtual memory configuration is used assuming that the entire memory space is allocated, but It may be larger than the physical memory space provided by memory 11.

If the processing unit 30 does not access a specific location within the virtual memory space, When the virtual memory space is not available, the required portion of the virtual memory space is allocated to the physical memory -11 or shifted out of the physical memory. Virtual memory space not located within 11 is stored on a mass storage device (typically a disk storage unit). knit).

A part of the arithmetic processing unit 30, that is, the memory management circuit 37 is stored in the memory 11. The entries on the translation page table (not shown) that are displayed are used to create a “virtual address in the virtual memory space, called "address", and the physical memory 11 Performs translation between physical addresses within. Systems with virtual memory Since the procedure for translation from a virtual address to a physical address in is well known, , will not be explained here.

Memory management circuits are used to speed up translation from virtual addresses to physical addresses. Path 37 lists a selected number of recently used page table entries in connection with the translation. The circuitry of translation buffer 260, including translation buffer 260 that stores 4A, and a more detailed logic diagram of translation buffer 260 is shown in FIG. It is shown in Figure B-1 and Figure 4B-2.

Referring to FIG. 4A, translation buffer 260 stores the high-order portion of the virtual address. a content-addressable memory 110 having a plurality of items to store and a hint buffer 1; 11 and a page frame number storage circuit 112. virtual address high A portion identifies a “page” in virtual memory space, where a page is a predetermined number of It has consecutive storage locations. The page frame number storage circuit is a content addressable memory. It contains the same number of items as Molly. Each item in the page frame number circuit is Associated with an item in addressable memory; the content is a temporary in addressable memory. High-level part of the physical address or page frame that corresponds to the high-level part of the virtual address Store numbers. In one embodiment, the content addressable memory and page frame The program number storage circuits together contain 28 entries.

Translation buffer 260 also includes protection logic circuit 113, which also has 28 terms. each of which is associated with one item of content-addressable memory.

Each item in the protection logic circuit has a corresponding item in the addressable memory 110. The program's access rights to the contents of the storage location specified by the contents of the Stores the decrypted protection code representing.

The translation buffer 260 also contains four sets of flags: set 114, rTB, V translation buffer 260 valid flag &1l 15, rPTE, V page table item validity flag' set 116, and rPTE , M page table item modification flag" set 117. Contents addressable Each item in function memory 110 is the rNUL last unused flag in set 114. One of the groups, group 115, rTB, V translation buffer 260 valid flag, Notes, group 116(7) rPTE, Vbe'; one of the table item validity flags, and set 1 17 rPTE, M page table item modification flag. r NUL last unused flag' set 114 and rTB, V translation buffer 2 &11115 of “60 Validity Flag” is used to control the operation of the translation buffer. It will be done. In particular, NLU flag set 114 indicates that the new page table entry is in memory. 11. used.

The flag of 260 items of translational buff that was not used immediately is sent, and it is updated. You can replace it with a new item. rTB, V translation buffer 260 validity flag' is , content addressable memory 110 and page frame number circuit 112. indicates that the items are valid, that is, they can be used.

The remaining flags form part of the page table entries retrieved from memory 11. "rPTE, V page table item validity flag" 116 indicates the corresponding page rPTE, M page table entry indicating whether the table entry is valid and usable The "Eye modification flag" 117 indicates whether the corresponding page has been modified; If a page has a location in physical memory 11 other than another page in the virtual address space Each is stored on disk or tape if not modified when used for Not done.

The processing unit 30 (Figure 1) accesses memory using a specific virtual address. When accessing, first - translation buffer 260 corresponds to the high part of the virtual address. It is determined whether there is an item in the content addressable memory 110. A The VA 5RCE virtual address source signal represents the high-order portion of the virtual address. , the signal is sent to content addressable memory 110. content addressable The items consisting of the memory 110 correspond to the VA 5RCE virtual address source signal, and rTB, the associated flag in the set 115 of "V translation buffer 260 validity flags" is set, indicating that the item is valid, the PE THIT (27:O) The corresponding one of the page table item hint signals is It is claimed in 113. Hit buffer 111 is PTE HIT (27:0) Buffer page table item hit signals and make them responsive to internal timing signals to adjust the time. If PTE HIT (27:O) Page table item hint signal If one of the is asserted at the appropriate time, the corresponding HIT 5EL (27:0) hint A selection signal is asserted. HIT SEL (27:0) One of the hint selection signals The selected one is a pair of 28 items in the page frame number storage circuit 112. the corresponding one is transferred to internal bus 34.

Translation buffer 260 also includes protection logic circuit 113, which includes two It includes 8 items, each of which corresponds to the corresponding item of the page frame number storage circuit 112. Grants a program access to the contents of a page specified by the number of page frames. The represented focus is stored in decoded form. Each page table item is In addition to the number of page frames stored in the frame number circuit 112, accessing the page for a read or write operation Contains a protection field that specifies the lowest possible operating protection level mode. De Coder 120 receives the protected field and decodes the protected field bits. generated, the bit is the content addressable memory 110 and the number of page frames. The corresponding entries in circuit 112 are loaded into translation buffer 260 shown in FIG. 4A. stored in the protection logic circuit when

Specifically, one embodiment includes (in order of decreasing privilege) core (K), administrative (E), Four operational protection level modes are provided, referred to as Visual (S) and User (U).

Read or write when the processing unit 30 is operating in the operating privilege level mode. If you can access a page that requires a lot of movement, the calculation processing bag M30 will have a higher movement rate. for the same read or write operation when operating in privileged level mode. can be accessed. In that embodiment, the information to be stored in protection logic circuit 113 is and the encoded protection value of the page table entry and the encoded protection value generated by the decoder circuit 120. The corresponding decoded bit values are as follows. :oooo ooo o　oooo.

0010 RW---100010000011R---10000000 0100RW R-4 RW 1111 11110101 RW RW -- 110011000110RW R--110010000111RR--11 000000 1000R RW RW -111011101001RW RW R-11 1011001010RWRR-11101000 1011RRR-11100000 1100RW RW RW R1111111011014 RW RR111 111001110RW RRR11111000 (〇-denial, 1-assertion, R- Read access, W vote write access “-” - neither read nor write access) The composite value is an 8-pin The four points on the left indicate the number of page frames involved. An operational privilege level mode that allows reading from more specific locations. The bit on the right is written in the location specified by the associated page frame number. It is understood that this represents a privileged level mode of operation in which the Within each group of 4 bits, the bits indicate one of the operating privilege level modes. is associated with. Specifically, within each group of 4 bits, each bit From left to right, the tables are associated with operating privilege level modes of decreasing privilege. There is.

The translation buffer 260 shown in FIG. 4A converts virtual addresses into physical addresses. When used to translate or translate, the VASRCE virtual address source signal At the same time as sending the contents of CUR to the addressable memory, other decoders 121 MODE current privilege level mode signal, asserts RD read if operation is a read operation. or, if the operation is a write operation, an asserted WRT write signal. Ru. The CURMODE current mode signal indicates the current mode in which the processing unit 30 is operating. Identify protection level operating mode.

Accordingly, the decoder 121 selects the current operating protection level mode and (7:0) protection. One of the code signals is asserted on the corresponding signal line 122. That is, as follows In addition, each of the four high-level signals of the PCODE (7:O) protection code signal is readable. There are four operating protection level modes associated with extrusion operation, and four lower The signal is associated with one of four operational protection level modes in connection with a write operation. Ru.

Operation mode Operation P C0DE (7: O) Signal product READ 1000 　0000 WRITE 0000 1000 Management READ 0100 0000 WRITE 0000 0100 Monitoring READ , , , 0010 0000 WRITE 0000 0010 User READ 0001 0000WRITE 0000 0001 (0=denial, 1-assertion) The protection logic circuit compares the PC0DE (7: O) signal with the contents of the protection logic 113. do. If the asserted P C0DE (7: O) protection code signal is At least one set of pins in the decrypted protected field stored in the 1130 item ACCESS (27: O) One of the access signals corresponds to the corresponding It is claimed on one of the lines 123 associated with the item. On the other hand, if the claimed P C0DE (7: O) Protection code signal of decoded protection field in one item ACCESS (27: O) Access signals are also not asserted.

ACCESS (27: O) The access signal is the corresponding HITSEL (27 : 0) N is ANDed with the hint selection signal.

5 TALL (27: O) signals, each of which is a translation buffer term. Associated with one of the eyes. The arithmetic processing unit 30 is N.

Using the 5TALL (27:O) signal, the translation buffer 260 selects the required page. It is determined whether or not the number of frames is included, and if it is included, the corresponding calculation process is performed. A page consisting of memory 11 can be read in a privileged level mode of operation where the It is determined whether or not a write or write operation is to be performed. Waka NO5T If at least one of the ALL(27:O) signals is asserted, the translational pant processor 30 has the required operating privilege level mode.

Figures 4B-1 and 4B-2 illustrate various aspects of translation buffer 260 shown in Figure 4A. 1 is a detailed logic diagram of a single item portion of a circuit. To be more specific, the content address The memory 110, page frame number circuit 112, and protection logic 113 are contain an identical number of logical storage cells, each with an associated high-level virtual address, image frame number and the focus of one of the decoded protection fields. the cell are identical, so we remove only one cell from each of circuits 110, 112 and 113. It is shown in FIG. 4B-1 and FIG. 4B-2.

Referring to FIG. 4B-1, content addressable memory 110 includes a processing unit VA 5RCE high level virtual address source from circuit 251 (Figure 1B) in 30 Connected to line 132 which receives one of the signals, namely the VA 5RCE (Y) signal. The 0 circuit 251 including the CAM cell 131 is VA 5RCE except for the following points. (Y) signal and almost complementary VA 5RCE (Y) COMP signal to line 13 Provided on 2A. Other CAM cells in the item containing CAM cell 131 are other VAs. 5RCE signals are received in parallel, and all iVA 5RCE signals are content address The entire high-order portion of the virtual address sent to memory 110 (Figure 4A) Configure. All items in content addressable memory 110 are stored in VA 5RCE virtual address. Receive address source signals at the same time.

The VA5RCE virtual address source signal serves one of two purposes: That is, to write to an item in the translation buffer, each address translation is translated can be directed to the content addressable memory 110 to obtain the . translation bar While writing to the buffer item, other circuits in the arithmetic processing unit 30 are virtualized. Transmit the high-order focus of the address as a VA 5RCE virtual address source signal, TBE WRT translational buff associated with 206 translational buff items to be written Assert the 260 item write signal. In response, the passing transistor of cell 131 Registers 133 and 133A are turned on and the signals on lines 132 and 132A are turned on. The signal is relayed to a flimp flop consisting of inverters 134 and 135. young If address focus on line 132 is asserted (and that If the complement bit is negated), the output of inverter 134 is low and the inverter The output of 135 is high level. If the address bits on line 132 are negated If so, the output of inverter 134 is high level, and the output of inverter 135 is It is at a low level.

The page frame number circuit also includes an entry number each containing a cell number; One cell 140 is depicted in Figure 4B-1.

TBE WRT conversion buffer 260 write signal is the conversion buffer 260 entry indicates a write operation to the memory, and if an input is received, the pass transistor 142 is turned on. , PFN (Z) pagef on line 143 from other circuits within processor 30. The frame number (Z) signal is a flip-flop consisting of inverters 144 and 145. supplied to Inverters 144 and 145 according to the state of the PFN (Z) signal The signal state from is similar to the signal state from inverters 134 and 135.

PFN (Z) Page frame number (Z) signal is the entry containing cell 141 This is the page frame number of 1 pinto stored in the page frame number.

Similarly, the protection logic includes multiple entries, each containing multiple cells; Inner cell 151 is depicted in Figure 4B-2. TBEWRT conversion banfa 260 books When the input signal is input, the pass transistor 152 is turned on and the decoder circuit 12 The PROTDEC(W) decoding protection code signal from 0 is sent to inverters 154 and 15. It is supplied to a flip-flop consisting of 5. PROT DEC (W) decoding protection signal The status of inverters 154 and 155 according to the status of the inverter 134 and The signal status from 135 is similar.

PTE, V and PTE, M page table entry valid and qualification flags 116 and 117 are frames containing cells 161 and 171, respectively, of similar structure. The gate 116 includes a pass transistor 162, which has an input TBE WRT When turned on by the conversion conversion buffer 260 entry write signal, the processor 30 PTE, V WRT page table entry variant writing from other circuits within In order to store the read signal in a flip-flop consisting of inverters 164 and 165, supply to Flag 117 also includes a pass transistor 172, which Turned on by input TBE WRT conversion conversion buffer entry write signal When, PTE, M WRT page table entry modification write signal inverter A flip-flop consisting of 164 and 165 is supplied for storage.

NLU flag 114 (Figure 4A) is not involved in the conversion operation and is Not depicted in Figure 4B-2. TB, V conversion buffer 260 valid flag is , PTE, similar structure to V page table entry flag, and related and will not be discussed further.

As mentioned above, the circuits depicted in Figures 4B-1 and 4B-2 also address virtual addresses. Used in connection with translation to physical addresses.

In the following, the higher order part of the virtual address includes cell 131 (Figure 4B-1) The corresponding page frame number is stored in the entry containing cell 141. The corresponding decoding protection field bits from decoder 151 are 151, and the corresponding PTE, V page table entry Flags are adjusted to indicate that the page table entry is valid It is said that

Referring to Figure 4B-1, just before conversion, the precharge voltage is applied to line 14. 3. Line 18 for transmitting PTE HIT(X) page table entry signal 1 and ACCESS (X) transmits an access signal (line 123 in Figure 4A) 183 (included in the conversion buffer) and both lines are concatenated in the translation buffer. .

During the precharge time, V from the virtual address source circuit 251 (FIG. 1B) Both the A 5RCE (Y) signal and the VA 5RCE (Y) COMP signal are (in low voltage conditions) to turn off transistors 136 and 138. , permit execution of precharge operation. The low voltage is also connected to the entry. HI-SEL (X) supplied to line 182 that transmits the hit-select signal. It will be done. Line 181 indicates all cells within one entry of content addressable memory 110. 131 and line 182 is connected to page frame number circuit 112. Connected to all cells 141 in the entry, line 183 connects to protection logic circuit B It is connected to all cells 151 in 113 connected entries.

After the line is precharged, other circuits within processor 30 JJj, transmits the virtual address source signal to the content addressable memory 110 (FIG. 4A). Ru. Cell 131 is connected to the signal state on line 132 and to inverters 134 and 135. It consists of transistors 136 to 139 that compare the state with the entry written. includes a comparator that indicates the signal state on line 132 that was already latched when . That is, the launch is performed by a flip-flop consisting of inverters 134 and 135. VA 5RCE (Y) The virtual address source signal was already input. If so, the output of inverter 134 becomes low and the output of inverter 135 becomes high. Become. Therefore, inverter 134 turns off transistor 139 and impaks 135 turns on transistor 137. VA 5RCE (Y) signal is currently input If so, transistor 138 turns on and inverter 140 turns on transistor 138. 136 is turned off. Since transistors 136 and 139 are turned off, the There is no current path between IN 181 and ground, so the line is precharged. The voltage level remains the same.

Similarly, a flip-flop consisting of inverters 134 and 135 is used to launch the VA 5RCE (Y) Virtual address source signal was already canceled If so, the output of inverter 134 will be high and the output of inverter 135 will be low. becomes. Therefore, inverter 134 turns on transistor 139 and inverts The transistor 135 turns off the transistor 137. VA 5RCE (Y) signal during conversion is currently canceled, transistor 138 is off and impark 140 is Turn on transistor 136. Transistors 137 and 138 are turned off. Therefore, there is no current path between line 181 and ground. In this state, line 1 81 also remains at the precharge voltage level.

V launched by a flip-flop consisting of inverters 134 and 135 A 5RCE (Y) If the virtual address source signal has already been input, the Transistor 139 is turned off and transistor 137 is turned on. During conversion, V If the A5RCE (Y) signal is currently canceled, transistor 138 is turned off and transistor 136 is turned on. This allows the current path to between line 181 and ground through resistors 136 and 137, so that the line The voltage on in 181 is reduced to ground voltage level. If V was lunched before A 5RCE (Y) Virtual address source signal is canceled and input during conversion , the current path is through transistors 138 and 139 to line 181. and ground, so the voltage on line 181 also drops to the ground voltage level. reduced.

Therefore, if the state of the VA 5CRE (Y) virtual address source signal during conversion is If it is the same as when writing the entry, cell 131 connects line 181. Isolated from the ground voltage level and maintained at a precharge voltage level, i.e. cell 131 If the two states are the same in Allow tree hint signals to be input. On the other hand, if the two states are different, the line 181 is pulled down to a low voltage level. That is, PTE HIT (X) cable entry hint signal is canceled. Entries in associative memory 110 If all cells 131 in - are connected to line 181, the input P TEHIT(X) For page table entry hit signals, the state is All in all a must for lunch.

When the PTE HIT (X) signal is input, the transistor in the hint buffer 111 Star 184 is turned on. When the PH2 phase 2 clock signal is input next , transistor 185 is also turned on, effectively bringing line 183 to the positive voltage supply V44. Connected. The input HIT SEL (X) hint select signal is The transistor 186 in the cell 141 in the frame number circuit 112 is turned on and the A buffer transition indicating the bit state of the page frame number stored in the page frame number 141. The output of star 187 is provided on line 143. The output is increased by amplifier 190. The signal is then supplied to one line of the bus 34.

The output of buffer transistor 187 is the page frame stored in cell 141. Indicates the bit state of the number, i.e., if the bit is canceled, the inverter 144 Turn on transistor 187.

HIT 5EL(X) Transistor 187 with hit select signal turned on , the current path is from line 143 to transistors 186 and 187. is formed on the ground side through the PFN (Y) page frame number (focus y) signal. shall be invalidated. On the other hand, when a previously stored bit is input, inverter 144 turns off transistor 187, so that even if transistor 186 turns on, Also, precharge line 143 is maintained at a high voltage level and the PFN(Y) signal is is input.

Temporarily, for transmission of VA 5RCE virtual address source signal to content addressable memory. Accordingly, the decoder 121 converts the PCODE (7:0) protection code signal into a protection code signal. Transmit to Jic 113. As mentioned above, in one embodiment P C0DE (7: O) One of the protection code signals is input and the processor and Determines the current protection level mode for (write or read) processing. Other PCODE ( 7: O) Protection code signal is ignored.

Referring to FIG. 4B-2, cell 151 within protection logic 113 transmits data from a cell. Transistor 1 controlled by P C0DE (Z) protection code signal 56, and a flip-flop consisting of inverters 154 and 155. Two transistors 156 and 157, including transistor 157, ACCESS (X) line 183 that transmits access signals connected to the entry connected in series between.

The state of transistor 157, i.e. whether it is on or off, depends on the This output is also the P value when the entry was last written. It depends on the state of ROT DEC(W) protection decoding signal. That is, PROT DE When the C(W) protection decoded signal is input, the output signal from the inverter 154 is transistor 157 is turned off. On the other hand, PROT DEC (W) protection When the decoded signal is canceled, the output signal from the inverter 154 is input, and the output signal from the inverter 154 is input. register 157 is turned on.

Similarly, the state of transistor 156 is the state of the PCODE (Z) protection code signal. respond to the situation. P　C0DE　(Z) When the protection code signal is input, the transistor transistor 156 is turned on, whereas when that signal is canceled, transistor 156 is turned on. To do so.

Transistors 156 and 157 control the state of line 183, thereby Controls the input and canceled state of the transmitted ACCESS (X) signal.

If both transistors 156 and 183 are present between and ground, then ACCE SS (X) signal is canceled. On the other hand, one of the transistors 156 or 157 is turned off, a current path exists between line 183 and ground through cell 151. Doesn't exist. If the current path through other cells in the entry in protection logic 113 is If not present, the ACCESS (X) signal is input.

Cell 151 is basically a flip-flop consisting of inverters 154 and 155. PROT DEC(W) decryption protection previously latched and previously written by P C0DE (Z ) signals, in particular the PCODE (Z) signal from the decoder 121. is input and the previously latched PROT DEC(W) from decoder 120 Cell 151 sends the ACCESS (X) signal only if the decryption protection signal is ignored. , thereby indicating that processor 30 is not operating at a sufficiently high privilege level. to show that

HIT 5EL (X) hint select signal and ACCESS (X) signal are AN Supplied to D gate 190. If HIT 5EL(X) hint select signal and If both the ACCESS and ACCESS (X) signals are input, the AND gate 190 converts Generates a No. 5 TALL (X) signal for the buffer 260 and sends the processor 30 The TB of the entry in cent 115, V conversion buffer 260 variable PTE in G and St. 116, V page table entry valid flag is adjusted as shown below.

On the other hand, if the No. 5 TALL signal is not input, other circuits within the processor 30 Perform accurate operation, especially when the HIT 5EL (X) hint select signal is input. Otherwise, other circuits obtain page table entries from memory 11 (Figure 1). , perform the conversion.

Temporarily, the page table entries obtained from memory 11 are stored at the end of the NLU. The unused flag 114 is used to written to the entry.

On the other hand, when the ACCESS (X) signal is canceled, the inverter 191 The signal is applied to one input of AND gate 192. Corresponding HIT 5EL ( X) When a hint select signal is input indicating a match in the content addressable memory 110. , AND gate 192 operates to input the ACCVIOL (X) access violation signal. The processor 30 then executes the requesting operator to perform the requested access operation. protection level mode.

The processor can perform conventional recovery actions in response to an access violation. .

As described, when the No. 5 TALL (X> signal is input, the processor 3 0 also indicates TB, V translation buffer 260 valid flag 115 and PTE, V The state of page table entry valid flag 116 (Figure 4A) is also used. Ru. Since the flap structure is similar, PTE, V page table entry Only the valid flag 116 will be described in detail. Referring to Figure 4B-2 , if the page table entry in translation buffer 260 is valid, the translation When buffer 260 entries are written, PTE V WRT page table An entry variable write signal is input, which causes inverters 164 and A flip-flop consisting of 165 cents, then PTE, V page table Set entry valid flag. In that state, the inverter 16 The input of 4 is at a high voltage level and its output is at a low voltage level.

In this state, inverter 166 keeps transistor 167 in regulation. . Input HIT 5EL (X) HIT linked with conversion panfoot 260 entry The client select signal is connected in series with transistor 167 between line 169 and ground. The other connected transistor 168 is turned on. As a result, in cell 161 When both transistors 167 and 168 are turned on, the ground level signal is on the line 169. Inverter 170 transfers the signal to high input PTE Supplements the T page table entry valid output signal.

Line 169 represents all entries in translation buffer 260 (Figure 4A). Commonly connected to transistors corresponding to transistors 168 in all cells 161 It will be done. This causes the HIT 5EL(X) signal to enter the conversion buffer 260. The PTE and V flags are input to some of the converter buffers 260. When both transistors 167 and 168 are turned on, the ground A level signal is input on line 169.

On the other hand, the PTE and V page table entry valid flags are clear. i.e. the previously written PTE V WRT page table entry valid If the write signal is ignored, transistor 167 is turned off, thereby pin 169 is isolated from ground. Line 169 is pre-charged prior to the conversion operation. When the PTE V OUT page table entry from inverter 170 is The Lee output signal is canceled.

PTE, M page table entry modification flag 117 indicates PTE, V page It is configured in the same way as the table entry valid flag 116, and its operation is also the same. It is. However, the PTE, M flag is set when a page in memory 11 is written. PTE M WRT page table entry modification write signal input only to adjusted accordingly. Cell 171 (Figure 4B-2) is PTE.

An example of one of the M page table entry flags 117 is shown.

The page frame number is transmitted by circuit 112 (FIG. 4A) and No. 5TA After the LL signal is generated, the processor connects transistor 185 (Figure 4B-1) to ) is turned off, the PH4H4 clock is input, and the transistor 193 is turned on. 2 Deny the clock signal. Transistor 193 connects the ground level signal to line 18. 2 to negate the input HIT5EL(X) signal.

The processor then negates the PH4 clock signal and converts buffer 260 (fourth In Figure A), other virtual addresses can be input.

Selection and selection of page frame numbers needed to convert virtual addresses to physical addresses Simultaneously with transmission, a new translation buffer 260 is created by the processor for access. Enables determination of whether operating at sufficient operating privilege level mode shall be. Previously known translation buffers do not contain the encoded content of protected fields. The content is transmitted from the translation buffer along with the page frame number, at which time the Does the processor have the necessary operating privilege level mode to operate? The decision was made. Operating System Required for Processor Access This can compromise processor access unless it is running in privileged level mode. cognition was delayed.

cache logic As mentioned above, the processor 30 stores at least the most recently input data into the memory 11. including cache memory 35 (FIG. 1B) for storing copies of several data; The data at that time is stored in the memory 35 of the memory 11 as a copy of the data at that address location. Determine whether to include peas. Figure 5 includes data for which cache has been determined. Under the control of the bus interface unit 33, the device A circuit within the cache memory 35 that transmits data to the internal IDAL bus 34. The functional block diagram is shown below.

Referring to FIG. tag sets 42A, 42B, tag sets 41A, 41B and data storage area 38A , 2 data storage cells each containing 64 entries divided into 38B) 3 Includes 9A and 39B. Tangsen) 41A and 41B entries are also Parity focus to check the integrity of tag information stored in each tag set including. Each entry in data storage areas 38A and 38B is 2 words or 8 It stores bit data, the -word is a high-order word, and the other words are low-order words. Consists of C.

Cache memory 35 is configured as a two-way set associative cache, where The low order portion of the address corresponds to the 64 entries in each of data storage sets 39A and 39B. data storage cells in cache 35) 39A and 39 When one entry in B is written with data from memory 11, the physical The lower part of the target address identifies the entry in the data storage center where the data will be written. The high-order part of the physical address, along with the parity focus, is set to tag set 4. 1A or 41B.

In register 300 in source register 257 (Figure 1B), the virtual address In the described embodiment, the bins that form the higher order part (31:9) and the lower order part It consists of 32 bits with (8:O). The higher order part is VA 5RC E (31:9) Generates page frame number as virtual address source signal and transmits it to the page frame number register 302 in the cache memory 35. is transmitted to the conversion logic 301 that performs the conversion. The logic 301 is shown in FIG. 4A, 48- IE and the translation buffer 260 described above in connection with FIG. 4B-2; is also used by other traditional methods that generate page frame numbers from higher-order parts of virtual addresses. It consists of Kanism. Bits (8:O) of the virtual address do not change during address translation. It doesn't change.

The focus of the lower part of the virtual address (8: 3) is VM 5IICE (8: 3) ) 39A as a virtual address source signal from the register 300 to the data storage cell. and transmitted to 39B. VA 5RCE (8: 3) Virtual address source signal establishes one of the 64 entries in both data storage sets. V A 5RCE (8:3) Confirmed error in response to virtual address source signal input The contents of the entry are transmitted from each data storage cent.

That is, the contents of the selected entry in data storage center A are VALIDS As the ET A and TAG+PARITY SET A signals, the comparator 30 3. The high word of the committed entry is mapped as a HIGHA signal. The low order word is multiplexed as a LOW A signal. It is transmitted to lexer 304. The multiplexer selects bits ( VA corresponding to 2) 5RCE (2) Controlled by the virtual address source signal It will be done. VA 5RCE (2) Multiplexing according to the virtual address source signal The server 304 uses one of the input signals as the DATA SET A signal to drive the gate. Supply to bar 310.

A similar signal is transmitted from the data storage cellar) 39B to the comparator 305 and the multiplayer VA 5RCE (8:3) virtual address source signal to The information is transmitted based on the entry determined there. multiplexer 30 6 is also controlled by the VA 5RCE(2) virtual address source signal, One of the HIGHB or LOWB input signals from the data storage area 38B. , DATA SET B signal is supplied to the gate driver 311.

The page frame number in register 302 is also transmitted to comparators 303 and 305. be done. The page frame number is also transmitted to comparators 303 and 305. The PAR parity signal is transmitted to a parity generator 307 which generates a PAR parity signal. register Page frame number from 302 and PAR parity from parity generator 307 The signal corresponds to the TAG+PARITY SET A signal, and the flag set 41 When the VALID SET A signal from A is input, the comparator 303 Enter the number of ET A HIT4.

Similarly, the page frame number from register 302 and parity generator 307 These PAR parity signals correspond to the TAG0 PARITYSET B signal, and the When the VALIDSET B signal from signal center 41B is input, the comparator The data input terminal 305 inputs the 5ETB HIT signal.

The SET A HIT and SET B HIT signals are SET　B　When one of the HIT signals is input, generates an input HIT signal. is supplied to OR gate 312.

The HIT signal is transmitted to the bus interface unit 33 and cache memory 35 contains the data determined by the virtual address in register 300. Correspondingly, the bus interface unit 33 CHE Input the XMIT internal bus cache transmission signal.

When the SET A HIT signal from the comparator 303 is input, the AND gate 3 130 input is also excited. IDAL CACHEXMIT internal bus scan When the multiplexer 3 transmission signal is input, the gate driver 310 Supplies the DATASET A signal from 04 to the internal IDAL bus 34 . Similarly, when the SET B HIT signal from the comparator 305 is input, the AN D gate 314 input DMI L, IDAL, CACIIE X? IIT When the internal bus scan transmission signal is input, the gate driver 311 connects the DATASET B signal from multiplexer 3064 to the internal I Supplied to the DAL bus 34.

The arrangement of cache memory 35 shown in FIG. 5 has various advantages. Primarily , the cache memory 35 shown in FIG. 5 is a two-way cent associative cache. In the meantime, each set in Figure 5 only has additional circuitry for additional cents. and it very easily extends to an n-way ('n' is an integer) cent associative cache. It will be done. Also, while converting a virtual address to a physical address, high-order focus (3 When a 1:9) conversion is performed to generate a page frame number, it is initially constant. Data storage set 39A based on bits (823) of the virtual address held in Bit or miss decisions can be made very quickly by accessing I can do it. If the required data is in the cache memory 35, the data data can be quickly obtained from there, which is the indoor bath stand, bath interface unit 3. 3 can initialize the data correction operation immediately after the page frame number is generated. .

Bus In - Facelo 33 Bus interface circuit 33 in one embodiment of processor 30 is shown in FIG. It will be done. Referring to FIG. 6, the bus interface circuit 33 connects the bus 13 (first A The operation of the state machine 270 and the internal IDAL bus 34 that control the two state machines 2, including a second state machine 271 that controls operations; 70 and 271 indicate that the state machine 270 requires operation of the bus 13, as shown below. A state machine and various flags and control signals indicate that the Except for the response signal supplied to state machine 271 to indicate completion of the operation, stand up and operate.

State machine 271 that controls internal IDAL bus 34 generally controls A source within processor 30 indicated by control logic 273, typically bus 13. various terminals on bus 13 as indicated by pins 274 of and control circuit 4 0 (FIG. 1B). statemacy The link 271 includes logic that controls the transfer in conjunction with the floating point processor 31. Circuit 272 and cache and address input multi-brainer 264 (FIG. 1B) ) to a controlled number of circuits within processor 30, including various signals controlling the functions of transmit force signals.

Additionally, the output signal of the state machine 271 is a logic signal including a flag (not shown). 276, as indicated by the state of the RD REQ continuation request signal. , indicates that the read process is bending, and the WRT REQ write request signal indicates that the write operation is bending, as indicated by the status of As indicated by the state of the BRDCST REQ communication request signal, the processor 3 The operand transfer from 0 to the floating point processor 31 is is currently in progress.

Control logic 276 controls the buffer during successive processing under the control of the operating system. Some information input from the cache 13 (Figure 1A) is stored in the cache 35 (Figure 1B). For example, the operating system The system is programmed to remember all information it reads in cache 35. Adjust the processor 35. The operating system also writes data to the cache 35. It does not allow the storage of pro-sensor instructions, but rather the storage of data to be processed in the cache. permission to do so. However, in JG, the operating system has various restrictions. The information entered from the control register is stored in the system cache 35 as shown in FIG. 1A. Will not allow memory to other parts of the system.

Control logic 276 controls caching of information input from bus 13. Adjusts the CACHE ACC cacheable access signal as follows.

As mentioned above, a unit external to processor 30 has a transfer line 61 (FIG. 1A). ) CCTL cache control on ■ What should be cached by means of signals It also controls whether

State machine 271 directly or indirectly controls other control M logic (not shown). The write data and continuation and write address from launch 250 to 252 are sent via also controls the loading and input data ramps based on the signal state on pin 274. It also controls the transfer of read data from chip 254.

A state machine 270 that controls transfers from bus 13 connects bus pins 274 to Similarly to the signals of RD REQ read request, WRTREQ write request, and BRDCS Inputs the TREQ communication request signal and controls the various signal states that make up the bus 13. It generates a signal to be transmitted to the controlling logic circuit 277. Also, statemacy Connector 270 generates a signal that is transmitted to control logic 280 and also connects D on bus 13. Enables signal supply and signal input to AL data/address line 50. Latches 250.251.252.254 and multiplexer 253 (Fig. 1B) ). After the successive processing is complete, the state machine 270 controls CLRR that allows logic 276 to cancel the RD REQ read request signal D.FLAGS Clear read flag signal is also input.

Against this background, the operation of the bus control circuit 33 shown in FIG. 6 will be explained. writing place During the process, the DMA ORWRT PND ( DMA or write processing) signal is input by control logic 273. If not, the state machine 271 first writes the write address launch 251 ( (Figure 1B) and the location of the address to be written to the cache. cache 35 (FIG. 1B). DMA　O If the RWRT PND signal is input, other units of the system shown in Figure 1A If the write address uses bus 13 or state machine 271 The remaining seven channels 251 and 250 (first (Figure B).

The DMA ORWRT PND (DMA or write bending) signal is If the location to be written is not entered by the logic 273, the location to be written is A decision is made as to whether the If the location is cached, then The entry in cache 35 corresponding to the location is amped up with the new data. To determine whether the 0 position that must be cached is The host machine 271 uses CHACHE to enable the cache to be read. FTN (1: O) Cache function signal and multiplexer 264 are virtual The physical address generated by the address conversion circuit 37 can be used. CHAC) IEADR3(1:0) signal is generated. During this operation, IDA LCHACHE XMIT cache transmission signal (Figure 5) is an internal data data from the cache to be provided to the tabus 34. If the 0 position is cached, the HIT signal is sent to AND gate 312 (FIG. 5). This is reflected in the state of the MI SS signal from the control logic 273. be done.

If the MISS signal is not input, the location to be written is cached. no In response to the specified Miss signal, the state machine 271 performs a cache write. CHACHEFTN (1:0) cache function signal and master that enable operation. The multiplexer 264 performs the physical address generated by the virtual address translation circuit 37. Generates the CHACHE ADR3 (1: O) signal that enables the address to be used. do. At the same time, the data written to the cache entry is the write data flags in the control logic are input Coordinated to generate the WRREQ write request signal. During this operation, MBOX The 5ALL signal is input to disable the operation of the virtual address translation circuit.

On the other hand, when the Miss signal is input, the write position is canceled. Input MI In response to the SS signal, the state machine executes write data launch 250 of the write data. (Figure 1B), and the control logic 2 of the WRT REQ signal. CHACHE ADR3 (1:0) The refresh address signal increments the refresh counter 262 (Figure 1B). and multiplexer 264 supplies flag 42 head address. , tag 41 and data store 38 (FIG. 1B) to refresh them. adjusted to allow for. During this operation, the virtual address translation circuitry To prevent the production of physical addresses, to make it impossible to operate, The MBOX 5 TALL signal is also input.

After the write process is completed, DMA ORWRT PND (DtlA or write bending) signal is rejected. This allows other address and write data The data is loaded into latches 250 and 251 (FIG. 1B). Refresh behavior It is also possible to create.

The operations performed or enabled by state machine 271 during succession processing are as follows: Whether the requested information is an instruction or data, and the requested information is stored in the cache 35 (Figure 1B). ) depending on whether it was within or not. The position determined by the address is cached. case, and tongue 41A, 41B or which disables the cache entry. If there is no parity error in either data 38A or 38B (Figure 5), the information will be It's in the cache. A follow-up process is required to revoke the order, in which case the control The control logic 273 outputs an IB REQ command command buffer request signal. Otherwise For example, the control circuit 40 inputs the RD continuous output signal. Request information is in cache 35 If not, the control logic 273 also inputs the READ MISS signal.

The READ Miss signal indicates completion of the HIT signal shown in FIG.

RD successive signal input from control circuit 40 or IB REQ command command buffer required Depending on the signal strength, state machine 271 enables cache reads. CHACHE FTN (1: O) Cache function signal and multiplexer 264 (Figure 1B) can use the address from the virtual address translation circuit 37. Generates the CHACHE ADR5 (1:O) signal to At the same time, stay Thomasin 271 specifies the virtual address to be loaded into read address latch 252. ARM ADR3ATR arm address that enables address conversion logic Input the dress strobe signal. That operation was in response to the IBREQ signal. If it is possible to set the control logic flag, PREV IB REQ pre-order INIT IB REQ initial instruction buffer that enables input of instruction buffer request signal The state machine 271 also receives an input request signal.

If the information is in cache 35, state machine 271 35 to 1, to the operation terminal as described above in connection with Figure 5. Allow to be supplied.

If the information is not in the cache 35, and DtlA ORWRTPND (DM A or write bending) signal is input, the state machine 271 is both the 5TALL, MBOX, and 5TALL signals that stall the processor 30. Inputs the CACHE ADR3 (1: O) signal that allows refresh operations. Strengthen.

Due to this stall, the write process is completed before the successive process is executed.

DMA ORWRT PND (DMA or write bending) signal rejected If the RD REQ read request is executed, the state machine 271 proceeds with the successive processing. The request signal can be input to the control logic 276. State machine 271 is , then CACHEABLE, CCTL cache control, RDY ready and E The end of successive processing is determined by monitoring the RR error signal. If CACHEABL E or CCTL cache control signal indicates that the information should not be cached , there is one transfer via bus 13. On the other hand, if the information is If the cache entry (first (Figure 5), one is for low words and the other is for high words. When the RDY ready signal is input, if DAL PARERR No parity error signal is input, indicating that the input information has no parity error. state machine 271 causes multiplexer 264 (FIG. 1B) to address from the virtual address translation circuit to select an entry in cache 35. information can be loaded into one of the selected high or low words. shall be able to be coded. The word in cache 35 into which information is to be loaded is VA (2) Corresponds to the state of the virtual address bit (see Figure 5). The information is that It is then fed to data path 36 (FIG. 1B).

DAL PARERR If parity error signal is input or ERR error A signal is input to line 55 (FIG. 1A) to connect other units operating within the transfer. If an error response due to knitting is indicated, processing is performed before PREV IB REQ. Depends on whether the instruction buffer request signal is input. If so, the control Path 40 (FIG. 1B) indicates the input IB FILL ERR command command buffer buffer. The file error signal prompts and allows it to perform the correct operation. P.R.E. V IB REQ pre-previous instruction buffer request signal If not input, 5TALL and The MBOX 5 TALL signal is input and stalls the processor 30, and TRAP The REQ trap request signal is input, which causes the processor control circuit 40 to Select or allow cover operation.

ERR errors when input information is cached and as data is entered - signal is in state when DAL PARERR parity error signal is input. Once the second word 2 has been properly entered, the machine 271 reads it as described above. It is stored in cache 35. The state machine 271 is a multiplexer - CAC that enables the use of addresses from the virtual address translation circuit 37 in 264 HE　ADR3(1:　O) Cache address signal and second word cache CACHE FTN (1:O) that enables storage in the entry generates a switch function signal. The state machine 271, however, Transfer to route 36 is not possible.

On the other hand, the ERR error signal or DAL PARERR parity error signal is input. When the MBOX 5TALL signal is input, the virtual address conversion circuit 37 is skipped. the entry in the cache where the first word is written is marked invalid. be done. At the same time, CACHE ADR3 (1:0) 4 refreshes the contents of cache 35 and increments the counter The refresh address from refresh counter 262 is used for It will be adjusted.

The state machine 271 stores the information from the state machine 271 to the information cache 35. If it is not possible to write or read data, refresh operations can be performed. shall be. To enable processing to occur, state machine 271 includes multiple Lexer 264 receives the refresh address signal from refresh counter 262. The contents of memory circuits 38, 41 and 42 (Figure 1B) are stored in the conventional manner using Generates the CACHEADR3 signal that allows refreshing.

State machine 271 also indicates that entries in cache 35 are In response to the DMA INV REQ invalidation request signal from the block 273, the is possible. As described above in connection with Figure 1B, the input CCTL cache control Both the signal and the input ADR3STR address strobe signal are shown in Figure 1A. When input by other units in the system, this depends on the coincidence of both signals. signal is generated. Other units are connected to DMR (direct memory access) along with memory 11. This occurs when the DMG directly performs a memory ground signal is input.

If another unit is cached by cache 35, the position in memo 1J11 is If the data is transferred to another location, the cache entry is marked as invalid. . Referring to Figure 1B, the DMG and ADRS STR address strobe signals Depending on the match, the AND game) 401 inputs the input data launch 254, in this case the It is possible to launch the signal that is the address signal onto the DAL data/address line 5o. shall be.

In response to the DMA INV REQ invalidation request signal, the state machine 271 First, allow data from the cache to be provided onto the internal bus 34. cache 3 using the address in input data latch 254 without Execute the read operation in step 5. If the MI SS signal is input, the position is .

nothing happens.

However, if the MISS signal is negated, the The location identified by address is cached and the state machine starts a cache invalidation operation. At this time, the state machine enables the disable operation. Cache function signal CACHE FTN (1:0) Multiplexer 264 uses the contents of the input data launch for Cache address signal CACHEADR3 (1:0 ) occurs.

State machine 270 receives cache control signals CC from bus 13, direct memory Request signal DMR, ready signal RDY and error signal ERR1 control logic read request signal RD REQ, write request signal WR from T REQ, broadcast request signal BRDC3T, # and cache Access signal CACHE ACC and direct memory access prohibited Signal INHDMA and arm read request signal ARM RD REQE It operates accordingly. If state machine 270 is in another unit in the system shown in FIG. asserted direct memory indicating that the client wishes to transfer via bus 13 ・After receiving the request signal DMR, the DMA inhibit signal INHDMA or Unless the broadcast request signal BRDC5TREQ is asserted, This machine negates the direct memory grant disable signal DIS DMG and then This negated signal causes the control logic 277 to directly represent the memory grant signal DMG. make it possible to clarify This asserted direct memory grant DMG is allows clients to perform transfers over bus 13. Furthermore, the condition Machine 270 asserts the DATA IN signal, which is The DAL III control logic 280 provides allows other devices to use the DAL data/address lines 50.

State machine 270 also asserts the TRl-5TATE STR signal; The control logic 277 receives the data strobe signal DATA from other devices. STR, address strobe signal ADRS STR and transfer type signal TR Allows you to use TYPE.

Instead, if any other device in the system transfers via bus 13 If not, state machine 270 returns (7) RD from control No. 276. REQ signal, WRT REQ signal, and broadcast request signal BRDC3T may enable transfer on bus 13 in response to the REQ signal; If write request signal WRTREQ is asserted, launch 251 and and write address and write data in latch 250 (see Figure 1B). is indicated, and if the DMR signal is not asserted, state machine 270 , multiplexer 253 converts the write address from latch 251 into DAL data. DAL C0NT (1 : 0) (DAL content) Generates a signal. At the same time, state machine 270 The strobe enable signal ADR5S 5TREN is asserted, but then This signal is then used by control logic 277 to generate an address strobe signal ADRSS. Allows to assert TR.

Next, the state machine 270 outputs the (DAL content) signal DAL C0NT(1:O) This signal causes the multiplexer 253 to select the write data and the other channel. 250 contents onto the DAL data/address line 50. Become. State machine 270 simultaneously outputs data strobe enable signal DAT. A STREN is asserted, but this signal causes the control logic 277 to - Strobe signal DATA STR can be asserted.

After this, the state machine determines whether ready signal RDY or error signal ERR is asserted. remains in the waiting state until If an asserted RDY signal is received, this Operation is based on address strobe enable signal ADR3STREN and data. - When the straws are activated by these signals, the control logic 277 then Dress strobe signal ADR3STR and data strobe signal DATA STR can be negated, and control logic 276 can also negate WRTR. It becomes possible to negate the EQ signal.

On the other hand, if the asserted error signal ERR is received, the state machine 27 0 attempts to retry and converts the data signal from launch 250 to DAL data/address. DAL C that allows multiplexer 253 to couple onto line 50 Generates a 0NT (1:0) (DAL content) signal.

If both ready signal RDY and error signal ERR are asserted, A try signal is sent and the transfer is attempted again.

If no other operations are occurring, state machine 270 Generates C0NT (1: 0) (DAL content) signal, and uses this signal to The plexer 253 converts the contents of the read address latch 252 into DAL data/address. connection on the response line 50 becomes possible. This causes state machine 27 0 indicates a read operation when other signals and conditions permit a read operation to occur. Operation can be started quickly. During read operation, read request signal RD REQ is asserted, state machine 270 asserts address strobe enable signal A DR35TREN and then this signal causes control logic 277 to Res strobe signal ADR3STR can be asserted. state machine 270 then asserts the data-in signal DATAIN and is controlled by this signal. Logic 280 indicates that other devices in the system are connected to DAL data/address lines 5. It becomes possible to condition these lines so that 0 can be used. at the same time , the state machine receives the data strobe enable signal DATA STREN. This signal then causes control logic 277 to assert the data strobe signal. It becomes possible to assert the number DATA STR.

The next operation is that the cacheable access signal CACHE ACC is the control logic 276. If this signal is asserted, the search The stored data can be cached, so the two words are sent one after the other via bus 13. be done. On the other hand, if the cacheable access signal CACHE ACC is asserted When the retrieved data is not cacheable and requires only one The code is read out via bus 13. Cacheable access signal CHA CH If EACC is not asserted, state machine 270 asserts the input signal RD DATALAT, which, when asserted, 254 (see FIG. 1B) on the DAL data/address lines 50. It becomes possible to receive signals. After that, a series of data launch signals RD When ATA LAT is negated, the signal is latched by the input launch. if The error signal ERR is negated and the read flag clear signal CLRRD FL When AGS is asserted, state machine 270 responds to the asserted ready signal RDY. asserted to 0 to negate the read data launch signal RD DATA LAT. In response to the CLRRD REQ signal, control logic 276 issues a read request signal. No. RD REQ is denied.

On the other hand, if the cacheable access signal CACHE ACC is asserted, A read operation is performed as described above. Data latched during input data launch If the cache control signal CCTL is not asserted when is also executed.

On the other hand, if the cache control signal CCTL is asserted and other devices involved in the transfer If it appears that the location prevents data caching, the second action The work will not be executed.

The state machine 270 directly receives memory request signals DMR from other devices. state machine to prohibit asserting the direct memory grant signal DMG in response. 271 uses a direct memory access inhibit signal INHDM,A. direct memo The re-access inhibit signal INHDMA is activated during the transfer of the floating point processor 3] (see Figure 1A).

Read broadcast signal 11111 from control circuit 40 BRDC3T and and the basic broadcast signal BASICBRDC3T are processed by the state machine 271. , from cache 35 or from data bus 36 (data path 36 ) can transfer floating point/operand information from REGISF 255 in make it possible. Control logic 276 also receives broadcast request signal BR. The DC3TREQ signal can now be asserted, and then state machine 270 , allowing this information to be transferred as described above.

State machine 271 also outputs floating point processor bending signal FPP Enable control logic 273 to set a flag to assert ND.

The state machine 271 receives the results of floating point operations from the floating point processor 31. In order to indicate to the PPP interface circuit 272 that it is ready to receive, As mentioned above, the 0 condition code asserting the dynamic point processor signal SIG PPP is in the ready state, the interface circuit 272 asserts the CP OK signal. , and if the result data is in the ready state, assert the ready signal CP RDY. do. In response to the ready signal CPRDY, state machine 271 causes state machine 27 0 to receive result data. If floating point processor 31 , when the error occurrence signal is sent, the interface circuit 272 sends the X-2-signal CP E Express RR4. In response to the CP OK, CP RDY or ERR signal, the status Machine 271 sets a flag B that controls floating point processor bending signals. is reset, thereby negating this signal.

Bus interface circuit 33 provides many benefits. First, individuals were different. Two state machines 270 and 270 control operations and communicate via flags. By using H.271, the circuit is considerably simplified.

Furthermore, the state machine 271 enables refresh operations of the cache 35. , which allows dynamic storage elements to be used therein. child This reduces the physical dimensions of the cache or As was the case in This makes it easy to provide multiple storage devices.

Furthermore, the bus interface circuit 33 detects cacheable data. During the search, the program first retrieves the data it needs and then searches the cache. Searching for other words for storage in the entry of the file is evaluated. In earlier systems, words of data were stored in memory. therefore, the first data word is the one the program needs immediately. It was not necessarily the case that the This will search for the second word. The resumption of processing was delayed until the

Furthermore, the interface circuit 33 suspends (bending) the write operation. ), the read address is generated and the read address latch 25 2, allowing the start of a read operation. The continuous operation is Not completed until the pending write operation is completed, but the write operation is completed Therefore, the read address can be sent immediately.

Finally, the bus interface circuitry also ensures that read or write operations are The system shown in FIG. direct memory access operations performed by other devices Enables entries to be invalidated. i.e. write data and write addresses are launched during respective launches 251 and 250 (see Figure 1B). (see) Furthermore, when the read address is launched during launch 252, the cache is The DMA address received during input launch 254 It is possible to generate it in response to the dress. This allows you to process is simplified.

The above description has been limited to specific embodiments according to the invention. However, the book Modifications and improvements may be made to the invention that may achieve some or all of the advantages of the invention. It will be obvious that modifications may be made and it is therefore the object of the appended claims to reflect the invention. We reserve the right to protect all such changes and modifications within the spirit and scope of authenticity. Is Rukoto.

Claimed to be new and covered by United States Letters Patent The requirements are described on the next page.

::・, No change in latent content) FIG, 2A FIG, 3A Sign table flat 1-5028tiO(22) FIG, 3C (I!Sote address conversion 3rd page) I　6　4J　□　,-,/-&φ-IL% Commissioner of the Patent Office Yoshi 1) Mr. Moon Takeshi 1. Indication of case PCT/US 881004533, person making amendment Relationship to the case: Applicant 5. Date of amendment order: Self-issued 7. Contents of amendment as attached international search report international search report USε8004S3 SA21184

Claims (2)

[Claims] 1. Processing means for generating virtual addresses, transfers using physical addresses Translation means and means for translating virtual addresses to physical addresses. and an operation mode instruction means for instructing one of a plurality of operation modes. In the processor used in the digital data processing device, the translation means comprises A. Before virtual address storage means connected to the storage processing means and receiving virtual addresses therefrom; contains multiple entries, each for storing virtual addresses, and each when the content of that entry corresponds to a virtual address from said processing means. A virtual address record that includes a hit signal generating means that generates a hit signal when memory means and B. A plurality of entries connected to the transfer means each storing a physical address. physical address storage means, each entry of which corresponds to said virtual address storage means; is connected to receive a hit signal from one entry in the a physical address which is enabled to transmit a physical address to said transfer means accordingly; dress memory means; C. A means of protection, i. It includes a plurality of entries each storing a protection code, and each entry stores the temporary protection code. a secure storage means associated with one entry of the virtual address storage means; i. connected to the operation mode instruction means and instructed by the operation mode instruction means; An encoder that generates an encoded operating mode code in response to the operating mode specified. - ding means; iii. the protected storage means, the encoding means, and the virtual address storage means and said protection connected to said transfer means and identified by said hit signal. comparing the contents of the entry in the storage means with the encoded operating mode code; and and said transfer means transfers a physical address from said physical address storage means in response to a positive comparison. protection measures, including protection comparison measures that allow the use of A processor characterized by comprising: 2. Processing means for generating virtual addresses, transfers using physical addresses Translation means and means for translating virtual addresses to physical addresses. and an operation mode instruction means for instructing one of a plurality of operation modes. In a translation device used with a digital data processing device, A. connected to the processing means. virtual address storage means connected to and receiving virtual addresses therefrom, each virtual Contains multiple entries for remembering addresses, each entry a hit signal when the contents of the entry correspond to the virtual address from said processing means; virtual address storage means including means for generating a hit signal; B. A plurality of entries connected to the transfer means each storing a physical address. physical address storage means, each entry of which corresponds to said virtual address storage means; is connected to receive a hit signal from one entry in the a physical address which is enabled to transmit a physical address to said transfer means accordingly; dress memory means; C. A means of protection, i. It includes a plurality of entries each storing a protection code, and each entry stores the temporary protection code. a secure storage means associated with one entry of the virtual address storage means; ii. connected to the operation mode instruction means and instructed by the operation mode instruction means; An encoder that generates an encoded operating mode code in response to the operating mode that is coding means; iii. the protective storage means; the encoding means; connected to the virtual address storage means and the transfer means and responsive to the hit signal; The contents of the entry of the protected storage means identified by the encoded operational model and the transfer means, in response to a positive comparison, transfers the physical address to the physical address code. and a protective comparison means that allows the physical address from the storage means to be used. step by step A translation device comprising: