JPH0147125B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic driving vehicle, specifically a steering angle detector provided on a steering wheel, a sampling means for sampling the output of the steering angle detector at predetermined time intervals, and a steering angle detector provided on a steering wheel. It has a memory that stores sampling values, and a drive circuit that reads out the memory contents and steers the steering wheels so as to reproduce the steering angle stored in the memory contents, so that the vehicle can be artificially steered while driving. A teaching playback method that stores the steering angle of the steering wheels from the starting point when the vehicle is running automatically, and during automatic driving, replays the steering of the steering wheels based on the memorized steering angles. related to self-driving vehicles.

In a vehicle that automatically travels using such control means, the deviation from a predetermined course tends to gradually increase as the vehicle travels. The cause of such course deviations is the reproduction error in the direction of travel, so in order to achieve practical long-distance automatic travel using this method, it is necessary to
It is necessary to eliminate such reproduction errors.

For this purpose, it is necessary to precisely reproduce the steering angle of the steering wheel during teaching during playback, and it is advantageous to use digital memory because there is no uncertainty in the storage medium or signal processing. However, since only intermittent sampling values are stored in the digital memory, errors will occur during playback unless sampling is done at small sampling intervals depending on how quickly the steering angle changes. Conversely, reducing the sampling interval requires more memory.

The present invention aims to eliminate such tradeoffs.

For this purpose, the automatic traveling vehicle of the present invention has a rate of change detection means for detecting a temporal change in the output of the steering angle detector, and when the output of the rate of change detector is equal to or higher than a predetermined value, This method is characterized by being equipped with a means for reducing the sampling interval, which saves memory, and does not cause the drawbacks of the conventional method even when the operating speed of the steering wheel during teaching is high. , there is no need to set a limit on the steering speed.

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 shows a lawn mower in which an automatic traveling vehicle according to the present invention is used as a traveling machine body 1, and the automatic traveling vehicle according to the present invention is a lawn mower used as a traveling body 1.
A lawn mowing device 4 is suspended between the front and rear wheels 2 and 3 so as to be able to move only vertically. The front wheel 2 is a steering wheel for steering, and a potentiometer 5 for detecting a steering angle is attached to the front wheel 2.

FIG. 2 is a hydraulic circuit diagram for steering the front wheels 2. A hydraulic cylinder 6 for steering the front wheels 2 is connected to a hydraulic pump 8 via an electromagnetic valve 7, and the electromagnetic valve 7 has an oil flow direction. Left and right solenoids 9 and 10 are provided to move the valve body to be changed, and the front wheels 2 are steered by operating these solenoids 9 and 10.

FIG. 3 shows a control circuit for storing and reproducing steering angles. This control circuit is switched between teaching and playback by switch _SW1 , and during playback, switch _SW1 is set to mode line M.
When teaching, a high level signal is emitted to
Switch _SW1 outputs a low level signal to mode line M. During playback, the switch SW' ₁ linked to the switch SW ₁ closes the line for inputting the output of the potentiometer section 5 provided on the front wheel 2, which is the steering wheel, to the drive circuit 13 of the electromagnetic valve 7. On the other hand, it is designed to open during teaching. Artificial control during teaching is performed by a switch provided in the drive circuit 13.
Turn ON/OFF SW ₄ and SW ₅ to turn on solenoid valve 7.
This is done by operating the left and right solenoids 9 and 10. The mode line M is input to the inhibit terminal of the change rate detection circuit 12 and the latch C, and when there is a high level signal on the mode line M, the output of the flag and sampling data, which are the respective outputs of these two circuits, is inhibited. .
Furthermore, the mode line M is input to an inverter _N1 , and the output of this inverter _N1 is output to the second mode line M'. The second mode line M' is input to the flag input gate G ₅₁ which is the output of the rate of change detection circuit 12, and to the inhibit terminal of the D/A converter 16 on the output side of the memory section 14.

Therefore, during teaching, the gate _G51 is open, the flag signal can pass through, and the rate of change detector 1
Flag 2 can be output to flag line F,
Latch C outputs the sampled value and D/A converter 16 does not output. On the other hand, during playback, gate _G51 is closed, rate of change detector 12 does not generate a flag signal on flag line F, and latch C does not output a sampled value onto data bus D.
Due to the model line M being input to the clock pulse generator G, this generator outputs slow pulses during playback. Furthermore, memory 1
A second mode line M' is input to the read/write mode terminal 4', and the mode is set to write mode during teaching and read mode during playback.

During teaching, the steering angle of the front wheels 2 is detected by the potentiometer 5', and the steering angle of the front wheels 2 is detected by the potentiometer 5'.
1 and sampled by latch C at the rising edge of timing pulse _φ2 ;
It is stored in memory 14'. On the other hand, latch A of the change rate detector 12 detects the change rate of the steering angle while sampling the output of the A/D converter 11 at a timing pulse φ ₁ earlier than φ ₂ . Next, to explain each part, latch A of change rate detector 12 latches the output of A/D converter 11 at the rising edge of timing pulse φ ₁ , and then latches the output of A/D converter 11 at the falling edge of pulse φ ₁ . Its value is latched. At the rise of the next pulse _φ1 , that value is latched in latch B, and the current A/
The output of D converter 11 is latched into latch A. The values of latch A and latch B are each input to a subtracter 12a, and the difference between the two is constantly output from the subtracter 12a. This difference is input to the digital comparator 12b, and when the absolute value is greater than the reference value, a high level output is output from the digital comparator 12b to the flag line F. This reference value is generated by the reference value generator 12c.
It is caused by. This flag line F is the AND of the timing pulse generator 15.
It is entered into gate G ₅₁ . This AND gate
_G51 is open only during teaching and outputs the signal level on flag line F. On the other hand, the timing pulse generator 15 has its counter 15'
The output from the clock pulse generator G is input to the counter 15', and the timing pulse φ ₁ is output from the lower bit output terminal of this counter 15', and the slower pulse φ ₃ is output from the output terminal of the higher bits than this bit. It is being output. The pulse φ ₁ is input to the change rate detection circuit 12 as a synchronizing pulse, and is also input to the gate G ₅₃ in the timing pulse generator 15. One pulse _φ3 is input to the gate _G52 . The output _of gate G51 is input to these gates _G52 and _G53 in a branched manner, and a knot circuit _N51 is interposed only on the gate _G52 side. Therefore, when there is a high level output from gate _G51 , gate _G52 closes and gate _G53 opens, so pulse _φ1 is output as pulse _φ2 , and conversely, low level is output from gate _G51 . Sometimes pulse φ ₂ becomes φ ₃ which is slower than pulse φ ₁ .

The early timing pulse φ ₁ is used as a sampling timing pulse for the change rate detector 12, and the other timing pulse φ ₂ is input to the latch C for storage, and is also input to the memory 1.
4' is input via a delay line 17. The delay line 17 is provided to increase the processing time of the change rate detector 12. The flag, which is the output of the rate of change detector 12, is stored in the memory 14' together with the sampling value, which is the output of the latch C.
Therefore, during teaching, values sampled at short time intervals are stored together with the flag only when the change in steering angle is large. On the other hand, during playback, the clock pulse generator G generates a pulse that is slower than during teaching, and the vehicle speed is set to be correspondingly slower. The output of the gate _G51 of the timing pulse generator 15 is always at a low level, and the timing pulse _φ2 always matches the timing pulse _φ3 . The value of the memory 14' read out at the timing of the pulse φ ₂ is converted into an analog signal by the D/A converter 16, and this output and the output of the potentiometer section 5 are input to the differential amplifier A ₃₁ of the drive circuit 13. , the left and right solenoids 9 and 10 are actuated to steer the steering wheel 2 so as to reproduce the stored value in the memory 14'. A ₃₂ and A ₃₃ of the drive circuit 13 are comparators provided to generate an output when the output of the differential amplifier A ₃₁ is above a certain value. A flag stored at the time of teaching is output from the memory 14' together with the sampling value, and a vehicle speed control circuit, which will be described later, is configured so that the vehicle speed is reduced by the output of this flag.

That is, in response to the input at short sampling intervals during teaching, the flag becomes a flag that slows down the vehicle speed during playback. This flag signal is sent to a vehicle speed control circuit, which will be described later, only during playback.

The switch SW ₂ is a start switch, which starts the clock pulse G and also starts the memory 14'.
Activates the one-shot circuit SH that generates a pulse to initialize the address. and memory 1
The address of 4' is specified by an address counter AC that counts pulses φ ₂ .

Furthermore, the switch _SW3 is for stopping the operation of the clock pulse G.

Figure 4 shows the vehicle speed control circuit described above, in which the vehicle speed is determined by changing the gear lever of the hydraulic continuously variable transmission to a DC motor.
Move with MO. The rotation of this motor MO in two directions, forward and reverse, is controlled by turning ON and OFF relay switches 18' and 19'. A vehicle speed setting device 20 outputs a set potential. As this set voltage, a lower potential is output during playback than during teaching, and the set vehicle speed is lower. The output of the vehicle speed setting device 20 is amplified by the amplifier 21, and when the flag is output during playback, the flag operates the relay solenoid 22 and switches the resistors 23 and 23'. 22' and 22'' are turned on. Therefore, the gain becomes small and the output of the amplifier 21 becomes a low potential.
The target vehicle speed becomes slower. On the other hand, the vehicle speed is detected by a differential transformer 24 and a rectifier 25 provided on the speed change lever, and the target value and the detected value are input to comparators 26 and 27, and these outputs actuate relays 18 and 19. and turn relay switches 18' and 19' ON/OFF. Thus the motor
MO moves the gear lever to reach the target value.

In this embodiment, sampling storage and reading are configured by a hard logic circuit, but it is obvious that the hard logic circuit can be configured using a CPU and a program. For example, the hard logic 100 within the two-dot chain line in FIG. 3 is as shown in FIG.
The program is replaced with the flowchart program shown in FIG.

Figure 5 is a flowchart during teaching.
_T10 is a short sampling time corresponding to the sampling time of the latch A, and _T20 is a time corresponding to the pulse _φ2 .

(i) and (ii) are A/D converter 11 every ₁₀ hours.
The value of is sampled and entered into register A, and the previous value is entered into register B.

(iii) to (v) are A/D converter 11 every T ₂₀ hours.
The value of is sampled into register C and then stored along with the flag.

(vi) to (viii) switch _T20 and change the flag depending on the difference between the values of register A and register B.

On the other hand, during playback, only the memory contents, ie, the steering angle and flag, are output at set time intervals.

[Brief explanation of drawings]

The drawings show an embodiment of an automatic driving vehicle using a teaching playback system according to the present invention, in which Fig. 1 is an overall side view, Fig. 2 is a hydraulic circuit diagram for steering, and Fig. 3 is a diagram for reproducing memory of steering angles. FIG. 4 is a vehicle speed control circuit diagram, and FIGS. 5 and 6 are flowcharts of another embodiment. 2... Steering wheel, 5... Steering angle detector, C...
Sampling means, 14'...Memory, 13...
...Drive circuit, 12... Rate of change detector.

Claims (1)

[Claims] 1. A steering angle detector 5 provided on the steering wheel 2, a sampling means C that samples the output of the steering angle detector 5 at predetermined time intervals, a memory 14' that stores this sampling value, and the In a teaching playback type automatic driving vehicle having a drive circuit 13 for reading the memory contents and steering the steering wheel 2 so as to reproduce the steering angle of the memory contents, the steering angle detector 5
Change rate detection means 1 for detecting temporal changes in the output of
2, and comprising means for reducing the sampling interval when the output of the change rate detector 12 is equal to or greater than a predetermined value.