JPH0145170Y2 - - Google Patents

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Publication number
JPH0145170Y2
JPH0145170Y2 JP1982039722U JP3972282U JPH0145170Y2 JP H0145170 Y2 JPH0145170 Y2 JP H0145170Y2 JP 1982039722 U JP1982039722 U JP 1982039722U JP 3972282 U JP3972282 U JP 3972282U JP H0145170 Y2 JPH0145170 Y2 JP H0145170Y2
Authority
JP
Japan
Prior art keywords
address
circuit
image signal
memory
control circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1982039722U
Other languages
Japanese (ja)
Other versions
JPS58141659U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3972282U priority Critical patent/JPS58141659U/en
Publication of JPS58141659U publication Critical patent/JPS58141659U/en
Application granted granted Critical
Publication of JPH0145170Y2 publication Critical patent/JPH0145170Y2/ja
Granted legal-status Critical Current

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  • Editing Of Facsimile Originals (AREA)
  • Studio Circuits (AREA)
  • Storing Facsimile Image Data (AREA)
  • Fax Reproducing Arrangements (AREA)

Description

【考案の詳細な説明】 本考案はフアクシミリ装置などに用いられるダ
ブル複写機能を有する記録装置に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a recording device having a double copying function used in facsimile machines and the like.

最近のフアクシミリ装置に於いては、送受信機
能の他に複写機能を備えたものがあり、中には縮
小複写機能を備えたものも既に提案されている。
Some recent facsimile machines are equipped with a copying function in addition to the sending and receiving functions, and some have already been proposed that are equipped with a reduction copying function.

しかしながら、此種フアクシミリ装置の複写動
作は、読取器から導出された画信号を記録器に印
加することによつて行なうものであるから、1回
の動作で1枚のコピーしか採れないと云う欠点が
あつた。
However, since the copying operation of this type of facsimile machine is performed by applying the image signal derived from the reader to the recorder, it has the disadvantage that only one copy can be made in one operation. It was hot.

そこで、本考案は小さい原稿の場合には、2枚
のコピーが同時に採れるようにした記録装置を提
案するものである。
Therefore, the present invention proposes a recording device that can simultaneously make two copies of a small original.

以下、本考案の記録装置をフアクシミリ装置に
適用した場合を例にとり、説明する。図面はその
概略構成を示すブロツク図である。
Hereinafter, an example in which the recording device of the present invention is applied to a facsimile device will be explained. The drawing is a block diagram showing a schematic configuration thereof.

図面において、1は1ライン分の画素数または
それ以上の素子数を有するCCD等からなる読取
器、2はこの読取器から導出される各1ライン分
の画信号を送信用メモリ3に書込み読み出すため
のアドレス制御回路、4は送信用メモリから読み
出された画信号を圧縮コード化する符号化回路、
5はそこで符号化された信号を変調すると共に受
信信号を復調する変復調回路である。
In the drawing, 1 is a reader consisting of a CCD or the like having the number of pixels for one line or more, and 2 is for writing and reading out image signals for each line derived from this reader into a transmission memory 3. 4 is an encoding circuit for compressing and encoding the image signal read out from the transmission memory;
5 is a modulation/demodulation circuit that modulates the encoded signal and demodulates the received signal.

一方、6は前記変復調回路5から導出された符
号化信号をデコードする復号化回路、7はそのデ
コードされた画信号が順次1ライン分ずつ書込ま
れる受信用のメモリ回路、8はそこから読出され
た画信号を増幅する記録増幅回路、9は前記読取
器と同数の素子を有するサーマルヘツド等からな
る記録器、10,11は原稿及び記録紙を副走査
方向に夫々1ライン分ずつ移送せしめる原稿搬送
回路及び記録紙搬送回路、12は前記各回路2,
3,4,6,7,10,11の動作を制御するマ
イクロプロセツサー等からなる制御回路である。
On the other hand, 6 is a decoding circuit that decodes the encoded signal derived from the modulation/demodulation circuit 5, 7 is a receiving memory circuit in which the decoded image signal is sequentially written one line at a time, and 8 is a memory circuit for reading from there. 9 is a recorder consisting of a thermal head or the like having the same number of elements as the reader; 10 and 11 are for transporting the original and the recording paper by one line each in the sub-scanning direction. a document conveyance circuit and a recording paper conveyance circuit; 12 represents each of the circuits 2;
This is a control circuit consisting of a microprocessor, etc., which controls the operations of 3, 4, 6, 7, 10, and 11.

ここで、前記アドレス制御回路2は例えば記録
器がB4幅のものであれば、B6判の原稿を複写す
る場合は前記読取器1からの各1ライン分の画信
号の各ビツトを送信用メモリ回路3の対となる二
つの番地即ちi番地と(1024+i)番地(i=
0,1,2,…)に書き込むようにアクセスを行
なう。また、前記メモリ回路3,7はともに少な
くとも前記読取器1から導出される画信号の1ラ
イン分のビツト容量を持つ2個のラインメモリか
らなり、そのラインメモリの一方が書込み状態の
時に他方が読出し状態になるように構成されてい
る。
Here, for example, if the recorder is of B4 size, the address control circuit 2 stores each bit of the image signal for each line from the reader 1 into a memory for transmission when copying a B6 size original. Two paired addresses of circuit 3, i.e. address i and (1024+i) address (i=
0, 1, 2,...). Further, both of the memory circuits 3 and 7 are composed of two line memories each having a bit capacity for at least one line of the image signal derived from the reader 1, and when one of the line memories is in a writing state, the other one is in a writing state. It is configured to be in a read state.

本考案で特徴とするところは、ダブル複写時に
アドレス制御回路2によつて上述の如く送信用メ
モリ回路3の書込みを制御する仕方にある。従つ
て、以下は、B4判標準原稿の幅の半分であるB6
判の原稿を、主走査方向に2個並設して複写する
場合の動作を例に採つて説明する。
The feature of the present invention lies in the manner in which writing in the transmission memory circuit 3 is controlled by the address control circuit 2 during double copying as described above. Therefore, the following is B6, which is half the width of a standard B4 manuscript.
The operation will be explained by taking as an example the operation when copying two sized originals side by side in the main scanning direction.

複写動作は図示しない複写モード設定スイツチ
等の投入によつて読取器1〜メモリ回路3、メモ
リ回路7〜記録器9、及び搬送回路10,11が
動作し、符号化回路4〜復号化回路6が動作しな
い状態で行なわれる。この状態でダブル複写スイ
ツチ13を投入すると、制御回路12はアドレス
制御回路2が前述した動作を行なうよう制御する
と共に、メモリ回路3,7に次の動作を行なわせ
る。
In the copying operation, the reader 1 to the memory circuit 3, the memory circuit 7 to the recorder 9, and the transport circuits 10 and 11 operate by turning on a copy mode setting switch (not shown), and the encoding circuit 4 to the decoding circuit 6 operate. It is carried out in a state where it is not working. When the double copy switch 13 is turned on in this state, the control circuit 12 controls the address control circuit 2 to perform the above-described operation, and also causes the memory circuits 3 and 7 to perform the following operation.

即ち、読取器1から導出されたB6判の各1ラ
イン分の画信号(2048ビツト)が前記アドレス制
御回路2の書込みアクセスによつて送信用メモリ
3に前述の如く書込まれる。ここで原稿はB6判
であるから原稿の左端をB4判原稿と同じ位置に
セツトすれば、読取器1の出力は1ビツト目から
1024ビツト目までに画信号が、また、1025ビツト
目から2048ビツト目には白情報が現われる。従つ
てアドレス制御回路2は送信用メモリに画信号部
分の1024ビツトを各ビツト毎に受信用メモリのi
番地と(1024+i)番地に順次書込む。それ故、
受信用メモリ3には0〜1023番地と1024番地〜
2047番地にB6判の同じ画情報が並設して書込ま
れることになる。この場合、アドレス制御回路は
読取器1からの画信号の各ビツトを上記メモリ回
路3に書込む際に1ビツト間に2回アドレスを行
なえばよいわけである。そして同時に上記メモリ
回路3内の書込みが既に終了している他方のライ
ンメモリに対して、前記アドレス制御回路2の読
出しアクセスによつて、0番地から2047番地まで
順次1番地ずつ読み出しが行なわれる。従つて、
上記メモリ回路4から導出される画信号(2048ビ
ツト)は同一内容の1024ビツトの情報が主走査方
向に揃列された信号型式となり、この画信号の各
ビツトが受信用メモリ回路7に順次転送される。
そして、このメモリ回路7から1ラインずつ遅れ
て読出される画信号が記録増幅器8を介して記録
器9の対応する各素子に印加されて記録される。
従つて、記録画は主走査方向にB6判が2枚並設
されたものとなる。
That is, the image signal for each line of B6 size (2048 bits) derived from the reader 1 is written into the transmission memory 3 by the write access of the address control circuit 2 as described above. Here, the original is B6 size, so if you set the left edge of the original in the same position as the B4 original, the output of reader 1 will start from the 1st bit.
An image signal appears up to the 1024th bit, and white information appears from the 1025th bit to the 2048th bit. Therefore, the address control circuit 2 transfers the 1024 bits of the image signal portion to the transmitting memory into the i of the receiving memory for each bit.
Write sequentially to address and (1024+i) address. Therefore,
Reception memory 3 has addresses 0 to 1023 and addresses 1024 to
The same image information in B6 size will be written side by side at address 2047. In this case, when the address control circuit writes each bit of the image signal from the reader 1 into the memory circuit 3, it is sufficient to perform addressing twice between each bit. At the same time, by the read access of the address control circuit 2 to the other line memory in which writing in the memory circuit 3 has already been completed, reading is performed sequentially one address at a time from address 0 to address 2047. Therefore,
The image signal (2048 bits) derived from the memory circuit 4 has a signal format in which 1024 bits of information with the same content are aligned in the main scanning direction, and each bit of this image signal is sequentially transferred to the receiving memory circuit 7. be done.
Then, the image signal read out from the memory circuit 7 with a delay of one line is applied to each corresponding element of the recorder 9 via the recording amplifier 8 and recorded.
Therefore, the recorded image is two B6 size sheets arranged side by side in the main scanning direction.

なお、これまでは標準原稿がB4判の場合にB6
判の原稿をダブル複写するものとして説明した
が、標準原稿がA4判の場合はA6判を同様にダブ
ル複写することができる。
In addition, until now, if the standard manuscript was B4 size, B6
Although the description has been made assuming that a standard document is double-copied, if the standard document is A4-size, A6-size can be similarly double-copied.

また、上述した実施例において、記録器9は読
取器と同数の素子を有するサーマルヘツド等の場
合について説明したが、シリアル型のプリンタや
インクジエツトプリンタ、レーザプリンタ等が適
用できることは言うまでもない。
Further, in the above-described embodiments, the recorder 9 is a thermal head having the same number of elements as the reader, but it goes without saying that a serial printer, an inkjet printer, a laser printer, etc. can also be used.

更に、送信動作及び受信動作については、本考
案の要旨に直接関係ないので説明を省略するが、
図示の構成から容易に理解できるであろう。ただ
し、通常送信時にはアドレス制御回路2は送信用
メモリ回路3の書込みアクセスも画信号の1ビツ
ト毎に1番地ずつ順次行なう点に注意すべきであ
る。
Furthermore, the explanation of the transmitting operation and receiving operation will be omitted as they are not directly related to the gist of the present invention.
This will be easily understood from the illustrated configuration. However, it should be noted that during normal transmission, the address control circuit 2 also sequentially performs write access to the transmission memory circuit 3 one address at a time for each bit of the image signal.

本考案の記録装置は以上の如く構成されたもの
であるから、原稿幅が標準原稿の半分であれば、
1回の複写動作で2枚の記録画を同時に得ること
ができ、また記録時間も1枚の場合と同じである
から、複写機能を備えるフアクシミリ装置として
優れたものである。
Since the recording device of the present invention is configured as described above, if the document width is half that of a standard document,
It is an excellent facsimile machine with a copying function, since it is possible to simultaneously obtain two recorded images in one copying operation, and the recording time is the same as in the case of one copy.

【図面の簡単な説明】[Brief explanation of the drawing]

図面は本考案記録装置の要部概略構成を示すブ
ロツク図である。 1……読取器、2……アドレス制御回路、3…
…送信用メモリ回路、7……受信用メモリ回路、
8……記録増幅回路、9……記録器、12……制
御回路、13……ダブル複写スイツチ。
The drawing is a block diagram showing a schematic configuration of the main parts of the recording apparatus of the present invention. 1...reader, 2...address control circuit, 3...
...Memory circuit for transmission, 7...Memory circuit for reception,
8...Recording amplifier circuit, 9...Recorder, 12...Control circuit, 13...Double copying switch.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 読取器から導出された各1ライン分の画信号が
順次導入されるメモリ回路と、書込み時は同じ画
信号を重複して上記メモリ回路に書込むべく、上
記画信号の各ビツト毎に上記メモリ回路のi番地
と(n+i)番地(i=0,1,2,…,n−
1,nは1ライン分の画信号の画素数)を順次ア
クセスし、読出し時はこのメモリ回路の各番地1
番地ずつアクセスするアドレス制御回路とを備
え、上記アドレス制御回路によつて上記メモリ回
路から読出された画信号の各ピツトを記録器に導
き、同一書画を主走査方向に2個併設して複写記
録するようにした事を特徴とするダブル複写機能
を有する記録装置。
A memory circuit into which image signals for each line derived from the reader are sequentially introduced; Address i and (n+i) address of the circuit (i=0, 1, 2,..., n-
1 and n are the number of pixels of the image signal for one line) are accessed sequentially, and at the time of reading, each address 1 of this memory circuit is accessed sequentially.
and an address control circuit that accesses each address one by one, and the address control circuit guides each pit of the image signal read from the memory circuit to a recorder, and copies and records two identical calligraphies in the main scanning direction. A recording device having a double copying function, characterized in that:
JP3972282U 1982-03-19 1982-03-19 Recording device with double copy function Granted JPS58141659U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3972282U JPS58141659U (en) 1982-03-19 1982-03-19 Recording device with double copy function

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3972282U JPS58141659U (en) 1982-03-19 1982-03-19 Recording device with double copy function

Publications (2)

Publication Number Publication Date
JPS58141659U JPS58141659U (en) 1983-09-24
JPH0145170Y2 true JPH0145170Y2 (en) 1989-12-27

Family

ID=30051000

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3972282U Granted JPS58141659U (en) 1982-03-19 1982-03-19 Recording device with double copy function

Country Status (1)

Country Link
JP (1) JPS58141659U (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6054563A (en) * 1983-09-06 1985-03-29 Fuji Xerox Co Ltd Copying machine

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5614346A (en) * 1979-07-12 1981-02-12 Toshiba Corp Write and read system for frame memory unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5614346A (en) * 1979-07-12 1981-02-12 Toshiba Corp Write and read system for frame memory unit

Also Published As

Publication number Publication date
JPS58141659U (en) 1983-09-24

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