JPH0143493B2 - - Google Patents

Description

[Detailed description of the invention]

(Field of Industrial Application) The present invention relates to a signal converting device in a maximum likelihood error correction system that is extremely effective in reducing bit errors in digital communications. (Prior Art) With the recent trend toward digitalization of communication lines, the introduction of error correction methods, which are extremely effective in improving communication quality, into actual systems is being actively studied. There are many types of error correction methods, and among them, an error correction method that combines convolutional coding and maximum likelihood decoding is well known as a very powerful error correction means. Maximum likelihood decoding is a method in which the receiving side calculates the likelihood (certainty if it is actually transmitted) for all signal sequences that can be transmitted on the transmitting side based on the actual received signal sequence. It is a decoding means that determines the signal sequence showing the greatest likelihood among these as the signal sequence actually transmitted from the transmitting side. In particular, by performing soft-decision demodulation on the receiving side, information on the probability of each code symbol of the received signal sequence is given for its state (“1” or “0”), and the signal sequence is If a decoding means (soft-decision maximum likelihood decoding method) is used to accurately calculate the likelihood for , the error correction ability will be much stronger. However, when attempting to actually perform maximum likelihood decoding, the number of signal sequences (data patterns) that must be predicted on the receiving side increases exponentially as the transmitted data sequence becomes longer. When configuring , the hardware scale exceeds the realistic range. One way to solve such problems is to
A well-known Viterbi decoding method uses an algorithm that can efficiently perform maximum likelihood decoding by eliminating unnecessary likelihood calculations on the receiving side as much as possible. and,
This maximum likelihood error correction device that combines Viterbi decoding and convolutional coding has a low coding rate;
Moreover, hardware implementation has already been realized for codes with relatively short code constraint lengths. The coding rate here is the ratio of the number of input bits to the number of output bits of the coding circuit, and when the number of input bits is 1 and the number of output bits is 2, the coding rate is 1/2. The increased number of bits at this time indicates the degree of redundancy of the encoded code sequence. As the coding rate increases and approaches 1 (for example, 7/8), the redundancy of the code sequence decreases, and the error correction ability generally decreases. The code constraint length refers to the length of the input data sequence required to generate each output bit of the encoding circuit. However, it is generally known that the hardware scale of a decoding device that decodes a convolutional code with a coding rate ko/no and a code constraint length K using the Viterbi decoding method is approximately proportional to S in the following equation. (Literature reference: JAHeller and IM Jacobs,
“Viterbirecording for satellite and space
communications,” IEEE Trans.Commun.
Tecknol., vol.COM−19, pp.835−847,
Oct.1971) S=2 ^ko(k-1) (1) Equation (1) is the coding rate of the convolutional code used.
This means that as ko/no increases or as the encoding constraint length K increases, the hardware scale of the decoding device increases exponentially. The main reason for this is that as the code constraint length of the code sequence becomes longer or the coding rate becomes higher, the number of internal states of the code increases and the number of operations required by the decoder increases. As a result, in the prior art, even if Viterbi decoding is used, it is virtually possible to realize an error correction apparatus that can be applied to a code sequence having a coding rate exceeding 3/4. On the other hand, in communication systems with severe bandwidth limitations, from the viewpoint of effective use of bandwidth, it is desired to realize an error correction method that reduces the redundancy of information transmission as much as possible and has a large error correction capability. The present invention has been made in view of the above-mentioned prior art,
By using low coding rate encoding and decoding circuits that are relatively easy to implement in hardware, adding simple peripheral circuits to these circuits, and converting to a high coding rate on the communication channel for transmission. , it is an object of the present invention to provide a decoding device in a communication system that can equivalently perform error correction of high coding rate codes. (Example) A detailed explanation will be given below with reference to the drawings. FIG. 1 is a conceptual diagram when data is encoded and decoded based on the maximum likelihood error correction method according to the present invention. Input data series 1 is converted into encoded data series 3 by convolutional encoding circuit 2 and sent to coded symbol erasure circuit 4 . In FIG. 1, encoding with a coding rate of 1/2 is assumed, and encoded data series 3 is displayed as a parallel signal.
The code symbol erasing circuit 4 refers to the contents of the erasure pattern holding circuit 6 that holds a predetermined erasure pattern 5, and while erasing code symbols from the encoded data series 3, generates a transmission data series having a predetermined communication speed. Generate 7. In the example shown in FIG. 1, "1" in the erasure pattern 5 indicates the position of the code symbol to be actually transmitted, and "0" indicates the position of the code symbol to be erased. The operations described above are performed by the encoding device 10 to generate the transmission data sequence 7 from the input data sequence 1. Transmission data series 7 is transmitted through communication channel 1 with noise 11.
2 to the receiving side. The received data sequence 13 on the receiving side is obtained by demodulating the received signal, which is the transmitted signal corresponding to the transmitted data sequence 7 with noise 11 added, by hard decision or multilevel soft decision. can get. Soft-decision demodulation is a method that adds information indicating the reliability of the demodulated information to normal binary demodulation information of "1" or "0" and outputs it as multi-value information. For example, 8-value soft Assuming decision demodulation, each code symbol in the received data sequence 13 is 3
It will be made up of bits. As mentioned above, when maximum likelihood decoding is performed using such soft-decision demodulated data, the accuracy of likelihood calculation increases and the error correction ability becomes stronger. The received data series 13 is sent to a dummy symbol insertion circuit 14. The dummy symbol insertion circuit 14 refers to the contents of the insertion pattern holding circuit 16 that holds the insertion pattern 15 corresponding to the erasure pattern 5 on the transmission side, and corrects the received data sequence 13 corresponding to the code symbol erased on the transmission side. A dummy symbol (dummy data for the required number of bits during soft-decision demodulation) is inserted at the position to generate a decoding circuit input data series 17 having a predetermined communication speed. Here, the dummy data may be either 1 or 0. The x mark in the decoding circuit input data series 17 in the example of FIG. 1 indicates an inserted dummy symbol. This decoding circuit input data system example 17 is sent to a maximum likelihood decoding circuit 19 (here, a Viterbi decoding circuit is assumed). However, a predetermined likelihood value is fixedly given to the inserted dummy symbol to minimize the transmission bus selection error probability based on the likelihood calculation for each transmission path during maximum likelihood decoding. It is necessary to hold down. For this reason, for example, the dummy symbol insertion circuit 14 needs to have a function of sending the likelihood calculation inhibition pulse 20 for the inserted dummy symbol to the maximum likelihood decoding circuit 19. On the other hand, the maximum likelihood decoding circuit 19 may be configured as a Viterbi decoding circuit corresponding to the convolutional encoding circuit 2 on the transmitting side, but the dummy symbol insertion circuit 1
A control circuit that, when receiving a likelihood calculation prohibition pulse 20 from 4, temporarily prohibits normal likelihood calculation for the input symbol at the relevant timing and assigns a predetermined fixed likelihood value. Is required. In this way, by performing maximum likelihood (Viterbi) decoding while forcibly giving a likelihood value to the inserted dummy symbols, the decoded data series 8 is output from the maximum likelihood decoding circuit 19.
Above, from received data series 13 to decoded data series 8
An operation is performed by the decoding device 21 to obtain . The above is a specific explanation of the maximum likelihood error correction method according to the present invention, and the following can generally be said about the coding rate of this error correction method. The coding rate of the convolutional coding circuit 2 used in the coding device 10 is ko/no, and the erasure pattern 5 is
1 block of encoded data series 3 (1 block is
Consists of no symbols. ), then the coding rate of the transmission data series 7 for the input data series 1 is ko'/no' as shown in equation (2). ko′/no′=kol/nol−m (2) Therefore, the coding rate when using the maximum likelihood error correction method is equal to ko/no (when m=0), or
By appropriately selecting the value of l or m in equation (2), maximum likelihood error correction can be performed freely for codes with any coding rate higher than ko/no. There is. On the other hand, the error correction ability of the maximum likelihood error correction method in the present invention, that is, the bit error rate characteristic after decoding, is determined by the erasure symbol ratio (m/
(nol) and m erasure symbol positions. Here, a convolutional code with a coding rate of 1/2 and a constraint length of 7 (a Viterbi decoder for this code has already been implemented in hardware)
, the convolutional encoding circuit 2 in the encoding device 10
Assume that it is used for At this time, the optimal erasure pattern when performing maximum likelihood error correction by constructing a code with an appropriate coding rate of 1/2 or more using the maximum likelihood error correction method is:
Under a given coding rate, a computer examines the distance structure of codes obtained from all possible erasure patterns 5, and selects one erasure pattern that provides a code with the best error rate characteristics after Viterbi decoding. By selecting, it can be uniquely determined. Table 1 shows the optimal erasure patterns when configuring codes with coding rates from 2/3 to 7/8 based on the maximum likelihood error correction method using a 1/2 code with a constraint length of 7 as the original code. This is the result. The optimal erasure patterns in the table are displayed as erasure patterns for parallel symbols after 1/2 encoding. Therefore, when this pattern is displayed in series, it becomes "111001" in 3/4 code, for example.

【table】

[Table] In the table, l and m mean that m bits in l block (2l symbols) after 1/2 encoding are periodically erased. For reference, the table also shows the minimum distance d of each code and the total number C _k of error bits included in all erroneous paths whose distance from the correct path is d. Generally, it is known that the bit error rate characteristics after Viterbi decoding become better as d becomes larger and, for the same d, as the value of C _k becomes smaller. Therefore, from the same table, as the coding rate of the code increases (i.e.,
It is expected that as the erasure rate of 1/2 encoded symbols increases, the bit error rate characteristics during Viterbi decoding will deteriorate. Figure 2 shows that the coding gain at the achieved bit error rate = 10 ^-6 is calculated by theoretically calculating the bit error rate characteristics during 8-level soft-decision Viterbi decoding for each code shown in Table 1. , which is compared with that of a two-error correcting self-orthogonal code that has been commonly used in the past. The horizontal axis shows the band expansion rate (reciprocal of the coding rate n-1/n) decibel value of each code. However, the coding gain here refers to the required E _b /N _p (E _b : Energy per 1 bit of information, No: One-sided noise power density) is defined as the difference. From the same figure, 1/2 of restraint length 7
When a convolutional code is used as an original code and the error correction method based on the present invention is combined with an 8-ary soft decision, the coding gain is considerably larger than that of a typical convolutional code, which is a two-error correcting self-orthogonal code. , even when compared with 7/8 code, the achieved bit error rate =
It can be seen that this is about 1.3 dB better in terms of 10 ^-6 . In this way, the maximum likelihood error correction method can provide extremely excellent bit error rate characteristics even for codes with high coding rates. Furthermore, as LSI technology develops in the future, there is a good chance that hardware encoding circuits and Viterbi decoding circuits for convolutional codes with a coding rate of 1/2 and a constraint length greater than 7 will be realized in the near future.
In that case, by performing maximum error correction based on the maximum likelihood error correction method, it is possible to easily realize an error correction device for high coding rate codes that has characteristics even better than those shown in FIG. Can be done. Next, the encoding device 10 based on the maximum likelihood error correction method
A specific method of configuring the decoding device 21 will now be described. FIG. 3 shows an example of the configuration of the encoding device 10 when the convolutional encoding circuit 2 in the encoding device 10 uses a code with a coding rate of 1/2 and a constraint length of 7. The convolutional code circuit 2 includes seven stages of sister registers 22 and an exclusive OR gate 23. Assuming that the rate of the input data series 1 is R, the circuit operates by supplying a shift lock 24 with a rate R. The encoded parallel data series 3 is converted into a serial data series 26 by the parallel/serial conversion circuit 25.
After being converted into , it is sent to a first-in first-out (FIFO) memory 27 . on the other hand,
The erase pattern holding memory 28 that holds the contents of the erase pattern 5 specified from the outside has a speed of 2R.
The address counter 30 operated by the supply of the clock 29 sequentially outputs the contents of the specified address. The address counter 30 has an erasure symbol pattern 5 of length l block (number of symbols: 2l).
Erase pattern holding memory 28 containing the contents of
It has the function of specifying the addresses of 1 in sequence periodically. Output signal 31 of erase pattern holding memory 28
and the continuous clock 29 with a speed of 2R are ANDed by an AND gate 32, and the resulting blank clock 33 is supplied as a write clock to the FIFO memory 27. Therefore, only the encoded data 26 at the time when the write clock 33 is supplied is selectively written into the FIFO memory 27. When the erasing period specified by the erasing pattern 5 is 1 block and the number of erasing symbols is m, a clock with a speed of (2l-m/l)R is supplied as the reading clock 34 from the FIFO memory 27, and the FIFO The data written in the memory is read out as continuous data converted to a predetermined speed (2l-m/l)R, and this is output as the transmission data series 7. Figure 4 shows the phase relationship of the clocks required in Figure 3 using the 7/8 code (l = 7, m6 →
2l-m/l=8/7). In the same figure, A is the clock 24 at speed R, B is the clock 29 at speed 2R, C is the output signal 31 of the erase pattern holding memory 28 when the erase pattern 5 is serially read out, and D is the output signal 31 between B and C. The toothless clock 33 with a speed of 2R and E generated by taking the logical product is a read clock 34 with a speed of 8/7R. Next, FIG. 5 shows an example of the configuration of the decoding device 21 corresponding to the encoding device 10 having the configuration shown in FIG. 3. In principle, the decoding device 21 performs the opposite operation to that on the transmitting side. In other words, a dummy symbol is reinserted in the position of the erased code symbol, and a data sequence with the same speed as the encoded data sequence with a speed of 2R generated by the encoding circuit 2 is reconstructed, and then a 1/2 convolutional code is generated. Maximum likelihood decoding is performed using the Viterbi decoding circuit 19 for (constraint length K=7). Hereinafter, it is assumed that the received data series 13 is soft-decision data, and that the Viterbi decoding circuit 19 is capable of calculating (hereinafter referred to as metrics) for soft-decision input data. The received data series 13 uses a receiving clock at a speed of (2l-m/l)R as a writing clock 35.
Written to FIFO memory 36. On the other hand, insertion pattern 15 corresponding to deletion pattern 5 on the sending side
The insertion/holding memory 37 holding the address sequentially outputs the contents of the addresses specified by the address counter 39 operated by the supply of the clock 38 at a speed of 2R. The address counter 39 has a function of periodically and sequentially specifying the addresses of the insertion pattern holding memory 37 containing the contents of the insertion symbol pattern 15 of length l block. The output signal 40 of the insertion pattern holding memory 37 and the continuous clock 38 with a speed of 2R are ANDed by an AND gate 41, and the resulting toothless clock 42 is
The FIFO clock is supplied as a read clock for the FIFO memory 36 and is synchronized with the toothless clock 42.
Data is read from memory 36. On the other hand, the output signal 40 of the insertion pattern holding memory 37 is also used for controlling the switch 43, and the switch 43 inserts a dummy symbol into the FIFO memory 36 at the timing when data is read from the FIFO memory 36. At the right timing, it is controlled to be connected to the dummy data holding circuit 44 side. The decoding circuit input data series 17 obtained by the above procedure is input to the Viterbi decoding circuit 19. Furthermore, the polarity of the output signal 40 of the insertion pattern holding memory 37 is inverted by an inverter 45, and then a metric calculation inhibition pulse 20 is generated for the insertion dummy symbol.
The signal is sent to the Viterbi decoding circuit 19 as a signal. In the Viterbi decoding circuit 19, input data series 1
7 and metric calculation inhibition pulse 20 in series/
After being converted into parallel signals by parallel conversion circuits 47 and 48, a metric calculation circuit 48 executes metric calculation for the parallel input symbols. The metric calculation circuit 48 has a function of prohibiting normal metric calculation and forcibly giving a specific metric value to input symbols to which the metric calculation prohibition pulse 20 is sent at the same time. When metric calculation is disabled, the effect on the maximum likelihood path selection function in Viterbi decoding can be minimized by giving the same metric value to data "0" and "1", but this will be discussed later. In order to minimize the influence on the self-synchronization function of the soft decision data, it is most preferable to give an intermediate value between the maximum and minimum metric values for the soft decision data. The metric value 49 calculated by the metric calculation circuit 48 is transferred to the surviving path selection section 51 at a clock 50 having a speed R. Survival path selection section 51
Here, a path metric storage circuit 52 stores path metric values of surviving paths up to that point in each internal state of the code, and a surviving path memory 5 stores a bit sequence of each surviving path.
Based on the information from 3 and the metric value 49 at that point, select the surviving path in each internal state,
Based on the results, the path metric storage circuit 52
The contents of the remaining path memory 53 are updated one after another. The decoded data 8 is sequentially outputted from the surviving path memory 53 with a delay corresponding to the length of the aborted path specified in advance. The decoding procedure in the Viterbi decoding circuit 19 is described in the literature (GDForney,
J.R., “The Viterbi Algorithm”, proceedings
of the lEEE.vol−61, No.3, March.1973,
(pp.268-276) for details. Note that the surviving path memory 5 in the Viterbi decoding circuit 19 used in this method
The truncation path length in 3 needs to be considerably longer as the coding rate increases; for example, in the first
The 3/4 code shown in the table requires 60 bits, and the 7/8 code requires about 100 bits. By the way, when this decoding device 21 is used for continuous data, a self-synchronization function in units of erasure patterns is required in order to always insert dummy symbols at correct positions in the received data series 13. Such self-synchronization on the receiving side can be performed, for example, as follows. In general, when the codes are synchronized and the signal-to-noise power ratio is large to a certain extent, the path metric value during Viterbi decoding will be large only for a path with a certain characteristic, and the metric values of other paths will be The value will be quite low. On the other hand, when an out-of-synchronization occurs, the metric values of all paths are averaged to a constant value. Therefore, in the Viterbi decoding circuit 19, based on the size of the metric of each path,
It becomes possible to create metric information that is a measure of the code synchronization state. For this purpose, the metric information 54 created by the path metric storage circuit 52 is sent to the synchronization state monitoring circuit 55, and when the metric information 54 enters a predetermined value range that is considered to be an out-of-synchronization state, An address control pulse 56 is sent from the synchronization state monitoring circuit 55 to the address counter 39. The address counter 39 receives the address control pulse 56
This has a function of shifting the read address from the insertion pattern holding memory 37 by one symbol. The synchronization state monitoring circuit 55 repeats the above control at regular time intervals, and the Viterbi decoding circuit 19
When the metric information 54 from the address control unit returns to the range of values considered to be in synchronization, it is determined that the out-of-synchronization has been recovered, and the sending of the address control pulse 56 is stopped. By the above operation, it is possible to automatically detect out-of-synchronization of codes on the receiving side and achieve a function of recovering synchronization. The phase relationship between the clocks necessary for the operation of the decoding device 21 in FIG. 5 is the same as that of the encoding device 10 shown in FIG. 4, and therefore will not be described here. Furthermore, in the above explanation of the configuration and operation of the error correction device, it is assumed that all input/output data sequences are serial continuous signals, but these may be parallel signals or burst data at a predetermined speed. As explained above, by using the decoding device in the maximum likelihood error correction system according to the present invention, it is possible to realize a maximum likelihood error correction device for high coding rate codes, which has been considered difficult to configure in hardware. Moreover, when combined with soft-decision demodulation, its error correction ability is considerably superior to the characteristics of existing error correction codes, making it extremely useful for improving the communication quality of various digital communication lines. effective. Furthermore, the error correction device using the decoding device in the present error correction system has the great feature that the coding rate of the code to be used can be freely selected and specified by selecting the erasure pattern. In the future, it is thought that it will be possible to apply adaptive error correction, which performs error correction by always selecting a code with the optimal coding rate depending on the line condition, increasing the flexibility of line design for digital communication lines. , it is also very effective.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the basic concept of the maximum likelihood error correction method in the present invention, and FIG.
The coding gain of the n-1/n code at the achieved bit error rate of 10 ^-6 when performing error correction using the maximum likelihood error correction method using an 8-value soft decision using the 2-code as the original code is expressed as Figure 3 shows a configuration example of an encoding device based on the maximum likelihood error correction method, and Figure 4 shows a clock signal necessary to operate the encoding device shown in Figure 3. Figure 5 is a diagram showing the phase relationship of 7/8 code as an example.
1 is a diagram illustrating a configuration example of a decoding device based on a maximum likelihood error correction method. DESCRIPTION OF SYMBOLS 1... Convolutional encoding circuit, 4... Code symbol erasure circuit, 12... Communication channel, 14... Dummy symbol insertion circuit, 19... Maximum likelihood decoding circuit.

Claims (1)

[Claims] 1. In a decoding device in a system in which a data sequence to be transmitted is redundantly encoded on the transmitting side and maximum likelihood decoded on the receiving side, a dummy symbol insertion pattern corresponding to a coded symbol erasure pattern on the transmitting side is provided. an insertion pattern holding circuit that holds the insertion pattern; a dummy symbol insertion circuit that inserts a dummy symbol at a position corresponding to a code symbol erased on the transmission side of a received data series while referring to the insertion pattern holding circuit; 1. A decoding device comprising: decoding means for giving a predetermined likelihood value to a dummy symbol inserted by a circuit to perform maximum likelihood decoding.