JPH0137879B2 - - Google Patents
Info
- Publication number
- JPH0137879B2 JPH0137879B2 JP59068010A JP6801084A JPH0137879B2 JP H0137879 B2 JPH0137879 B2 JP H0137879B2 JP 59068010 A JP59068010 A JP 59068010A JP 6801084 A JP6801084 A JP 6801084A JP H0137879 B2 JPH0137879 B2 JP H0137879B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- thin film
- ground
- ceramic
- multilayer wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000010409 thin film Substances 0.000 claims description 44
- 239000000919 ceramic Substances 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 11
- 239000010408 film Substances 0.000 claims description 5
- 239000000463 material Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229920000620 organic polymer Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】 (発明の属する技術分野) 本発明は多層配線基板に関する。[Detailed description of the invention] (Technical field to which the invention pertains) The present invention relates to a multilayer wiring board.
(従来技術)
情報処理装置等に用いる配線基板においては、
その配線の高密度化およびこの配線を伝播する信
号の高速化を同時に達成できることが要求されて
いる。主に電源配線パターンを形成したセラミツ
ク積層配線部と薄膜法により形成した微細な信号
配線パターンを有する複数の薄膜配線層を持ち前
記セラミツク積層配線部上に形成した薄膜多層配
線部とから構成した基板が上記要求を満足させ得
る基板として用いられており、特に、薄膜配線層
間の絶縁材料として、ポリイミド系樹脂等の誘電
率の低いものを用いたときにはより一層の高速化
が可能である。(Prior art) In wiring boards used for information processing devices, etc.
It is required to simultaneously increase the density of the wiring and increase the speed of signals propagated through the wiring. A substrate mainly composed of a ceramic laminated wiring section on which a power supply wiring pattern is formed, and a thin film multilayer wiring section formed on the ceramic laminated wiring section, which has a plurality of thin film wiring layers having a fine signal wiring pattern formed by a thin film method. is used as a substrate that can satisfy the above requirements, and in particular, when a material with a low dielectric constant such as polyimide resin is used as an insulating material between thin film wiring layers, even higher speeds are possible.
このような従来の多層配線基板を第1図に示
す。第1図を参照すると、従来の基板は、複数の
セラミツク層12と該セラミツク層間の予め定め
た部分に形成された接地配線11、電源配線13
およびスルーホール14とを有するセラミツク積
層配線部10と、薄膜法により形成した微細な信
号配線21および23と複数の絶縁薄膜22とを
有する複数の薄膜配線層を持つ薄膜多層配線部2
0と、配線部20上に形成した部品取付端子25
と、配線部10と配線部20との間に形成された
接続パツド15と、配線部10上に形成された端
子ピン接続パツド16と、パツド16に接続され
た端子ピン17とから構成されている。 Such a conventional multilayer wiring board is shown in FIG. Referring to FIG. 1, the conventional board includes a plurality of ceramic layers 12, a ground wiring 11 and a power wiring 13 formed in predetermined areas between the ceramic layers.
and a ceramic laminated wiring section 10 having through holes 14, and a thin film multilayer wiring section 2 having a plurality of thin film wiring layers having fine signal wirings 21 and 23 formed by a thin film method and a plurality of insulating thin films 22.
0 and the component mounting terminal 25 formed on the wiring part 20
, a connection pad 15 formed between the wiring part 10 and the wiring part 20, a terminal pin connection pad 16 formed on the wiring part 10, and a terminal pin 17 connected to the pad 16. There is.
しかしながら、このような従来の多層配線基板
においては、薄膜多層配線部10内に形成された
薄膜配線21および23とセラミツク積層配線部
20内の接地配線11との距離がセラミツク層1
2の厚さにより変化するので、これにより薄膜配
線21および23の特性インピーダンスは設計値
に対してばらつく。また、このセラミツク層12
はセラミツク・グリーンシートを焼成してつくら
れるため、その厚さは、通常、あまり薄くでき
ず、0.1ミリメートル〜0.3ミリメートルの間にあ
り、この結果、薄膜配線の特性インピーダンスが
所定の値まで下らず、この配線と接続される回路
素子とのインピーダンス不整合やクロストーク特
性の悪化が生じるという欠点がある。 However, in such a conventional multilayer wiring board, the distance between the thin film wirings 21 and 23 formed in the thin film multilayer wiring part 10 and the ground wiring 11 in the ceramic laminated wiring part 20 is longer than the distance between the ceramic layer 1 and the ground wiring 11 in the ceramic laminated wiring part 20.
The characteristic impedance of the thin film wirings 21 and 23 varies with respect to the designed value. Moreover, this ceramic layer 12
Since it is made by firing a ceramic green sheet, its thickness cannot usually be made very thin, and is between 0.1 mm and 0.3 mm, and as a result, the characteristic impedance of the thin film wiring cannot be reduced to a predetermined value. First, there is a drawback that impedance mismatching and deterioration of crosstalk characteristics occur between the wiring and the circuit elements connected to it.
(発明の目的)
本発明の目的はセラミツク積層配線部と薄膜多
層配線部との境界面に予め定めた形状の接地配線
を形成することにより上述の欠点を除去した多層
配線基板を提供することにある。(Object of the Invention) The object of the present invention is to provide a multilayer wiring board in which the above-mentioned drawbacks are eliminated by forming a ground wiring in a predetermined shape on the interface between the ceramic laminated wiring part and the thin film multilayer wiring part. be.
(発明の構成)
本発明の基板は、複数のセラミツク配線層が積
層されたセラミツク積層配線部と、該セラミツク
積層配線部上に形成され予め定めたパターンを有
する接地配線と、薄膜法により形成した複数の薄
膜配線層を有し前記接地配線上に形成された薄膜
多層配線部とから構成される。(Structure of the Invention) The substrate of the present invention includes a ceramic laminated wiring part in which a plurality of ceramic wiring layers are laminated, a ground wiring formed on the ceramic laminated wiring part and having a predetermined pattern, and a ground wiring formed by a thin film method. and a thin film multilayer wiring section having a plurality of thin film wiring layers and formed on the ground wiring.
(実施例)
次に本発明について、図面を参照して詳細に説
明する。(Example) Next, the present invention will be described in detail with reference to the drawings.
第2図を参照すると、本発明の第1の実施例
は、複数のセラミツク層12とこのセラミツク層
12間の予め定めた部分に形成された接地配線1
1、電源配線13およびスルーホール14とを有
するセラミツク多層配線部10と、薄膜法により
形成した微細な信号配線21および23とヴイア
24と複数の絶縁薄膜22とを有する複数の薄膜
配線層を持つ薄膜多層配線部20と、配線部10
と配線部20との間に形成され予め定めた形状を
有する接地配線18および接続パツド15と、配
線部20上に形成した部品取付端子25と、配線
部上に形成された端子ピン接続パツド16と、パ
ツド16に接続された端子ピン17とから構成さ
れている。 Referring to FIG. 2, the first embodiment of the present invention includes a plurality of ceramic layers 12 and a ground wiring 1 formed at a predetermined portion between the ceramic layers 12.
1. A ceramic multilayer wiring section 10 having a power supply wiring 13 and a through hole 14, a plurality of thin film wiring layers having fine signal wirings 21 and 23 formed by a thin film method, vias 24, and a plurality of insulating thin films 22. Thin film multilayer wiring section 20 and wiring section 10
A ground wiring 18 and a connection pad 15 having a predetermined shape are formed between the wiring part 20 and the wiring part 20, a component mounting terminal 25 formed on the wiring part 20, and a terminal pin connection pad 16 formed on the wiring part. and a terminal pin 17 connected to the pad 16.
接地配線18はセラミツク積層配線部10の表
面に厚膜法により形成されている。この同じ表面
に形成された接続パツド15はセラミツク積層配
線部10内の配線と薄膜多層配線部20内の配線
21および23とをヴイア24を介して接続する
ためのものである。薄膜多層配線部20の底部全
域にわたつて接地配線18が分布しているので、
薄膜配線21および23の特性インピーダンスは
均一となり、その値は薄膜配線21および23自
体の幅寸法と絶縁薄膜22の膜厚および材質とか
らだけで定まる。すなわち、第10図に示すよう
に、絶縁層全体の厚さをH、信号配線の線幅を
W、信号配線間の間隔をS、信号配線ピツチを
D、信号配線の厚さをTおよび接地配線と信号配
線との距離をhとすると、薄膜多層配線の特性イ
ンピーダンスZ0は、
Z0=(Z0e・Z00)1/2〔Ω〕
ここで、Z0eは奇数次伝播項であり、Z00は偶数次
伝播項であり、それぞれ次のように表せる。 The ground wiring 18 is formed on the surface of the ceramic laminated wiring section 10 by a thick film method. The connection pads 15 formed on the same surface are for connecting the wiring in the ceramic laminated wiring section 10 and the wirings 21 and 23 in the thin film multilayer wiring section 20 via vias 24. Since the ground wiring 18 is distributed over the entire bottom of the thin film multilayer wiring section 20,
The characteristic impedance of the thin film wirings 21 and 23 is uniform, and its value is determined only by the width of the thin film wirings 21 and 23 themselves and the thickness and material of the insulating thin film 22. That is, as shown in Fig. 10, the thickness of the entire insulating layer is H, the line width of the signal wiring is W, the interval between the signal wirings is S, the pitch of the signal wiring is D, the thickness of the signal wiring is T, and the grounding. If the distance between the wiring and the signal wiring is h, the characteristic impedance Z 0 of the thin film multilayer wiring is Z 0 = (Z 0 e・Z 00 ) 1/2 [Ω] Here, Z 0 e is the odd-order propagation term. , and Z 00 is an even-order propagation term, which can be expressed as follows.
ただし、εre=εr{1−e×p(−1.55H/h)}
εr:絶縁層の比誘電率
絶縁薄膜22の膜厚および材質は、配線21およ
び23が薄膜法でつくられることから、かなり自
由に選択することができる。材質がガラス・セラ
ミツク系の場合には、誘電率は約10で膜厚は50
〜100マイクロメートル、材質が有機高分子の場
合には、誘電率は3〜7で膜厚は1〜50マイクロ
メートルとなり、薄膜配線の特性インピーダンス
は幅広い値のなかから決定することができる。接
続パツド15と接地配線18とは薄膜法で形成さ
れるために、精密微細なパターン形成が可能であ
る。このため、薄膜配線21および23の特性イ
ンピーダンスをきめ細かに制御することができ
る。また、接地配線18は直流的に接地されてい
なくても、交流的に接地されてさえいれば、薄膜
配線の特性インピーダンスを補正するように働
く。すなわち、接地配線18はセラミツク積層配
線部10内の接地配線11と接続されているが、
電源配線13と接続されていても同様に働く。 However, εre=εr {1-e×p(-1.55H/h)}
εr: Relative permittivity of the insulating layer The film thickness and material of the insulating thin film 22 can be selected quite freely since the wirings 21 and 23 are made by a thin film method. If the material is glass or ceramic, the dielectric constant is approximately 10 and the film thickness is 50.
~100 micrometers, and when the material is an organic polymer, the dielectric constant is 3 to 7 and the film thickness is 1 to 50 micrometers, and the characteristic impedance of the thin film wiring can be determined from a wide range of values. Since the connection pad 15 and the ground wiring 18 are formed by a thin film method, it is possible to form precise and fine patterns. Therefore, the characteristic impedance of the thin film wirings 21 and 23 can be precisely controlled. Furthermore, even if the ground wiring 18 is not grounded in terms of DC, as long as it is grounded in AC, it works to correct the characteristic impedance of the thin film wiring. That is, although the ground wiring 18 is connected to the ground wiring 11 in the ceramic laminated wiring section 10,
It works in the same way even if it is connected to the power supply wiring 13.
本発明の第2の実施例を示す第3図を参照する
と、本実施例は、接地配線18と接続パツド15
とが、セラミツク積層配線部10の研磨された表
面に薄膜法で形成されている点が第1の実施例と
異なるだけであるので説明は省略する。 Referring to FIG. 3 showing a second embodiment of the present invention, this embodiment has a ground wiring 18 and a connecting pad 15.
The only difference from the first embodiment is that it is formed by a thin film method on the polished surface of the ceramic laminated wiring section 10, so a description thereof will be omitted.
また、セラミツク積層配線部10の表面に形成
される接地配線18の形状としては、第4図に示
すようなシート状パターン、第5図に示すような
網目状パターン、第6図に示すような縞状パター
ン、第7図および第8図に示すような複数の島状
パターン、第9図に示すような複数の島状パター
ンの連結体等が考えられる。 The shape of the ground wiring 18 formed on the surface of the ceramic laminated wiring section 10 may be a sheet-like pattern as shown in FIG. 4, a mesh pattern as shown in FIG. 5, or a mesh pattern as shown in FIG. A striped pattern, a plurality of island patterns as shown in FIGS. 7 and 8, a combination of a plurality of island patterns as shown in FIG. 9, etc. can be considered.
(発明の効果)
以上、本発明には、薄膜多層配線部内に形成さ
れた薄膜配線の特性インピーダンスの設計値から
のバラツキおよび誤差を低減できるという効果が
ある。(Effects of the Invention) As described above, the present invention has the effect of reducing the variation and error from the design value of the characteristic impedance of the thin film wiring formed in the thin film multilayer wiring section.
第1図は従来の多層配線基板を示す断面図、第
2図は本発明の第1の実施例を示す断面斜視図、
第3図は本発明の第2の実施例を示す断面斜視
図、第4〜第9図は各種の接地配線パターンを示
す平面図および第10図は特性インピーダンスを
説明するための断面図である。
図において、10……セラミツク積層配線部、
11……接地配線、12……セラミツク層、13
……電源配線、14……スルーホール、15……
接続パツド、16……端子ピン接続パツド、17
……端子ピン、18……接地配線、20……薄膜
多層配線部、21……薄膜配線、22……絶縁薄
膜、23……薄膜配線、24……ヴイア、25…
…部品取付端子。
FIG. 1 is a sectional view showing a conventional multilayer wiring board, FIG. 2 is a sectional perspective view showing a first embodiment of the present invention,
FIG. 3 is a cross-sectional perspective view showing a second embodiment of the present invention, FIGS. 4 to 9 are plan views showing various ground wiring patterns, and FIG. 10 is a cross-sectional view for explaining characteristic impedance. . In the figure, 10...ceramic laminated wiring part,
11...Ground wiring, 12...Ceramic layer, 13
...Power wiring, 14...Through hole, 15...
Connection pad, 16...Terminal pin connection pad, 17
... terminal pin, 18 ... ground wiring, 20 ... thin film multilayer wiring section, 21 ... thin film wiring, 22 ... insulating thin film, 23 ... thin film wiring, 24 ... wire, 25 ...
...Component mounting terminal.
Claims (1)
ツク積層配線部と、該セラミツク積層配線部上に
形成され予め定めたパターンを有する接地配線
と、薄膜法により形成した複数の薄膜配線層を有
し前記接地配線上に形成された薄膜多層配線部と
から構成したことを特徴とする多層配線基板。 2 前記接地配線が、表面を研磨した前記セラミ
ツク積層配線部のこの表面上に薄膜法により形成
されたことを特徴とする特許請求の範囲第1項記
載の多層配線基板。 3 前記接地配線が、前記セラミツク積層配線部
上に厚膜法により形成されたことを特徴とする特
許請求の範囲第1項記載の多層配線基板。 4 前記接地配線のパターンが、シート形状、網
目形状、縞形状、島形状またはこれらを組み合わ
せた形状であることを特徴とする特許請求の範囲
第1項記載の多層配線基板。 5 前記接地配線は、交流的あるいは直流的ある
いは交流的または直流的に接地されていることを
特徴とする特許請求の範囲第1項記載の多層配線
基板。[Scope of Claims] 1. A ceramic laminated wiring part in which a plurality of ceramic wiring layers are laminated, a ground wiring formed on the ceramic laminated wiring part and having a predetermined pattern, and a plurality of thin film wirings formed by a thin film method. 1. A multilayer wiring board comprising: a thin film multilayer wiring section having a plurality of layers and a thin film multilayer wiring section formed on the ground wiring. 2. The multilayer wiring board according to claim 1, wherein the ground wiring is formed by a thin film method on the surface of the ceramic laminated wiring section whose surface has been polished. 3. The multilayer wiring board according to claim 1, wherein the ground wiring is formed on the ceramic laminated wiring portion by a thick film method. 4. The multilayer wiring board according to claim 1, wherein the pattern of the ground wiring is a sheet shape, a mesh shape, a striped shape, an island shape, or a combination thereof. 5. The multilayer wiring board according to claim 1, wherein the ground wiring is grounded AC or DC, or AC or DC.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6801084A JPS60211897A (en) | 1984-04-05 | 1984-04-05 | Multilayer circuit substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6801084A JPS60211897A (en) | 1984-04-05 | 1984-04-05 | Multilayer circuit substrate |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60211897A JPS60211897A (en) | 1985-10-24 |
JPH0137879B2 true JPH0137879B2 (en) | 1989-08-09 |
Family
ID=13361448
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6801084A Granted JPS60211897A (en) | 1984-04-05 | 1984-04-05 | Multilayer circuit substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60211897A (en) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0716100B2 (en) * | 1990-01-10 | 1995-02-22 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Multilayer wiring module |
JPH085579Y2 (en) * | 1990-02-08 | 1996-02-14 | 新光電気工業株式会社 | Thin film wiring board |
JP2579046B2 (en) * | 1990-09-19 | 1997-02-05 | 日本電気株式会社 | Multilayer wiring board |
JPH04132295A (en) * | 1990-09-21 | 1992-05-06 | Nec Corp | Multilayer wiring board |
JPH04252095A (en) * | 1991-01-28 | 1992-09-08 | Fujitsu Ltd | Ceramic printed circuit board |
JPH07123150B2 (en) * | 1992-03-06 | 1995-12-25 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Hybrid semiconductor module |
KR20010085811A (en) * | 1998-09-17 | 2001-09-07 | 엔도 마사루 | Multilayer build-up wiring board |
US9818682B2 (en) * | 2014-12-03 | 2017-11-14 | International Business Machines Corporation | Laminate substrates having radial cut metallic planes |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56160100A (en) * | 1980-05-13 | 1981-12-09 | Nippon Electric Co | Multilayer thick film circuit board |
JPS5957976A (en) * | 1982-09-27 | 1984-04-03 | 日本特殊陶業株式会社 | Metal film laminate ceramics |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2618258B1 (en) * | 1987-07-17 | 1990-01-05 | Suisse Electronique Microtech | IONIZING PARTICLE DETECTOR. |
-
1984
- 1984-04-05 JP JP6801084A patent/JPS60211897A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56160100A (en) * | 1980-05-13 | 1981-12-09 | Nippon Electric Co | Multilayer thick film circuit board |
JPS5957976A (en) * | 1982-09-27 | 1984-04-03 | 日本特殊陶業株式会社 | Metal film laminate ceramics |
Also Published As
Publication number | Publication date |
---|---|
JPS60211897A (en) | 1985-10-24 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EXPY | Cancellation because of completion of term |