JPH0137771B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is directed to a service processor (hereinafter referred to as SVP).
In a data processing device consisting of a main unit consisting of a plurality of processing units (PUs) equipped with a failure handling (RAS) circuit, the SVP diagnoses the processing units (PUs) of the main unit. This paper relates to a method for automatically generating test programs for

As modern data processing equipment is increasingly operated in real time, improved reliability is required, and SVP is required to exclusively control the operation and maintenance of the main equipment. The main device can be diagnosed by accessing the RAS circuit provided on the main device side from the SVP and having scan-in and scan-out functions.

FIG. 3 shows an example of the configuration of a data processing device equipped with the above RAS circuit.

In this figure, 1 is a main unit consisting of a plurality of processing units (PU) (for example, a central processing unit (CPU), a main memory (MEM), a channel device (CH), etc.), and 11 is each processing unit (PU). (PU)
2 is a service processor (SVP), 21 is a service processor link adapter (hereinafter referred to as SLA), and 22 is an SVP link, and all diagnostics from the SVP 2 to the main unit 1 are performed. , the SLA 21 and the SVP link 22.

The RAS circuit 11 provided in each processing unit (PU) on the main unit 1 side has a plurality of scan points, and a scan address is given to each scan point. Each point is divided into a plurality of scan groups.

Therefore, for example, based on instructions from SVP2,
If an error occurs when a specific value is scanned in to a specific scan point in each scan group through the SLA 21 and SVP link 22, the occurrence of the error causes the specific scan point to become "1". ” By the SVP recognizing this using the scan-out means, it is possible to diagnose the normality of a specific function (for example, an error detection circuit) of the processing unit (PU).

In a data processing device equipped with such a hardware mechanism, the RAS circuit 1 of the main device 1 is
1, SVP2 has SLA21, SVP link 2
2, generally, the hardware designer documents the test procedure for each processing unit (PU) of the main unit 1 in the form of a specification, and then performs the test procedure based on the documented specification. , the software person writes a program to access the scan points in each processing unit (PU) connected to the SVP link 22 using a dedicated programming language (called SDL language) and the SVP2 assembler language. The written program was translated into an object program that can be executed within SVP2 by computer processing, for example, and executed.

Therefore, until now, for example, in order to generate a test program in a language that can be translated by a computer, a hardware designer has to create the above specifications based on the hardware configuration of the main device 1.
Based on the specifications, SVP2 is SLA21, SVP
Through link 22, each processing unit (PU)
Since it had a two-stage structure in which a program that can access the RAS circuit 11 was created in a specific language that can be input into computer processing, if there was a hardware change on the main unit 1 side, the above test There are problems such as discrepancies between the procedure manual (specifications) and the above test program, and the need for a lot of man-hours to make corrections due to changes in the above hardware, so an effective test program generation method is awaited. It was

[Conventional technology]

Conventionally, a test program that accesses the fault handling circuit of a data processing device, that is, the RAS circuit, is
Hardware designers handwritten specifications and created test programs based on those specifications.

FIG. 4 schematically shows the above test program generation procedure.

In this figure, 1 is a main unit, 11 is a RAS circuit, 3 is a specification creation process, 4 is a coding process, and 5 is an assemble process for translating into machine language that can be executed by the SVP2.

FIG. 5 shows an example of a specification created in the above specification creation process 3. In this figure, is the test item number.

is a test item in the above test item number '2100', which indicates testing whether the mode error detection circuit of the channel device (CH) operates correctly.

is the initial setting condition necessary to test the mode error detection circuit of the channel device (CH) above, and registers A and B belonging to scan group 9.
This indicates that '1' is scanned into (1 bit).

indicates that only one clock is supplied to the processing unit (PU) in order to perform the above test.

is a confirmation process for the above test result, which scans out the register C (1 bit) belonging to the same group 9 as the scan group that performed the above scan-in, and if the value is '1', the mode error is detected. This indicates that the circuit is recognized to have operated correctly.

A test program is generated in accordance with the procedure shown in FIG. 4 based on the specifications in which test procedures are included.

First, the hardware designer 31 executes a specification creation process 3 to generate the above specification (test procedure manual). Next, the software designer (coder) 41, based on the contents of the specification,
The coding process 4 is executed using the SDL language or the SVP-compatible assembler language to generate a test program. Test programs in this case can be broadly classified into the following three types.

(1) Test data: The data values to be scanned in and scanned out, and the label specifications for the scanin, single clock start, and scanout programs (access procedures) necessary for the test operation, etc.
Written in the above assembler language.

(2) Access procedure: The access procedure specified by the label in the above test data, *scan-in operation, *single clock start operation, *scan-out operation, etc., is performed on main unit 1 through SVP2's SLA21 and SVP link 22. It is written in SDL language that allows direct access to the RAS circuit 11.

(3) Test procedure: Using the test data and access procedure, the test procedure indicated in the specification is written in the assembler language.

In this way, a test program coded in the SDL language or an assembler language suitable for SVP is translated into machine language that can actually be executed in the SVP 2 in the assemble processing 5, for example, by computer processing, and as an object program. Stored in the file memory of SVP2.

[Problem that the invention seeks to solve]

Therefore, in the conventional method, the specification creation process 3 and the coding process 4 are performed by different designers 31 and 41, respectively, so that if there is a design change on the main unit 1 side, the specification It is necessary to modify the specifications in the specification creation process 3, and to modify the test program in the coding process 4. As a result, the specifications and the test program may not match, or a lot of man-hours are required for the modification work. There was a problem that I needed it.

In view of the above-mentioned conventional drawbacks, the present invention describes the test procedure directly in a specification language (RAS language) using the same procedure as when a hardware designer documents a test procedure in the form of a specification. By automatically generating the above specifications and test programs using computer processing, for example, the man-hours required to create test programs can be reduced, and even if design changes occur, test procedures written in the RAS language can be easily used. The purpose of this invention is to provide a method for automatically generating new specifications and test programs simply by modifying them.

[Means for solving problems]

This purpose is based on the service processor (SVP) and
Multiple processing units (PU) with RAS circuitry
In a data processing device consisting of a main unit consisting of A dedicated specification language is provided to directly describe test procedures for diagnosis, and the service processor (SVP) uses this specification language to diagnose each processing unit (PU) of the main unit. The test procedure written in the above specification language is translated into a program that can be executed by a service processor (SVP), and assembled, and the above test procedure is edited into a specification in a specific format. This is achieved by the automatic test program generation method of the present invention, which prints out the test program.

[Effect]

That is, according to the present invention, in a data processing device consisting of a service processor (SVP) and a main unit constituted by a plurality of processing units (PUs) equipped with RAS circuits, SLA, SVP
Through the link, the hardware designer can write the test procedure for diagnosing the processing unit (PU) of the main unit mentioned above in a dedicated specification language (hereinafter referred to as RAS language) according to the procedure that they actually want to test. , Translate the written test procedure into a program that can actually be executed on the SVP, for example, by computer processing, and assemble it,
Since the test procedure is printed out in the form of a specification, the hardware designer can create a test program for the RAS circuit of each processing unit (PU) of the main unit using the RAS language, and It is possible to make changes,
By simply inputting the test procedure written in the RAS language into computer processing, for example, the specifications for the test procedure and the test program can be created at the same time, which has the effect of ensuring consistency between the specifications and the test program. .

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.
FIG. 1 schematically shows the process of automatically generating a test program by implementing the present invention, and the same symbols as in FIG. 4 indicate the same objects.
3', 6', and 7 indicate the processing necessary to carry out the present invention.

First, the RAS necessary to carry out the present invention
I will give an overview of the language.

The RAS language is the SVP link 2 explained in Figure 3.
The hardware designer specifies the functions that can be accessed through the SVP link 22 for the RAS circuit 11 of each processing unit (PU) of the main unit 1 connected to
It is a dedicated language that can be written directly in the same way as .

The main RAS languages are listed by code as follows.

(A) Declaration statement: PNO: Specifies program number, starts RAS language.

PEND: End of RAS language.

UTNO: Specify unit number, etc.

MSG: Message variable specification.

MSGC: Common message specification.

〓 (B) Comment text (omitted) (C) SCAN text: SCANIN: Scan flip-flop (FF)
Scan in to.

SCANOT: Compare the scanned out data with the expected value, and if there is a mismatch, branch to the specified label.

〓 (D) Condition setting statement (omitted) (E) Control statement: CLKSTP: Clock stop.

CLKSRT: Clock start.

SCLKSRT: Single clock start.

INTRST: Initial reset.

〓 (F) RAM-related statements (omitted) (G) Register-related statements (omitted) As is clear from the above explanation, the RAS language is RAS
It can be seen that the means for accessing circuit 11 is faithfully expressed in language at a level that is well understood by hardware designers.

Using the above RAS language to describe the test procedure shown in the specifications explained in Figure 5, we get:
It will look like Figure 2.

In this description example, "UTNO2100" declares the test item number '2100', and describes the one shown in Figure 5.

“*CH MODE ERROR1/3” is a comment text that explains the test content and describes the one in Figure 5.

declares that the diagnosis results will be printed out as a message, and “L1 MSGC CH
MODE ERROR” is a common message specification,
Indicates that the message is a diagnosis result of the channel (CH) mode error detection circuit, and “MSG
L1, 1/3" indicates the variable specification in the common message specified by the label 'L1' above, that is, the diagnosis result of the first bit of the channel mode error detection circuit consisting of 3 bits, The one in Figure 5 is described.

“SCANIN9, A, 1”, “SCANIN9, B,
1” are flip-flops (FF) indicated by nicknames A and B of scan group 9, respectively.
It shows that '1' is scanned in, and is described in Fig. 5.

“SCLKSRT” scans one clock to the corresponding processing unit (PU) after executing a scan-in.
This is an instruction to supply the same amount of water, and the one shown in Fig. 5 is described.

"SCANOT9, C, 1" indicates that the flip-flop (FF) indicated by the nickname C of scan group 9 is scanned out and compared with the expected value '1', and is described in FIG.

In this way, by using the RAS language, which is the key point of the present invention, a hardware designer can write a test procedure manual (specification document) by hand in the same way as the test procedure manual (specification document) shown in FIG. It is characterized by being able to describe.

Written (coded) in this way
This shows the process of translating a test procedure in the RAS language into a program that can actually be executed by SVP2 through computer processing, assembling it, editing the test procedure into a specification in a specific format, and printing it out. However, 5 in Figure 1
This is the process shown in 7.

First, coding process 3' using RAS language
Then, when the test procedure in the RAS language explained in FIG. , In the translation process 7, the test procedure in the hardware language is translated into the SDL language or the assembler language suitable for SVP.

The test procedure translated into SDL language or assembler language is performed in assemble processing 5.
It is translated into machine language that can actually be executed by SVP2.

In this way, in the present invention, hardware designers can write test procedures (i.e., code code) using the RAS language in the same way that they traditionally wrote test procedure manuals (i.e., specifications) by hand. The feature is that a specification in a specific format and an object program for a test program are automatically generated by a series of translation processes, for example, by a computer.

〔Effect of the invention〕

As explained above in detail, the test program automatic generation method of the present invention is a data processing system consisting of a service processor (SVP) and a main unit consisting of a plurality of processing units (PUs) equipped with RAS circuits. In the processing device, from the SVP to SLA, SVP
Through the link, the hardware designer can write the test procedure for diagnosing the processing unit (PU) of the main unit mentioned above in the dedicated RAS language according to the procedure they actually want to test, and then write the written test procedure. , for example, by computer processing, the above can actually be achieved.
The test procedure is translated and assembled into a program that can be executed by SVP, and the test procedure is printed out in a specification format, so that the hardware designer can use the RAS language mentioned above to program each process of the main unit. It is now possible to create and change test programs for the RAS circuit of the unit (PU), and by simply inputting the test procedure written in the RAS language into a computer, the specifications for the test procedure and the test program can be created at the same time. This has the effect of ensuring consistency between the specifications and the test program.

[Brief explanation of drawings]

FIG. 1 is a diagram schematically showing the process of automatically generating a test program by implementing the present invention.
Figure 2 is a diagram showing an example of a test procedure written in the RAS language, Figure 3 is a block diagram showing the outline of the configuration of a data processing device equipped with RAS functions,
FIG. 4 is a diagram schematically showing the process of generating a test program using the conventional method, and FIG. 5 is a diagram showing an example of a handwritten specification. In the drawing, 1 indicates the main unit (CPU, MEM,
CH,...), 11 is a RAS circuit, 2 is a service processor (SVP), 21 is a service processor link adapter (SLA), 22 is an SVP link, 3 is a specification creation process, 3' is coding in the RAS language 4 is a coding process, 5 is an assembling process, 6 is a specification printout process, 7 is a translation process, .about. is a test procedure creation process by handwriting or coding process, respectively.

Claims (1)

[Claims] 1 In a data processing device consisting of a service processor (SVP) and a main unit consisting of a plurality of processing units (PUs) equipped with RAS circuits, , we have created a dedicated specification language to directly describe test procedures for diagnosing the processing units (PUs) that make up the main unit, through the service processor link adapter (SLA).
Using the specification language, write a test procedure for diagnosing each processing unit (PU) of the main unit from the service processor (SVP), and then write the test procedure using the written specification language to the service processor. A test program automatic generation method characterized in that the test program is translated and assembled into a program that can be executed by Setsa (SVP), and the test procedure is edited into a specification in a specific format and printed out.