JPH0137732B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a copying machine, and more particularly to a control device for a copying machine equipped with a processor unit.

Prior Art With the advent of faster and more complex copiers,
The control logic for copiers has become sophisticated and complex.
In order to cope with this problem, copying machines have been controlled using processors (see Japanese Patent Application Laid-open No. 42542/1983). Such copying machines can be easily modified or changed by changing the program.
It is convenient because it can be combined with other devices relatively easily.

Problems to be Solved by the Invention However, the control data stored in the memory of the controller that operates the above-mentioned copying machine is transmitted to various copying processing devices at appropriate times and in the correct order. It must be.
Otherwise, it may be interfered with or interfered with by other functions and operations of the control device.
Additionally, in large, high-speed copying machines, noise is generated from the triax and silicon rectifier elements used to energize the motor and clutch, and this noise mixes into other motors, clutches, and switches, causing them to malfunction. However, the results were sometimes sent to the processor unit, causing the copying machine to malfunction. From a hardware perspective, eliminating this noise requires installing expensive noise suppression circuitry at the noise source. Therefore, there is a drawback that the price of the entire copying machine also increases.

For this reason, the inventor tried to see if it was possible to suppress this noise from the perspective of software. In other words, should we use a program to suppress noise signals from entering the processor unit, remove noise signals that have entered the processor unit using a program, or update the noise signals that have entered the processor unit with correct data? I tried. However, although it is possible to suppress the intrusion of noise signals and remove the intruded noise signals from a hardware perspective, it is difficult to solve the problem using software.

By the way, general commercially available microprocessors are capable of updating, or refreshing, the control data of a copy processing device with correct control data at a sufficiently high frequency, or in a short period of time, to eliminate the effects of erroneous signals. It was not responsive enough. For this reason, it is difficult to update or refresh the intruding noise signal with correct control data.

In view of this, it is an object of the present invention to provide noise countermeasures from a software perspective without requiring expensive circuits even in copying machines that are equipped with a programmable processor and perform high-speed, complex control. The purpose of this invention is to provide a copying machine that takes the following measures.

Means for Solving the Problems To achieve this objective, according to the present invention,
A plurality of selectively energized copy processing devices are adapted to operate together with each other and with a photosensitive member to electrostatically produce copies on a support for various types of copying operations. The controller includes a control console for setting a clock pulse, a clock pulse generating means, and a controller with a memory for operating the processing device, and the controller uses control data from the memory to perform a predetermined processing operation in a timing sequence according to a set specific copying operation. In the copying machine, the controller is provided with at least a processor unit, an interrupt means, a direct memory access means, and a refresh means, and the interrupt means is connected to the clock pulse generating means. The clock pulse generating means generates at least a first clock pulse for synchronization necessary for the operation of each processing device of the copying machine, and a second clock pulse generated in synchronization at an interval corresponding to one copying operation. The interrupt means generates two clock pulses, and the interrupt means sends interrupt signals with different priorities to the processor unit according to the first and second clock pulses to interrupt the processor unit. The direct memory access means and the refresh means are controlled, the direct memory access means cooperating with the refresh means to directly and independently of the control of the processor unit control data for the copying process from the memory. There is provided a copying machine characterized in that when the control data is directly transferred, the interrupt means interrupts the operation of the processor unit, and resumes the operation when the transfer is completed.

Summary of Operation of the Invention An important feature of the present invention is that the controller (control device) is provided with not only a processor unit, but also an interrupt means, a direct memory access means, and a refresh means, and these are organically linked. Another reason is that we are taking measures against noise from a software perspective. Hereinafter, it will be briefly explained that the configuration of the present invention allows refreshing with correct control data even if a noise signal enters the control data of the copying machine.

In the copying machine of the automatic copying system according to the present invention,
A plurality of selectively energized copying processing devices (e.g., input device, sorter, original image handling device, developing device, transfer device, fixing device, etc.) are provided in association with the photosensitive member. The copiers are capable of performing various types of copying operations, and are designed to statically and dynamically produce copies by interacting with each other to form an image on a photosensitive member and transferring the image to a support. A control console is provided for setting, and the number of copies, paper size, etc. are set on this control console, and copying is started by pressing a button.
The copying machine is also provided with a clock pulse generating means for creating the operation timing necessary for the copying machine's work, and a controller such as a microprocessor for operating the copy processing device. The controller is provided with a random access memory (RAM) for storing control data, etc., and the controller activates devices for predetermined processing in a predetermined timing order to perform a specific copying operation selected by the control console. Make a given copy.

Generally, in a controller using a microprocessor, in order to exchange control data or general data, the data is first input/output from an input/output processing device to a memory via the processor. Therefore,
The above data is exchanged along the flow of the program being executed. For this reason, it is difficult for a low-speed computer such as a microprocessor to update or refresh the data with correct data so as to remove the noise signal in a short period of time when a noise signal enters the computer.

In the present invention, the controller is provided with a CPU module serving as a processor unit,
This module is equipped with RAM as memory. The controller also includes an interrupt means to interrupt the work currently being executed,
Refreshing means for updating or refreshing the storage means (shift register 740, etc. to be described later) of the copy processing device with various data from the RAM, and direct memory access for directly transferring data between the RAM and the processing device. (DMA) means are provided. An address bus, a data bus, and a control bus are connected between the CPU module, the copy processing device, and the RAM, and not only addresses and information but also control data are stored in the copy processing device's storage means. sent to.

The interrupt means is inputted with a first clock pulse for synchronization necessary for the operation of the copy processing device and a second clock pulse generated in synchronization with an interval corresponding to one copy operation. is the CPU as a processor unit.
Interrupt the module by sending an interrupt signal with a different priority. In the present invention, this interrupt signal interrupts the copying operation in progress and causes a predetermined operation, that is, a refresh operation, to be performed, thereby enabling a direct memory access operation.

The direct memory access means receives the signal HOLD from the refresh means and transfers the control data directly from the RAM memory to the storage means of the copy processing device independently of the control of the processor unit, thereby updating the control data. (refresh). In order to prevent this transfer from interfering with a good copying operation, the direct memory access means and the refresh means are controlled by an interrupt means, which interrupts the processor unit during direct transfer of control data. The operation of the processor unit is interrupted and the operation of the processor unit is resumed when the transfer is completed.

Therefore, even if an abnormal noise that changes the copying state occurs, the storage means in the copying device is refreshed at short intervals and the correct control data is stored before any movement occurs in the motor or switch. Since the data is sent to each copy processing device, even if the data is changed due to abnormal noise, the state can be immediately returned to the correct state.

By doing so, the control data of the copy processing device can be refreshed with the correct control data at a frequency sufficiently high to eliminate the effects of erroneous signals, i.e., at a short enough time. Even if the microprocessor does not have a fast response, the present invention can temporarily control the microprocessor by organically combining the refresh means, the interrupt means, and the direct memory access means. While suspending (holding) the contents of the control data memory, the contents of the control data memory are quickly sent to the copy processing device in a short time, for example within 30 microseconds, achieving high-speed response.

Embodiment FIGS. 1 to 3 schematically show an automatic copying system 10 according to the present invention. Automatic copying system 10
The apparatus includes an electrostatographic copying machine 12, a sorter 14, an original handling device 16, and a controller 18. First, the configuration and operation of the copying machine 12 will be explained.

Copying Machine Copying machine 12 uses an endless photoreceptor belt 20 supported in a triangular configuration by rolls 21, 22, and 23. belt support roll 21,
22 and 23 are rotatably supported on a subframe 24. Belt travel switch 25 (second
(Figure) monitors belt misalignment from the side.

The copying machine 12 includes a transparent platen 35 on which the original image 2 to be copied is placed. Internal reflector 36
An illumination device consisting of a flash lamp 37 (FIG. 2) and a flash lamp 37 (FIG. 2) is located below at least two sides of the platen 35. A vacuum pump 38 and conduit 38 are provided to draw heated air upwardly from the lighting space to control the temperature within the lighting space.

The light image generated by the illumination device is transmitted to the mirror 3
9 and 40 and the variable magnifying lens assembly 11, the image is projected onto the photoreceptor belt 20 of the exposure section 27. A push button 81 on the control console 800 is equipped with a main drive reversible motor 43 to move the lens.
8,819,820. (See Figure 32). sensor 11
6, 117, 118 signal the current position of the lens device 41.

Referring to FIGS. 1, 6, and 7, a magnetic brush roll 50 is provided within the developing line housing 51 of the developer section 28. As shown in FIGS. The housing 51 is equipped with an interlock switch 52 to detect the position of the housing 51. To control the development of the electrostatic latent image on belt 20, magnetic brush sleeve 55 is electrically biased. A power supply 60 is provided for this bias, and the amount of bias is adjusted by controller 18.

The developer returns to the top of the developer housing 51 for reuse, and it is connected to a photocell 62 and lamp 6 that monitor the level of developer within the housing 51.
This is achieved by using 2'. The copier disclosed herein maintains an optimum toner to carrier ratio by sensing toner concentration and replenishing toner. As shown in FIG. 8, a pair of transparent plates 64 are installed in the developer housing 51 in parallel with a space between them, through which the developer returns. Appropriate circuit (not shown)
The plate 64 is charged and attracts the toner. The photocell 65 on one side of the plate pair is
Detects when developer passes between them. The photocell 65 monitors the concentration of the returning developer and the concentration signal output is used by the controller 18 to
The amount of freshly formulated toner added to developer housing 51 from toner supply container 67 is controlled.

A rotatable distribution roll 68 is provided within the entrance of the developer housing for discharging toner from the container 67. A motor 69 drives the roll 63. When new toner is required, a signal from photocell 65 causes controller 18 to activate motor 69 to rotate roll 18 for a period of time.

Referring to FIGS. 4, 9, and 12, a transfer roll 75 is provided to transfer the developed image from the belt 20 to the copy paper 3. A suitable electrical bias is applied to transfer roll 75 to facilitate transfer of the developed image from belt 20 to copy paper 3.

A deflector 96 is provided upstream of the cleaning brush 85 to prevent the risk of copy paper remaining on the belt 20 and the belt cleaning mechanism. A deflector 96, which is pivotally mounted on the brush housing 86, is operated by a solenoid 97. In the normal off position, the deflector 9
6 is separated from the belt 20 (solid line position shown). By energizing the solenoid 97, the deflector 96 is rotated downward to bring the tip of the deflector close to the belt 20.

Sensors 98 and 99 are provided on each side of deflector 96 for sensing the presence of copy paper on belt 20. The signal output from upstream sensor 98 triggers solenoid 97 to
Deflector 96 is placed at a position that blocks the copy paper above 0.
Rotate. The signal from sensor 98 is also
Initiates a stop cycle (paper jam due to mis-separation) in which the various operating components are stopped within the aforementioned period of time. During this period, the copy paper present in the thermal fuser 150 is removed, and the copy paper trap solenoid 158 prevents the next copy paper from entering or becoming stuck in the fuser 150. It works like this. A signal from sensor 99 indicating a failure of deflector 96 for removing copy paper from belt 20 immediately causes copier 12 to stop (jam). Power to drive motor 34 is cut off to immediately stop belt 20 and other components.

With particular reference to FIGS. 1 and 12, copy paper 3 is supplied from either a main copy paper tray 100 or an auxiliary copy paper tray 102. Each copy paper tray has a platform 103 that supports a quantity of paper in a stack. The tray base 103 moves up and down as the motors 105 and 106 operate. Pairs of side guides 107 within each tray 100, 102 define the tray side boundaries and are adjustable to move toward and away from each other when accommodating different sizes of paper. Sensors 108 and 109 output signals of the position of each pair of side guides 107 to regulate the operation of fade-out lamp 45 and fuser cooler 171. A lower limit switch 110 on each tray prevents downward overtravel of the tray platform.

A main paper feed device 120 and an auxiliary paper feed device 121 are provided to advance paper 3 from either tray 100 or 102. feeding device 120,
Each of 121 includes a feed roll 123 that engages and advances the frontmost paper within the gap formed by a feed belt 124 and a drawer roll 125. A pull roll 125, driven at a very low speed by a motor 126, cooperates with the feed belt 124 to limit paper feed from the trays 100, 102 to one sheet at a time.

The feed belt 124 is driven by a main paper feed motor 127 and an auxiliary paper feed motor 128, respectively. The roll 123 is pivotally mounted around the axis of a feed belt drive shaft 129 and is driven from the drive shaft 129. Stack height sensors 133, 134 are provided for the main tray and roll 123 serves to operate the sensors 133, 134 in response to copy sheet stack height. Misfeed sensors 135, 136 are provided at the tray outlet.

A main transport system 140 extends from the main copy paper tray 100 to a point slightly upstream from the gap formed by the photoconductive belt 20 and transfer roll 75. The transport device 140 is driven by the main motor 34. In order to register the image developed on the belt 20 to the paper 3, a registration finger 141 is provided and is arranged to move out in the paper path on the transport device 140 once per revolution. The alignment finger 141 is driven from the main motor 34 via an electromagnetic clutch 145. A tight reset switch 146 as a timing switch is set once for each rotation of the alignment finger 141. Sensor 139 monitors jams in transport device 140 .

The copy sheet leaving the gap formed by photoreceptor belt 20 and transfer roll 75 is stripped off by belt 155 at the tip of vacuum conveyance device 149 . This belt has holes for creating a vacuum, and is supported on a front roller pair 148 and a rear roll 153. A pair of vacuum chambers 15
1,154 is formed, and the front vacuum chamber 154 cooperates with the belt 155 to create a space between the belt and the transfer roll.
Pick up the paper as it leaves. Vacuum tube 147, 156
connects the vacuum pump 152 and the spaces 151 and 154. Pressure sensor 157 is vacuum pump 152
monitor operations. The sensor 144 is the transport device 1
Monitor 49 jams.

A trap solenoid 158 prevents paper on the transport 149 from being carried into the fuser 150 in the event of a jam or other failure.
provided below. By energizing solenoid 158, the paper is intercepted and stopped.

A paper stop 190 is provided adjacent the output end of the chute 186 for inverting the second side, or duplex copy sheet. The stop 190 is the chute 186
It is pivoted so that it can swing in and out. Solenoid 191 is for moving stop 190 into or out of chute 186. Pitch roll pairs 192, 193 act to pull out paper stuck in chute 186 by stop 190.

Output tray 195 receives the copies in undivided form. A conveying device 196, a portion of which is wound around a rotating roll 197, transports the copy paper into a tray 19.
Carry it to 5. Sensor 194 monitors jams in transport device 196. A deflector 198 is provided to advance the copy paper into output tray 195. When solenoid 199 is energized, deflector 198 intercepts the paper on conveyor 181 and advances the paper onto conveyor 196. When sorting copies, output tray 195 is not used and the copy sheets are conveyed to sorter 14 by conveyor 181.

Sorter Referring to FIG. 13, the sorter 14 is comprised of an upper shelf 210 and a lower shelf 211. Each shelf 210, 210 comprises a series of spaced, downwardly sloping trays 212 forming a series of individual shelves 213 for receiving copy sheets 3'.
A conveyor 214 at the top of each shelf cooperates with an idler roll 215 adjacent the entrance to each shelf to convey copy paper. Individual deflectors 216 on each shelf cooperate with idler rolls 215 when depressed to rotate the copy paper into each shelf. Operation solenoid 2
17 activates each deflector 216.

Optical sensors 225, 226 are provided at one end of the shelves 210, 211, respectively, to detect the entry of copy sheets 3' into the respective shelves 213. Sensor lamps 225', 226' are located adjacent to the other end. To detect the presence of copy paper in bin 213, a second set of optical sensors 227, 228 is provided for each shelf arrangement at the same level as tray remover 229. Reference lamp 2
27', 228' are placed opposite the sensors 227, 228.

Original Picture Handling Device Referring to FIGS. 14 and 15, the original picture handling device 16 is provided with a tray 233, and the original picture
is placed therein by the operator, and then the cover (not shown) is closed. A separator 235, driven into the passageway by a motor 236 through a solenoid operated rotary clutch 238, separates the originals. The original image feeding belt 239 has a drive roll 240, an idle roll 214, and a tray 233.
It is supported by the lower roll 242. Tray 233 has holes drilled into it to allow the belt surface to protrude. The feed belt 239 is driven by a motor 236 via an electromagnetic clutch 244. A guide 245 disposed near the discharge end of the feed belt 239 cooperates with the belt 239 to form a gap through which the original image passes.

An optical sensor 246 is positioned adjacent the discharge end of belt 236. Sensor 246 actuates clutch 248 in response to a failure to advance the original within a predetermined period of time to raise roll 242 and increase the contact area of feed belt 239 in contact with the original.

The original image guide 250 advances the original image from the tray 233 to the platen 35 via a pair of rolls 251 and 252. Roll 251 is driven by motor 236 via electromagnetic clutch 244. roll 2
51 causes the roll 252 to also rotate.

Rolls 260, 261 at the inlet of platen 35 advance the original onto platen 35. Roll 260 is driven forward through electromagnetic clutch 262.
The roll 261 is rotated in the original image feeding direction by contact with the roll 260. Roll 260 is connected to motor 236 and electromagnetic clutch 26 through gear 268.
5, and engagement and disengagement of clutch 265 causes roll 260 and roll 26
1 rotates in the opposite direction and carries the original picture to the tray 233. One-way clutches 266, 267 allow the roll drive shaft to rotate freely.

The original leaving roll pair 260, 261 is supported on platen 35 by platen transport belt 270, and belt 270 is comprised of a suitable flexible material with a white exterior surface. The belt 270 is supported by a drive roll 271 and an idler roll 272. The roll 271 is connected to the clutches 262 and 265.
is driven by a motor 236 to rotate in either a forward or reverse direction through. Engagement of clutch 262 drives belt in a forward direction through belt and pulley drive 279, and engagement of clutch 265 drives belt 270 in a reverse direction through drive 279.

To place the original in position on the platen 35, an alignment member 273 is provided at the platen entrance to engage the rear edge of the original. Platen belt 2
70, the original image is sent onto the platen 35, is conveyed past the alignment member 273, and then transferred to the belt 27.
0 is reversed to press the original against the alignment member 273.

After copying, registration member 273 is retracted to the inactive position to remove the original from platen 35. A solenoid 274 is provided to move alignment member 273.

Original image deflector 275 advances original images leaving platen 35 into return chute 276 . Platen belt 270 and pinch roll pair 260, 26
1 is reversed by engagement of clutch 265. Discharge roll pair 27 driven by motor 236
8 carries the original picture to be restored into the tray 233. Optical sensors 246, 280, 281, 282 are positioned along the original path to monitor movement of the original within the original handling device 16 and to detect jams and other failures. In order to align the original images 2 returning to the tray 233, an original image putter 284 is provided adjacent to one end of the tray 233. A putter 284 is vibrated by a motor 285.

Clock Pulse Generator To synchronize the necessary operations between the copier 12 and the controller 18, a mechanical clock 202 is provided which generates a clock pulse as a first clock pulse. With particular reference to FIG. 1, clocking device 202 is comprised of a toothed disk 203 supported on and driven by the output shaft of main drive motor 34. As shown in FIG. An optical clock pulse signal generator 204 is disposed along the teeth of the disk 203, and the clock pulse signal generator 204 generates a pulsed signal at a frequency related to the speed of the motor 34 whenever the drive motor 34 operates. It generates a signal output and generates a first clock pulse for synchronization necessary for the operation of each processing unit of the copying machine.

In this embodiment, the tight reset clock device 13
A second clock pulse generator, designated 8, is provided which includes a timing switch 146. Switch 146 cooperates with paper registration finger 141 to generate an output pulse once per rotation of finger 141. This resets the pulse controller 18 of the tight reset clock.
These are pulses at intervals corresponding to one copying operation, and are used to synchronize the operations of each processing device.

Referring to FIG. 15, an original image handling device clock pulse generator 286 is also provided which comprises a disk 287 on the output shaft of the original image handling device drive motor 236 and an optical signal generator 288.

In addition to the above-mentioned clocks, real-time clocks are also generated, as described below.

Controller Referring to FIG. 16, the controller 18 is
Computer processor unit (CPU) module 500, input/output (I/O) module 50
2, and CPU interface module 50
Contains 4. An address bus 507, a data bus 508, and a control bus 509 are connected to each CPU.
The module 500 and I/O module 502 are communicated. The CPU module 500 and I/O module 502 are shielded 5 to prevent noise interference.
18.

The interface module 504 includes an I/O module 502, a special circuit module 522,
It communicates with an input matrix module 524 and a main panel interface module 526. Module 504 is also I/O module 5
02 is connected to original handling device 530, input 532, sorter 534, and processing devices 536 and 538. A spare portion 504 is provided that can be used to monitor the operation of the copier or to control other equipment.

Referring to FIGS. 17, 18a, and 18b, the CPU module 500 includes a microprocessor 542, a 16K byte read-only memory (ROM) 545, a 2K byte random access memory (RAM) 546, memory lady 54
8, a power regulator 550, and a CPU clock 552. As shown in Figure 18a,
A buffer 510 in the address bus 507 and a buffer 511 in the data bus 508 disable each bus for the microprocessor 542 and suspend processor operation when there is a direct memory access (DAM) signal (HOLD A). let

Referring to FIG. 19, CPU clock 552
This clock 552 is a clock for operating the microprocessor 542, and includes the mechanical clock as the first clock, the reset clock as the second clock, and other clocks ( (original handling device clock and real-time clock). The width of the clock pulses of CPU clock 552, which operate microprocessor 542, is considerably shorter than the mechanical clock. This clock 552 is
A multi-bit (Q _A to Q _N ) shift register 554 and a clock oscillator 553 that sends pulses to this register.
It consists of Shift register 554 outputs four clock signal outputs φ ₁ , φ ₂ , φ _1-1 and φ _2-1 of different phases for operation of microprocessor 542 .

Referring to FIG. 20, data in ROM 545 is addressed by address signals A0 to A15 sent from processor 542 via address bus 507, and selection is made when the output of decoder 560 is input to chip select terminal CS-1. This is done by Address A13 controls chip select CS-2. Most significant address bits A14 and A15 select the first 16K of a total of 64K bytes of address space.

The data in the RAM 564 is transferred to addresses A0 to A from the address bus 507 by the selector circuit 561.
15. Address A10 selects the memory bank, and the five highest addresses A11
-A15 selects the last 2K bytes of the 64K bytes of address space. RAM 546 includes a 40-bit output buffer whose output is coupled with the output from ROM memory 545 and buffer 562 for driving data bus 508.
sent to. Either memory 545 or 546 is addressed and read MEM READ or
If any DAM request HOLD A is present, buffer 562 is enabled. The enable signal MEMEN is issued by the controller and also by a repair panel (not shown). Write control is performed using a signal from the processor (MAM
WRITE) or DMA (HOLD A) control. Buffer 563 is I/O module 50
The refresh control device 605 of the processor 5
When receiving the DMA signal (HOLD A) from 42, the MEM READ and MEM WRITE control channels can be accessed directly.

Details of the memory ready 548 shown in FIG. 17 are shown in FIG. 21, and with reference to this FIG. SYNC signal φ ₁ so that the count determined by input circuit 567
Counter 566, which is started by , counts at a predetermined speed. When the count reaches the maximum, an output "1" is output to the gate 568 and the counter 566 is stopped. If this cycle is a memory request (MEM REQ) and the memory location is onboard determined by the signal to buffer 569 (MEM HERE), then REDAY
A signal is sent to processor 42. MEM REQ
The line buffer 570 is the I/O module 5
The refresh control device 605 of No. 02 receives the DMA signal (HOLD A) from the processor 542 and enables direct access to the MEM REQ channel.

Power regulator 55 in Figures 22a-22c
0,551,552 are the various DC voltages required by module 500, i.e. +
Generates 5V, +12V, -5V. Power abnormality (PNN)
A detection circuit 571 is provided to reset processor 542 during the power up process. A reset from the repair panel for service personnel is supplied via this PNN detection circuit. In addition,
An enable signal (INHIBIT RESET) from memory control circuit 638 completes the write cycle of non-volatile (NV) memory 610 of I/O module 502.

With reference to Figures 18a, 20, and 21 and the DMA timing chart (Figure 18b), the RAM 54
6 to system 10 is accomplished by direct memory access (DMA). Signal HOLD to start DMA
is produced by the refresh control device 605 (FIG. 23b). Upon receiving the HOLD signal, processor 542 generates an acknowledge signal HOLD A, which is transmitted to buffers 510 and 511.
(Figure 18a) and buffer 563 (Figure 20)
and buffer 570 (FIG. 21), the address bus 507 and data bus 508 are released, and the memory read and write operations to the refresh control device 605 of the I/O module 502 (FIG. 20) and MEM REQ ( 21) and interrupts the operation of the processor.

Details of the I/O module 502 shown in FIG. 16 are shown in FIGS. 23a and 23b. First, in FIG.
is connected to the CPU module 500 through an address bus 507, a data bus 508, and a control bus 509, and also functions as a memory for the CPU module 500. Note that data transmission between the CPU module 500 and the I/O module 502 and commands to the I/O module 502 (excluding refresh output signals) are controlled by memory reference instructions executed by the CPU module 500. Ru. The refresh output is
Initiated by one of several specific memory reference instructions, this refresh output signal
I/O module 502 enables direct memory access (DMA) operations to RAM 546.

Referring to Figures 23a and 23b, I/
The O module 502 has a matrix input select 604 that receives data from an input matrix module 524 and a refresh controller 6.
04, a non-volatile (NV) memory 610, an interrupt control device 612, a supervisory timer and failure flag generator 614, and a function decode/ready section 601. and,
The I/O module 502 is provided with an I/O clock 670 as an operating clock.

The function decode and ready part 601 is
It receives and decodes commands from the CPU module 500. This decoding is performed on address bus 50 along with control signals from processor 542 on control bus 509.
This is done by discontinuing the information on 7. Upon receiving a command, decode portion 601 generates control signals to perform the instructed function. These functions include the functions shown in (a) to (i) below.

(a) Controlling buffer 620 to determine the direction of data flow on data bus 508.

(b) Buffer alarm 622 from data bus 508
strobe (a gate operation to synchronize multiple pieces of data) the data input to the

(c) Data from the interrupt control device 612 (D ₀ to D ₇ ), data from the real-time clock register 621 (RT clock data), data from the matrix input selector 604 (input matrix data), and non-volatile memory 610
multiplexer 624 to transfer data (NV memory data) from NV memory to data bus 508.
to control.

(d) Activating refresh control 605 to initiate DMA operations.

(e) Activating buffer 634 to enable address bits A0-A7 to be sent to system 10 to enable input matrix read operations.

(f) Instructing the matrix input selector 604 to operate.

(g) initiating a read or write operation of non-volatile memory 610 via memory control 638;

(h) Loading data from data bus 508 into real-time clock register 621 (Figure 23a).

(i) Resetting the monitoring timer of the monitoring timer/fault flag 614 and setting the fault flag.

Furthermore, function decoding and ready 601
includes logic to control and synchronize the READY control line to the CPU module 500, and the READY control line to the I/O module 500.
If the data on the data bus by 02 is valid, it is used by CPU module 500.

Monitoring timer and fault flag device 614 for detecting hardware and software faults
is a self-running counter, which is normally reset periodically by a refresh output command (REFRESH) from the function decode/ready section 601. If the refresh output is not received within a predetermined period (i.e. 25msec),
A fault flip-flop is set and a signal (fault) is sent to system 10. Signal (failure)
also disables the CPU module 500 via the HOLD line. Resetting a faulty flip-flop can be accomplished by generating a signal (RESET). Selector (not shown)
may be provided for disabling the monitoring timer. CPU failure flip-flop
It may be set by command from the module to indicate that the operating program has detected a fault.

Matrix input select 604 has the capacity to read up to 32 groups of eight inputs from system 10. Lines A ₃ to _{A 7} of the address bus 507 are connected to an optical isolator 569 such as a photocoupler.
It is sent to system 10 via CPU interface module 504 to select the desired group of eight inputs. Inputs selected by system 10 are received via input matrix module 524 (Figures 16 and 29), routed on data bus 508 by matrix input select 604 (Figure 23b), and It is sent to the CPU module 500 via multiplexer 624. Bit selection is done using the address bus 507 line.
This is achieved by A ₀ to A ₂ .

When a refresh signal (REFRESH) is output from the function decode/ready section 601 in response to an interrupt signal (described later), the refresh control device 605 starts to output 16 sequential word data or 32 sequential word data from the output buffer 562 of the RAM memory 546. Word data is transmitted directly to system 10 on line 574 at a predetermined clock rate. That is, it performs a direct memory access (DMA) operation. This Direct Memory Access (DMA)
is used for high-speed data transmission, and
Refresh controller 605 generates a HOLD signal to microprocessor 542 (see Figures 17 and 18a). When the HOLD signal is received and acknowledged, a signal HOLD A is generated as an acknowledgment, and this signal HOLD A causes the processor 542 to
enters a hold or suspend state. In this suspended state, via the buffers 510 and 511,
Address bus 507 to CPU module 500
and data bus 507 are placed in a high impedance state, while I/O module 502 (23a,
In Figure b), 16 or 32 word data is sequentially called out by the address data from the refresh address, and the data bus 508 and isolator 569
via CPU interface module 50
4 directly sends the data to system 10.
The contents will be transmitted to. CPU module 500
is suspended during this period.

By restricting data from address bus 507 and data bus 508 from being sent to CPU module 500, control signal LOAD on line 607 at a predetermined clock rate determined by the clock signal (CLOCK) on line 574 is activated. ,
It is used to generate eight 16- or 32-bit sequential words that are sequentially communicated via CPU interface module 504 to a predetermined location in system 10 where the serial-to-parallel exchange is performed. Alternatively, this data may be stored in addressable latches and distributed directly in parallel to the required destinations.

Non-volatile memory 610 contains a predetermined number of bits that are stored within I/O module 502 under the control of memory control 638. This non-volatile memory 610 is the CPU module 50
It is used as part of the 0 replenishment memory and can be called by a CPU memory reference instruction. With particular reference to FIG. 24, a rechargeable battery 635 is installed on the I/O to maintain the contents of non-volatile memory 610 when power is interrupted.
It is provided outside the module 502.
A CMOS protection circuit 636 couples the battery 635 to the memory 610 so that the memory 61
Protect 0. The signal INHIBIT RESET is used to prevent CPU module 500 from being reset during non-volatile memory write cycles.
Write operations in progress are completed before the device is stopped.

A multiple interrupt system is provided for tasks requiring frequent maintenance, fast response to external events, or synchronization with the operation of the main machine 10. These interrupts consist of three interrupts, referred to herein as the pitch reset interrupt, the machine clock interrupt, and the original handler interrupt, and a fourth interrupt, the real time clock interrupt.

With particular reference to FIGS. 23a and 36, the highest priority interrupt signal, or spot reset signal 640, is generated by the signal output of spot reset clock generator 138 (FIG. 1). The clock signal is optical isolator 6
45 and digital filter 646 (No. 23a
(Fig.) to an edge trigger flip-flop 647.

A second priority interrupt signal, mechanical clock signal 641, is sent directly from mechanical clock generator 202 through transformer 648 to phase lock loop 649. Loop 649 serves as a bandpass filter and signal conditioner
sends a square wave signal to flip-flop 651.
The second signal output (LOCK) serves to indicate whether loop 649 is locked on the valid signal input.

Interrupt signal with third priority, that is, original image handling device clock signal 642
is sent directly from original handler clock 286 to flip-flop 654 via transformer 652 and phase lock loop 653. Signal (LOCK)
serves to indicate the validity of the signal input to loop 653.

An interrupt signal or real-time clock signal 643 having the lowest priority is generated by register 621. CPU module 50
The register 621 that is loaded and stored by the memory reference instruction from
The count is decremented by the clock signal within. When the register count reaches zero, register 621 sends an interrupt signal to flip-flop 656.

Interrupt signal 640, 641, 642, 6
43 causes flip-flops 647, 651, 6
54,656 is set, a signal INT is generated to the processor 542 of the CPU module 500 through the priority chip 659. As an acknowledgment of this signal INT, the signal INT A
is sent from microprocessor 542 to set the states of flip-flops 647, 651, 654, and 656 in 4-bit latch 660 and generate an interrupt instruction code RESTART on data bus 508.

Each interrupt is assigned a unique RESTART instruction code. When a high priority interrupt is triggered, a new interrupt signal (INT) and RESTART instruction code are generated, and when the interrupt recognition circuitry is enabled within the CPU 500, nesting of the interrupt software routine occurs.

Priority chip 659 serves to prioritize the case of simultaneous interrupt signals according to the priority schedule described above. In addition,
The priority of the above-mentioned interrupts is not limited to the above-mentioned order.

When triggered, flip-flop 6
47, 651, 654, or 656 must be reset to catch the next occurrence of the interrupt associated with it. In addition to performing its programmed functions, each interrupt subroutine resets the flip-flop (through writing an encoded byte in a singly selected address) and interrupts (through execution of a rejoin instruction). help make it possible again. Initiation of the second interrupt is excluded while the first interrupt proceeds until it is re-enabled.

Line 658 is a memory reference instruction.
The CPU module 500 inquires about the interrupt status. I/O module 502 (No. 23a,
A suitable pulse generator or clock 670 is provided in FIG. b) to generate the various timing signals required. This clock 6
70 is driven by the pulsed outputs φ ₁ and φ ₂ of the processing CPU clock 552 (FIG. 17).
(See also figure 9a). As mentioned above, clock 670
generates a reference clock pulse on line 574 to synchronize new output data and is the source of clock pulses for driving real-time register 621 (line 623).

The CPU interface module 504 (FIG. 26) connects the system 10 and the I/O module 50.
2 (see FIG. 16) to transmit data stored in RAM 546 to system 10. With particular reference to FIGS. 25 and 26, data and address information are input to module 504 through suitable means, such as photocoupler 700. Referring specifically to FIGS.
With a signal from refresh controller 605 on LOAD line 607, the data in bus 508 is
A predetermined byte length is recorded in RAM 546 bit by bit in parallel and byte by byte in series at the reference clock rate in line 574. As best seen in Figure 25, each data channel D ₀
~D ₇ has an assigned output function, data channel D ₀ is used to operate the front panel lamp 830 of control console 800, data channel D ₁ is used for special circuit module 522, and the remaining data channel D ₂
-D ₇ is assigned to the original handling section 530, input section 532, sorter section 534, processing section 536, 538, (spare 540) of the reproduction system 10. A portion of data channels D ₁ -D ₇ contain bits for the front panel lamps and digital display of control console 800.

Since the bit capacity of data channels _D2 - _D7 is limited, a bit buffer 703 is preferably provided to detect bit overflows in data channels _D2 - _D7 .

Parts 530, 532, 534, 536, 53
8,540 is electrically far away from the CPU interface module 504 and the environment is electrically noisy, so channel D ₂
-D ₇ is preferably transmitted through shielded twisted wire pairs 704 to portions 530, 532, 534, 530, 538, and 540. With this twisted wire pair, induced noise appears as a differential input on both lines and is rejected. An associated clock signal is also transmitted on line 704.

Channel for special circuit module 522
The data in D ₁ is input to shift register 705 for communication to module 522 . Data is input to main panel interface module 526. Address information in bus 507 is transmitted to input matrix module 524 via photocoupler 700.

The CPU interface module 504 is
A fault detection circuit 706 is included to monitor both faults occurring within the system 10 and faults along the bus, where faults along the bus are typically brownouts or faults in one of the power lines. Mechanical failures include a failure within the CPU module 500, a belt setting path signal from sensor 27 (see FIG. 2), opening of one of the doors or covers, overheating of the fuser as detected by sensor 175, etc. be. In the event of a bus fault, a reset signal (RESET) is automatically generated in line 709 to the CPU module 500 (17th and 18th lines) until the fault is removed.
(see figure). In the event of a mechanical failure, a signal is generated by the CPU in line 710 to activate appropriate relays (not shown) that control power to all or part of system 10. A load disable signal (LOAD DISBEL) is input to photocoupler 700 via line 708 in the event of a failure of CPU module 500 to terminate data input to system 10. Other fault conditions are monitored by a background program. In the event of a fault, a signal is generated in line 711 to the digital display on control console 800 to indicate the fault.

With particular reference to FIGS. 25 and 27, specialized circuit module 522 consists of a collection of relatively independent circuits for monitoring the operation of system 10 or for driving various elements. module 522
Sensors 225, 226, 227, 228 are installed in the sorter 14 and the original image handling device 16, respectively.
, appropriate circuitry 712 for amplifying the outputs of 280, 281, and 282, circuitry 713 for operating fuser release clutch 159, and main and auxiliary copy paper tray feed roll clutches 130, 13.
1 and a circuit 714 for operating the original image handling device feed clutch 244.

Additionally, fuser detection circuit 715 detects fuser 150 in response to sensor 174.
monitor the temperature status of the Overheating of the fuser 150 turns off the heater 163, actuates the clutch 159 to separate the fuser roll and pressure roll, and activates the trap solenoid 158 to prevent the next copy sheet from entering the fuser 150. to trigger and stop the system 10.
A signal (FUS-OUT) is generated. Circuit 715 also periodically operates fuser heater 163 to maintain fuser 150 at the proper operating temperature.

Rotation 716 is under closed loop control by a sensor 98 responsive to the presence of copy paper 3 on belt 20. With the signal from sensor 98, solenoid 97
is triggered, the deflector 96 is moved to the belt 2
0 to the blocking position adjacent to 0. At the same time, a backup timer (not shown) is activated. If the copy sheet is lifted from belt 20 by deflector 96 within the allotted time, a signal from sensor 99 overrides the timer, a jam condition due to paper stripping malfunction of system 10 is declared, and system 10 is shut down. .
If a signal from synthesizer 99 is not received within the allotted time, a copy paper jam on photoreceptor belt 20 is declared and the system immediately shuts down.

Circuitry 718 provides operator-selected reduction mode and lens position responsive sensors 116, 11.
The image reduction position is controlled by various optical elements including the main lens 41 in response to the signal input from the main lens 41. The signal output of circuit 718 operates lens drive motor 43 when necessary to place the optical elements of lens 41 in the proper position to achieve the image reduction programmed by the operator.

Referring to FIG. 28, input matrix module 524 includes various sensors (i.e., copy paper sensors 135, 136, pressure sensor 15).
7 etc.), and includes an analog gate 719 for receiving data from the module 52.
4 converts the signal input to byte output for transmission to the I/O module 502 under the control of the input matrix selector 604. module 524
Byte output to is selected by address information input on bus 507 and encoded in module 524. Conversion matrix 720, which may be constructed from a diode array, faithfully converts an input logic signal of "O" to a logic "I". Data from input matrix module 524 is transferred to optical isolator 721 and I/O module 5.
02 input matrix selection device 604
It is transmitted to the CPU module 500.

With particular reference to FIG. 29, main panel interface module 526 serves as an interface between CPU interface module 504 and control console 800 and as an interface between input matrix module 524 and control console 800. . As previously mentioned, data channels D ₀ -D ₇ have data bits for each channel associated with a control console display or lamp. This data is clocked in buffer circuit 723 and from there for digital display.
The data of channels D ₁ - D ₂ is sent to multiplexer 7.
24. Multiplexer 724 selectively multiplexes data to segmented converter 725 . Software controlled output driver 726
is provided for each digit to enable appropriate numeric display in response to the data output of converter 725. This also provides a blank control for zero suppression or intermediate digit suppression.

Buffer circuit 723 also includes anode logic device 7
28 to enable common numeric anode drive. A signal (LOAD) to the latch and lamp drive control circuit 729 adjusts the length of the display cycle.

Channel D ₀ for control console lamp 830
The data in is clocked by a shift register 727 and its output is connected by a driver to the control console lamp. Input matrix module 52
The control console switch and keyboard access by 4 is controlled by the main panel interface module 52.
It is done through 6.

Each part of the system 530, 532, 534, 5
36,538,540 (see Figure 16) is
It is connected to the I/O module 502 by a CPU interface module 504. During each interrupt/refresh cycle, data is transferred on data channels D ₂ , D ₃ , D ₄ , D ₅ , D ₆ , D ₇ in portion 53 at the rate of the clock signal in line 574.
0,532,534,536,538,540.

The third section shows the original image handling device section 530.
Referring to FIG. 0, data input to section 530 is stored in shift registers 740 and latches 741, and circuitry 744 that supplies data to drivers 742 associated with each copying device receives signals such as input data. It is used to cut off the DC part of the circuit, and consists of a digital comparator, output latch, etc.

Output line 60 of refresh control device 605
The LOAD signal from 7 inputs new data into shift register 740. When this LOAD signal disappears, new data is transferred to latch 741. The LOAD signal also starts a timer 745 that imposes a maximum allowable deadline for refresh operations initiated by the refresh controller 605. If a refresh does not occur within the maximum time limit described above, timer 745 causes shift register 7
Generates a signal (RESET) to set 40 to zero.

Output portions 532, 536, 5 as copy processing portions except for a sorter portion 534 to be described below.
38,540 is essentially the original image handling device part 530
is the same as Therefore, the sorter portion 534 will be explained. Referring to FIG. 31, a decode matrix device consisting of a programmable read only memory (PROM) encoder 750 controlling a pair of decoders 751, 752 is provided to drive the deflector solenoid 221 of the sorter. The outputs of decoders 751, 752 drive sorter solenoids 221 on upper and lower shelves 210, 211. Input data is input to encoder 750 by shift register 754 .

Referring now to FIG. 32, control console 800 allows an operator to program system 10 to perform the required copying tasks. At the same time, various indicators on control console 800 display the operating status of system 10. The control console 800 is
It also includes a housing 802, with a panel 803 having various buttons and indicators. The buttons include a power on/off button 804, a PRINT button 805, a STOP button 806, and a keyboard copy number selector 808. A series of selection buttons are provided including an auxiliary copy paper tray button 810, a duplex copy button 811, a light copy button 814, and a dark copy button 815.

Furthermore, image size selection buttons 818, 81
9 and 820, original image selection buttons 822 and 823 for operating the original image handling device 14, a sorter setting button 825, and a stack button 826. A repair/inspection button 828 is provided for machine repair/inspection operations. Also, “READY”, “WAIT”, “Side 1”
(SIDE1)”, “Side 2 (SIDE2)”, “Add copy paper (ADD PAPER)”, “Check status panel (CHECK STATUS PANEL)”, “Press fault code (PRESS FAULT CODE)”, “Number of copies completed ( QUANTITY COMPLETED), CHECK DOORS, UNLOAD AUX TRAY, CHECK DOCUMENT PATH, CHECK PAPER PATH, and CHECK PAPER PATH. An indicator light 830 and display device such as UNLOAD SORTER is provided.

Operation (FIGS. 33-41a, 41b, 41c) It is convenient to divide automatic reproduction system 10 into a number of operating states. The control program is divided into background routines and foreground routines. Normal operations are carried out in background routines. An output buffer 562 of RAM 546 is used for refreshing and transferring control data; control data from both background and foreground routines is input to buffer 562 for sequential transfer to system 10. Transfer and refresh of control data in output buffer 562 is accomplished through direct memory access (DMA) with the aid of a machine clock interrupt routine. The control data of the foreground routine, including the work table created in response to the set copy operation, is transferred to the output buffer 562 by the multi-priority interrupt device, and the background routine being processed is temporarily interrupted. , fresh control data for the foreground routine is entered into the buffer 562, and a direct transfer of data between RAM 546 and the storage means of the device for each process takes place, after which the interrupted background routine resumes. You can start (return).

The operating program of system 10 is divided into a collection of foreground tasks, some of which are driven by several interrupt routines and background or non-interrupt routines. Foreground tasks are typically tasks that require frequent repair, fast response, or synchronization with system 10. Background routines are related to the state of system 10, and different background routines are executed in different machine states. A background control program (STAT CHK) is provided which consists of specific subprograms associated with the basic operating state of system 10. A byte called STATE contains a number indicating the current operating state of system 10.
The machine states are shown below.

State No. Machine state Control subroutine 0 Software start INIT 1 System not ready NRDY 2 System ready RDY 3 Copy PRINT 4 System in progress, RUNNPRT Not printing 5 Repair TECHREP Referring to Figure 33, each state is the start part. It is divided into , loop part, and end part. Upon entering a given state (start), it typically performs a set of operations, and these are executed only once upon entering that state. For complex operations, calls may be made to application subroutines. Relatively simple operations (i.e. turning the device on and off;
(clearing memory, presetting memory, etc.) is done directly.

Once the “starting state” is complete, we enter the main body of the loop. The program (STATCHK) remains in this loop until it receives and accepts a change in the (state) request. When there is a change in the "state" request, it enters the "remaining state" where a series of operations are performed. , followed by that "state" entering the "start" of the next "state".

Referring to the program (STATCHK) of FIG. 34, actuation of the power on button 804 enters the software initiation state (INIT). In this "state" the controller is activated and enters the controller automatic test subroutine. If the controller successfully passes the automatic tests, it enters the "System Not Ready State" (NRDY). If not, a fault signal is issued.

In “System Not Ready State” (NRDY),
Enter background routine. These include settings for ready graphs, control registers, timers, etc.
Turning on power supplies, fusers, etc., starting fault handling equipment (remaining from previous work)
This includes checking the copy paper jam, door and cover interlocks, fuser temperature, etc. During this period, the standby lamp on the control console 800 is lit and operation of the system 10 is inhibited.

When all readiness conditions have been checked and found to be satisfactory, the controller 18 enters the system readiness state (RDY), the readiness lamp on the control console 800 is illuminated, and a final readiness check is made. Completion of copying program input, loading one or more originals 2 into original handling device 16 (if selected by the operator), and actuation of start print button 805 prepares system 10 for operation. Next, the status is copying or printing, and the set copying operation is executed.

Following a copy operation (print), the controller normally enters the system not ready state (NRDY) to recheck readiness conditions. If all is satisfied and the power off button 804 is not pressed and there is no shutdown due to failure, the system proceeds to the system readiness state (RDY). The last state (TECH REP) is the machine repair state, and here the repair routine is available to the machine repairman.

With particular reference to FIG. 32, a control console 800 is used for the necessary copying operations. Settings can be made in the system not ready state (NRDY) or system ready state (RDY). Copying operations include determining the number of copies using the keyboard 808 and, when necessary, using the auxiliary copy paper tray 102 (push button 810), selecting the image size (push buttons 818, 819, 820), and using the original handling device/sorter. Select (push buttons 822, 823,
825, 826), copy density (push button 814,
815) etc. Once the settings for the copying job are completed, the print start button 805 is activated to start the programmed copying job. In the following description, it is assumed that the ready lamp is turned on, that the original handling device 16 is selected, and that original 2 is placed in the tray 233 of that original handling device 16.

The controller 18 stores the set information in RAM.
An input routine is entered which is transmitted to portion 546. The copy work program data is sent to the input matrix module 524 via the main panel interface module 526, and then to the I/O module 50.
2 matrix input selection device 604, multiplexer 624, and buffer 620.
It is input to a predetermined address in the RAM portion 546 of the CPU module 500.

Once in the print state, a work event table (FIG. 35) consisting of foreground tasks cooperating with background tasks causes the various copy processors of system 10 to operate to make programmed copies. The content of the job is formed by controller 18 through a combination of fixed pitch event tables and variable pitch event tables stored in ROM 545 and non-volatile memory 610, as appropriate for the selected job.

The fixed pitch event table is transferred to the transfer roll 7.
5, the operation of the toner concentration sensor 65, the timing of the roll 161 of the fuser 150, etc., during the pitch cycle. Variable pitch table has pitch fade out lamp 4
The operating timing, such as the timing of the flashlight lamp 37 and the timing of the flash illumination lamp 37, are comprised of mechanical events whose operating timings change with each copying operation. The variable pitch table is combined with event address information from ROM section 545, partitioned by actual clock counts, and stored in RAM section 546;
The pitch table is constructed from copy job information programmed by controller 18 (using the machine control program stored in ROM portion 545 and non-volatile memory 610). The fixed pitch event table and the variable pitch event table are combined with relative clock count differences between pitch events calculated to form a working event table.

With particular reference to FIG. 35, the work event table consists of a series of individual events 851.
Each event 851 consists of four blocks, block 852 containing the number of clock pulses (from machine clock 202) to the next predetermined pitch event (REL DIFF), and block 853 containing the shift register position associated with that event. (RELSR), and block 854 (event
LO) and 855 (Event HI) contain the address of the event subroutine. In machine states other than printing, block 852 (REL
DIFF), 853 (REL SR) are set to zero. Data blocks 854 and 855 hold address information for non-copy state events.

The control data in the work event table represents part of the foreground task and is transferred to buffer 562 in RAM 546 by a routine that inhibits the pitch reset and machine clock. Other control data representing foreground tasks that is not in the work event table is
RAM buffer 562 due to original image handling device clock and real-time clock interrupt routines.
will be forwarded to. The remaining transfer of control data to buffer 562 is accomplished by background (non-interrupt) routines. Transfer of control data from output buffer 562 of RAM 546 to various locations in system 10 is accomplished by refreshing via DMA in response to machine clock interrupt signals. The interrupt routine uses individual interrupt signals 640, 641, 642, 6
43.

Please refer to FIGS. 23, 35-37. The pitch reset interrupt signal 640, which has the highest priority, can only operate in the copying state and is triggered every revolution of the copy paper register finger 141 as responded by the sensor 146 of the pitch reset clock generator 138. Occurs once in. In the case of an interrupt signal, an interrupt signal (INT) is generated at each pitch reset interrupt signal after determining the priority by the priority chip 659. Receipt from processor 542, an acknowledgment signal (INTA), initiates the spot reset interrupt routine.

Upon entering the Pitch Reset routine, interrupts are again enabled and the contents of the working registers are stored. A check is made to determine if the work event table is complete. A check is also made to ensure that at least 910 clocks have been counted since the new shift register value was formed and the last tight reset elapsed. If not, the machine will stop immediately. Note that this pitch reset routine also performs an interrupt operation shown in a machine interrupt routine (see FIG. 37), which will be described later.

If the above check is satisfactory, the shift register pointer, which is a variable byte containing the address of the previously selected shift register location, is decremented by one, and the contents of the shift register are shifted following the exact reset interruption. A variable byte containing the new shift register value to be updated. The event pointer and the next predetermined variable 2 bytes containing the entire address of the event are reset to event number 1.

A machine cycle down, normal down, and plane 1 delay checks are made and, if negative, the count of the cycle up counter is checked. If this count is less than the expected control count (ie 5), the counter increments by one. When the count of the cycle up counter is equal to the control count, the imaging flag is set.

When a normal down, cycle down, or plane 1 delay is initiated, the cycle up counter is reset to the preset starting count (ie, 2). The tight reset interrupt routine is
This ends with restoration of the working registers and resetting of the tight reset flip-flop 647.

The second priority mechanical clock interrupt routine operates in all operating states of system 10. When the drive motor 34 of the processing device operates, the mechanical clock 2 operates only in the present state.
02 generates a mechanical clock. Mechanical clock pulses are provided by phase lock loop 649 when motor 34 is stopped.

Referring to FIG. 38, a machine clock interrupt routine is entered by a signal (INTA) from processor 542 following machine clock interrupt signal 642, as described above. The event control register (C
register) is obtained and the contents of the working register are recorded. This C register is decremented by one,
Preset to the count corresponding to the next event in the event work table.

The control register (C REG) is zero checked. If the count is not zero, a refresh operation is started. Note that if the number of refresh operations is large, the number may be decreased. In this case, as shown in FIG. 37, if the count in the control register is not zero but an odd number, an output refresh cycle is started and the data in the RAM output buffer 562 is directly transferred to the system 10 for refreshing. If this number is even, or if the interrupt system is re-enabled following an output refresh, the machine clock interrupt flip-flop 651 may be reset to restore the working registers. after that,
Return to the interrupted routine.

If the control register count is zero, then
The event pointer identifying the clock count (in data block 852) for the next scheduled event (REL DIFF) is loaded and the control register is reset to the new count at a time equal to the next event. The event pointer is incremented to the relative shift register address for the event (RELSR, data block 853) and the shift register address information is set in the shift register (B, D, E, A register).

The event pointer is the event subroutine address information (EVENT
LO) (EVENT HI) and the address information is loaded into the register pair (D&E registers). The event pointer is incremented to the first data block (REL DIFF) of the next event in the working event table, and the register pair that makes up the event pointer (H&L registers) receives the event from the register pair that holds the information (D&E registers). Loaded by subroutine address. A register pair (D&E registers) is set to the return address for the event subroutine. Using the address information, the event subroutine is called and the subroutine is transferred to the RAM output buffer 562 for transfer to the system on the next output refresh. The machine clock interrupt routine then ends as previously described.

The output refresh cycle transfers/refreshes data from output buffer 562 of RAM 546 to system 10. Direct memory access (DMA) ensures high data transfer rates.

During a refresh, the refresh controller 605 (see FIG. 23) invokes the HOLD line to the processor 542, which is communicated by the HOLD A signal when the operation in progress is complete. Processor 5 in hold state
42, and (batshua 510, 511, 563,
570) I/O module 502
With the address bus 507 and data bus 508 released to be done.

The original image handling device interrupt routine operates only when the original image handling device drive motor 236 operates. Original image handling device interrupts have the third priority.

With particular reference to FIG. The original handler interrupt routine is accomplished in the same manner as described above in conjunction with the spot reset and machine interrupt routines, and is entered in response to a special restart instruction code for this routine. Upon entry, shutdown is enabled and program registers are stored. A control counter that counts clock counts between events is decremented and its count is queried. Based on this count, the appropriate original handling device routine (AD-
STATE) is called. The registers are then restored and original handler interrupts are again possible.

Real-time interrupts with the lowest priority operate in all machine states. First, the interrupt acts as an interval timer by decrementing a series of timers, which in turn serves to control the initiation of background subroutines used for control and error checking purposes.

See Figures 40a, 40b, 40c. The real-time interrupt routine is entered in the same manner as the interrupt routines described above, and in response to a special restart instruction code assigned to the real-time interrupt. When this routine is entered, interrupts are again enabled and the contents of the registers are stored. The timer pointer (PNTR) for the first class of timers (ie, 10 msec timers) is loaded and a loop counter identifying the number of timers in this class (ie, 10 msec timers) is preset. The control register is loaded and the timer decrement loop is entered for the first timer.
This loop decrements the special timer, increments the timer pointer to the location of the next timer in this class, checks the timer count, and decrements the loop counter. The decrement loop routine iterates for each timer in this class (i.e. 10msec timers) and subsequently the control counter is decremented by one for the second group of timers (i.e. 100msec timers) and its count is checked. be done.

The control counter is initially set to a count equal to the first timer interval divided into the second timer interval, and so on. For example, if the first class of timers is a 10msec timer and the second class of timers is a 100msec timer, the control counters are initially set to 10 and then ramped down to zero by one at each real-time interruption. Decrease.

If the count of the control counter is not zero,
The registers are restored, the real-time interrupt flip-flop 856 is reset, and the routine exits. If the count of the control counter is zero, then the counter is set to the first maximum count (i.e. 10)
and enters a loop that individually decrements the second group of timers (i.e., the 100 msec timers). When complete, exit this routine as described above.

With particular reference to the timing chart shown in FIG.
A typical copying operation is shown that makes two-sided copies. The copy selector 808 button in FIG. 32 is set to the required copying machine, ie, 3, and the original handling device button 822, sorter selection button 825, and duplex button 811 are pressed. Originals, in this case two, single-sided originals, are loaded into the toner 233 of the original handling device 16 (FIG. 14);
Then, the print button 805 is pressed. When the button 805 is pressed, the system 10 enters the print state and the work event table for the copying operation is constructed by the controller 18 and the RAM portion 5
46. As previously mentioned, the working event table, along with the background routines, passes through the multiple interrupt system and output refresh (through DMA) to the system 1 in time to form a programmed copy.
Useful for operating various components of 0.

During operation, the first original is advanced by the original handling device 16 onto the platen 35 and here three exposures (first side 1) are made, as seen in FIG. Three electrostatic latent images are formed on belt 20 in succession. As mentioned above, these images are developed in the developer section 28 and transferred to individual copy sheets fed forward from the main copy sheet tray 100 (first feed side 1). The copy paper bearing these images is transported by a vacuum transport device 155 between the transfer roll and the belt to a fixing device 150, where the images are fixed. Following fusing, the copy paper is directed by deflector 184 to return transport 182 and conveyed to auxiliary copy paper tray 102. Paper entering tray 102 is aligned by edge pattern 187 in preparation for refeeding.

Following the feeding of the last copy sheet to the auxiliary copy paper tray 102, the original handling device 16 is operated to remove the first original from the platen 35 and record the original of FIG. 2 on the platen 35. bring into position. The second original image is exposed three times (side 2) and the image is developed on the belt 20 of the developer station 28 and transferred to the opposite side of the copy sheet which was imaged on one side. Following transfer, the image on side 2 is fixed by fuser 150 and advanced toward stop 190 .
The engagement of the leading edge of the copy sheet and the stop 190 directs the trailing edge of the sheet into the discharge chute 186 to invert the copy sheet with images formed on both sides. The reversed sheets are guided into the sorter 14 through the conveyance device 181 and placed on the shelves 21 according to the arrangement of the deflectors 220.
It is placed at either 0,211.

The sorter 14 and the original image handling device 16 do not need to be provided as long as they can perform copying operations on either one side or both sides.

Effects of the Invention Therefore, according to the copying machine according to the present invention, the controller 18 is provided with an interrupt means, a direct memory access means, and a refresh means, and these are organically related to each other to reduce noise from the software perspective. The interrupt means includes a first clock pulse for synchronization necessary to operate each processing device of the copying machine, and a second clock pulse generated in synchronization with an interval corresponding to one copying operation. at least two clock pulse generating means are connected to the processor unit, and the interrupt means is configured to interrupt the processor unit by sending interrupt signals having different priorities to the processor unit according to the first and second clock pulses, The direct memory access means cooperates with the refresh means to transfer the control data from the memory directly and independently of the control of the processor unit to the storage means of the apparatus for copy processing. The refresh means is controlled by the interrupt means, and the interrupt means is characterized in that it interrupts the operation of the processor unit when the control data is directly transferred, and resumes the operation when the transfer is completed. Even if an abnormal noise that changes the state occurs, the storage means in the device is refreshed every short period of time to ensure that the correct control data is available for each copying process before any movement occurs in the motor or switch. Since the signal is sent to the device, it returns the state changed due to abnormal noise to the correct state.

In the present invention, by combining the refresh means with the interrupt means and the direct memory access means, the contents of the control data memory can be quickly transferred to the copy processing device while temporarily interrupting the microprocessor. For example, because it sends data in a short time of less than 30 microseconds and achieves high-speed response, it is possible to use an inexpensive commercially available microprocessor, which eliminates the need for expensive hardware to prevent noise. A highly reliable high-speed copying machine can be obtained without requiring any wear.

[Brief explanation of drawings]

1 is a schematic front view of an automatic copying system in which the control device of the present invention is combined, FIG. 2 is a left side view of the automatic copying system shown in FIG. 1 with the sorter removed, and FIG. 3 is the same as shown in FIG. FIG. 4 is a perspective view showing the driving part of the automatic copying system shown in FIG. 1, and FIG. 6 is an enlarged view showing details of the developing device of the system shown in FIG. 1, FIG. 7 is an enlarged view showing details of the drive device of the developing device, and FIG. FIG. 9 is an enlarged view showing details of the development control device of the system shown in FIG. 1; FIG. 9 is an enlarged view showing details of the transfer load support mechanism of the system shown in FIG. 1;
FIG. 10 is an enlarged view showing details of the photoconductor cleaning mechanism of the system shown in FIG. 1, FIG. 11 is an enlarged view showing details of the fixing device of the system shown in FIG. 1, and FIG. Schematic diagram showing the paper transport mechanism and sensors of the system shown in FIG.
3 is an enlarged view showing details of the sorter of the system shown in FIG. 1, FIG. 14 is a schematic view showing details of the original image handling device of the system shown in FIG.
5 is a diagram showing details of the drive mechanism of the original handling device shown in FIG. 14, FIG. 16 is a block diagram of the controller of the automatic copying system according to the present invention, and FIG. 17 is a block diagram of the CPU module. 18
Figure 18a is a block diagram showing the input and output connections of the CPU module, Figure 18b is a timing chart for DMA read and write cycles, Figure 19
Figure a is a logic diagram of the clock generator, Figure 19b is a chart showing the output waveform of the clock generator shown in Figure 19a, Figure 20 is a logic diagram of the RAM and ROM of the CPU module and their connection, and Figure 21 is a diagram showing the output waveforms of the clock generator shown in Figure 19a.
Figure 22a, 22b, and 22c are circuit diagrams of the power supply for the CPU module, etc., Figures 23a and 23b are block diagrams of the I/O module, and Figure 24 is the nonvolatile memory power supply. Figure 25 is a logic diagram showing the connections between the CPU interface module and the main pulse interface module.
Figure 6 is a block diagram of the CPU interface module, Figure 27 is a block diagram of the special circuit module, Figure 28 is a block diagram of the main panel interface module, Figure 29 is a block diagram of the input matrix module, 30 is a block diagram of a typical remote device; FIG. 31 is a block diagram of a remote sorter; FIG. 32 is a plan view of a control console for inputting copying commands into the system shown in FIG. 1; FIG. 33 is a flowchart showing typical machine operating conditions, FIGS. 34a and 34b are flowcharts of the machine's operating routine, FIG. 35 is a diagram showing an event table in the copying state, and FIG. 36 is a flowchart showing various clocks. FIG. 37 is a flowchart of a pitch reset interrupt routine;
Figure 39 is a flowchart of the machine clock interrupt routine, Figure 39 is a flowchart of the original image handling device interrupt routine, and Figures 40a and 40b.
Figures 41a, 41b and 41c are timing diagrams of the major operating components of the automatic copying system during a typical copying operation. Explanation of the code, 2...Original picture, 3...Copy paper,
10... automatic copying system, 12... copying machine, 1
4... Sorter, 16... Original picture handling device, 18...
...Controller, 20...Photoreceptor belt, 27...
...Exposure section, 28...Development section, 34...Motor, 3
5...Platen, 75...Transfer roll, 100...
...Main copy paper tray, 102...Auxiliary copy paper tray, 138...Pight reset clock generator, 202...Mechanical clock generator, 500...
... CPU module, 502 ... I/O module, 504 ... CPU interface module, 507 ... address bus, 508 ... data bus, 509 ... control bus, 542 ... microprocessor, 545 ... ROM , 546...
RAM, 601...Function decode/ready section, 605...Refresh control section, 61
0...Non-volatile (NV) memory, 612...Interrupt control device.

Claims (1)

Claims: 1. A plurality of selectively energized copy processing devices adapted to operate together with each other and with a photosensitive member to electrostatically produce a copy on a support. , comprising a control console for setting various types of copying operations, clock pulse generation means, and a controller with a memory for operating the processing apparatus, and the controller uses control data from the memory to perform operations according to specific copying operations set. In a copying machine configured to energize devices for predetermined processing in a timing sequence, the controller is provided with at least a processor unit, an interrupt means, a direct memory access means, and a refresh means, and the interrupt means is provided with at least a processor unit, an interrupt means, a direct memory access means, and a refresh means. is connected to the clock pulse generating means, and the clock pulse generating means generates clock pulses in synchronization with the first clock pulse for synchronization necessary for the operation of each processing device of the copying machine and at intervals corresponding to one copying operation. The interrupt means generates at least two clock pulses, a second clock pulse and a second clock pulse, and the interrupt means interrupts the processor unit by sending interrupt signals having different priorities to the processor unit according to the first and second clock pulses. The interrupt signal controls the direct memory access means and the refresh means, and the direct memory access means cooperates with the refresh means to directly transfer control data from the memory and control the processor unit. A copying machine, wherein the control data is independently transferred to the copy processing device, and when the control data is directly transferred, the interrupt means interrupts the operation of the processor unit, and resumes the operation when the transfer is completed.