JPH0136691B2 - - Google Patents

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Publication number
JPH0136691B2
JPH0136691B2 JP57030034A JP3003482A JPH0136691B2 JP H0136691 B2 JPH0136691 B2 JP H0136691B2 JP 57030034 A JP57030034 A JP 57030034A JP 3003482 A JP3003482 A JP 3003482A JP H0136691 B2 JPH0136691 B2 JP H0136691B2
Authority
JP
Japan
Prior art keywords
reaction tube
wafer
tube
compound semiconductor
heating table
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57030034A
Other languages
Japanese (ja)
Other versions
JPS58147112A (en
Inventor
Kazumi Kasai
Kenya Nakai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3003482A priority Critical patent/JPS58147112A/en
Publication of JPS58147112A publication Critical patent/JPS58147112A/en
Publication of JPH0136691B2 publication Critical patent/JPH0136691B2/ja
Granted legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/02546Arsenides
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/52Controlling or regulating the coating process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/02549Antimonides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)

Description

【発明の詳細な説明】 (a) 発明の技術分野 本発明は急峻な不純物濃度勾配をもつ多層構造
の化合物半導体を製造する結晶製造装置に関す
る。
DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a crystal manufacturing apparatus for manufacturing a compound semiconductor having a multilayer structure having a steep impurity concentration gradient.

(b) 技術の背景 硼素(B)、アルミニウム(Al)、ガリウム(Ga)、
インジウム(In)などの族元素と窒素(N)、
燐(P)、砒素(As)、アンチモン(Sd)などの
族元素とが共有結合して正四面体配位をとり閃
亜鉛鉱形或はウルツ鉱形の結晶構造をとるガリウ
ム砒素(GaAs)、インジウムアンチモン
(InSb)、インジウム砒素(InAs)などの―
族化合物半導体は公知である。これらの―族
化合物半導体の単結晶は水平ブリツジマン法、帯
域溶融法、単結晶引上げ法などの溶融法か或は材
料の昇華を利用するか輸送剤による化学反応を利
用する気相エピタキシヤル法など各種の方法を用
いて育成されている。こゝでマイクロ波用ダイオ
ード、トランジスタ或はレーザ素子などの半導体
素子は単結晶ウエハにドナー不純物又はアクセプ
タ不純物を拡散させるか単結晶ウエハ上にこれら
の不純物を含んだ同種の結晶をエピタキシヤル成
長させて半導体の電導のタイプ(電子電導、正孔
電導)および電導度の異つた半導体領域を作り、
これを用いることによつて各種のデバイスが形成
されている。
(b) Technical background Boron (B), aluminum (Al), gallium (Ga),
Group elements such as indium (In) and nitrogen (N),
Gallium arsenide (GaAs) is covalently bonded with group elements such as phosphorus (P), arsenic (As), and antimony (Sd) to form a regular tetrahedral coordination and has a zincblende or wurtzite crystal structure. , indium antimony (InSb), indium arsenide (InAs), etc.
Group compound semiconductors are known. Single crystals of these - group compound semiconductors can be produced by melting methods such as the horizontal Bridgeman method, zone melting method, and single crystal pulling method, or by vapor phase epitaxial methods that utilize sublimation of materials or chemical reactions with transport agents. It is cultivated using various methods. Semiconductor devices such as microwave diodes, transistors, and laser devices are manufactured by diffusing donor impurities or acceptor impurities into a single-crystal wafer, or by epitaxially growing the same type of crystal containing these impurities on a single-crystal wafer. to create semiconductor regions with different conductivity types (electron conduction, hole conduction) and conductivity.
By using this, various devices are formed.

さてダイオード、トランジスタなど電導キヤリ
ヤの種類が異る半導体層の接合を用いるデバイス
においては高い整流比をもつていることが必要で
あり、これは急峻な不純物濃度勾配をもつ半導体
層を作ることによつて実現できる。本発明はこの
ような急峻な濃度勾配をもち多層構造をとる化合
物半導体をエピタキシヤル成長せしむる結晶成長
装置の構造に関するものである。
Now, devices such as diodes and transistors that use junctions of semiconductor layers with different types of conductive carriers need to have a high rectification ratio, and this is achieved by creating semiconductor layers with steep impurity concentration gradients. It can be realized. The present invention relates to the structure of a crystal growth apparatus for epitaxially growing a compound semiconductor having a multilayer structure with such a steep concentration gradient.

(c) 従来技術と問題点 第1図は従来のエピタキシヤル成長装置の断面
構造を示す。同図において、化合物半導体単結晶
からなるウエハ1はグラフアイト製の加熱台2の
上に置かれており、この加熱台2の内部には保持
棒3の内部に熱電対4が挿入されており、これに
よりエピタキシヤル成長させるウエハ1の温度測
定がされるようになつている。また石英製の反応
容器5の上部には化合物半導体をエピタキシヤル
成長させるための原料ガスを導入する複数個の導
入口6が設けられておりまた反応容器5の下部に
は排出口7が設けられている。こゝで化合物半導
体の原料ガスとドーパントは給気口6より導入さ
れて混合した状態でウエハ面に供給され、高周波
誘導加熱炉8により加熱されたウエハ1の面上で
分解してエピタキシヤル成長が行われ、分解が終
つた不要ガスは排気口7より除去される。かゝる
従来の縦形気相成長装置において急峻な多層構造
をもつエピタキシヤル層を成長させるためには次
の何れかの方法がとられていた。
(c) Prior Art and Problems Figure 1 shows a cross-sectional structure of a conventional epitaxial growth apparatus. In the figure, a wafer 1 made of a compound semiconductor single crystal is placed on a heating table 2 made of graphite, and a thermocouple 4 is inserted into a holding rod 3 inside the heating table 2. This allows the temperature of the wafer 1 to be epitaxially grown to be measured. Further, a plurality of inlet ports 6 for introducing raw material gas for epitaxially growing a compound semiconductor are provided in the upper part of the reaction container 5 made of quartz, and an outlet port 7 is provided in the lower part of the reaction container 5. ing. Here, the raw material gas and dopant for the compound semiconductor are introduced through the air supply port 6 and supplied to the wafer surface in a mixed state, and are decomposed on the surface of the wafer 1 heated by the high frequency induction heating furnace 8, resulting in epitaxial growth. The unnecessary gas that has been decomposed is removed from the exhaust port 7. In such conventional vertical vapor phase growth apparatuses, one of the following methods has been used to grow an epitaxial layer having a steep multilayer structure.

(1) 原料ガスの流量を大にする。(1) Increase the flow rate of raw material gas.

(2) 原料ガスをウエハ近くまで細管を用いて導入
する。
(2) Introduce the source gas close to the wafer using a thin tube.

(1)の方法は反応容器中の原料ガスの交換は速に
行われるが、ウエハおよび原料ガスの分解温度や
ガスの流れなどが変る結果としてエピタキシヤル
成長の均一性を損うと云う欠点がありまた(2)の方
法は成長過程の温度調節を熱電対によらず赤外線
温度計を用いて行うような場合には視野を遮るた
め使えないと云う欠点があり、急峻な不純物濃度
をもつ多層構造をエピタキシヤル成長法により形
成することは困難であつた。
In method (1), the source gas in the reaction vessel can be exchanged quickly, but it has the disadvantage that the uniformity of epitaxial growth is impaired as a result of changes in the decomposition temperature of the wafer and source gas, the gas flow, etc. Method (2) has the disadvantage that it cannot be used when the temperature during the growth process is controlled using an infrared thermometer instead of a thermocouple because it obstructs the field of view. It has been difficult to form this by epitaxial growth.

(d) 発明の目的 本発明は急峻な不純物濃度分布をもつ化合物半
導体の多層構造をエピタキシヤル成長させる結晶
成長装置を提供するにある。
(d) Object of the Invention The present invention provides a crystal growth apparatus for epitaxially growing a compound semiconductor multilayer structure having a steep impurity concentration distribution.

(e) 発明の構成 本発明によれば、この目的は、保持棒により保
持されている加熱台の上にウエハを固定し、加熱
台を中心として内壁部に緩く嵌合するライナ管を
備え、外周部に高周波誘導加熱用コイルを備える
下部反応管と、この下部反応管よりも内径が小さ
く、側面に種類の異なる反応ガスが導入される複
数のガス導入管を備え、上部に赤外線温度計によ
りウエハの温度測定を可能とする頭頂部を備えた
上部反応管とが接続して設けられており、複数の
ガス導入管より装置内に流入する反応ガス種の切
り換えを行うことにより急峻な濃度勾配をもち多
層構造をとる化合物半導体層をエピタキシヤル成
長させる結晶成長装置の使用により解決すること
ができる。
(e) Structure of the Invention According to the present invention, the object is to fix the wafer on a heating table held by a holding rod, and to provide a liner tube that loosely fits into the inner wall around the heating table; The lower reaction tube is equipped with a high-frequency induction heating coil on the outer periphery, and the inner diameter of the lower reaction tube is smaller than the lower reaction tube. It is equipped with multiple gas introduction tubes on the side for introducing different types of reaction gases, and the upper part is equipped with an infrared thermometer. It is connected to an upper reaction tube with a top part that enables the temperature measurement of the wafer, and a steep concentration gradient can be achieved by switching the type of reaction gas flowing into the device from multiple gas introduction tubes. This problem can be solved by using a crystal growth apparatus that epitaxially grows a compound semiconductor layer having a multilayer structure.

(f) 発明の実施例 第2図は本発明にかゝる化合物半導体結晶の成
長装置の説明図また第3図はこれを用いて作られ
る電界効果トランジスタ(FET)の構成図であ
る。
(f) Embodiments of the Invention FIG. 2 is an explanatory diagram of a compound semiconductor crystal growth apparatus according to the present invention, and FIG. 3 is a block diagram of a field effect transistor (FET) manufactured using the same.

以下化合物半導体としてGaAsを用いる実施例
について本発明を説明する。
The present invention will be described below with reference to an embodiment using GaAs as the compound semiconductor.

第3図に示すマイクロ波用GaAsFETは厚さ約
500μmのGaAsウエハ基板9の上にクローム元素
(Cr)をドープした厚さ2〜3μmの高抵抗の
GaAsバツフア層10がありこの上に厚さが約
0.3μmで不純物濃度nが1×1017cm-3のN型の
GaAs動作層11が何れもエピタキシヤル成長法
で作られ、この動作層11に金・ゲルマニウム合
金(Au・Ge合金)を拡散させてソース(S)電
極とドレイン(D)電極を作り、また中央部にア
ルミニウム(Al)からなるゲート(G)電極を
形成した構造をしている。ここでGaAsFETが優
れた電気的特性を示すためにはバツフア層10か
ら動作層11への不純物濃度勾配が急峻な勾配を
もつて行われていることが必要である。
The microwave GaAsFET shown in Figure 3 has a thickness of approx.
A 2-3 μm thick high-resistance film doped with chromium element (Cr) is placed on a 500 μm GaAs wafer substrate 9.
There is a GaAs buffer layer 10 on top of which the thickness is approximately
N-type with 0.3μm and impurity concentration n of 1×10 17 cm -3
A GaAs active layer 11 is made by epitaxial growth, and a source (S) electrode and a drain (D) electrode are formed by diffusing gold/germanium alloy (Au/Ge alloy) into this active layer 11. It has a structure in which a gate (G) electrode made of aluminum (Al) is formed in the upper part. In order for the GaAsFET to exhibit excellent electrical characteristics, it is necessary that the impurity concentration gradient from the buffer layer 10 to the active layer 11 be steep.

第2図の本発明に係る装置はこれを実現するも
ので、第1図の従来の装置と較べて次のような特
徴がある。
The device according to the present invention shown in FIG. 2 realizes this, and has the following features compared to the conventional device shown in FIG.

(1) 反応管において原料ガスが導入される上部反
応管12部分がエピタキシヤル成長が行われる
下部反応管13よりも細く形成されている。
(1) In the reaction tube, the upper reaction tube 12 portion into which the raw material gas is introduced is formed to be thinner than the lower reaction tube 13 through which epitaxial growth is performed.

(2) 下部反応管13内部にライナ管14が設けら
れている。
(2) A liner tube 14 is provided inside the lower reaction tube 13.

(3) 上部反応管12の頭頂部15は光学的に透明
に作られている。
(3) The top portion 15 of the upper reaction tube 12 is made optically transparent.

こゝで反応管は石英製であり上部反応管12の
外周側面には複数個のガス導入口(この実施例の
場合4個)が設けられており本実施例の場合、ア
ルシン(AsH3)16、トリメチールガリウムGa
(CH3317、硫化水素(H2S)18、クローム
カルボニルCr(CO)619などの原料ガスが供給さ
れるようになつており、上部反応管12において
混合されて加熱台2の上に置かれたGaAsウエハ
1に垂直に供給されるようになつている。こゝで
AsH3とGa(CH33は Ga(CH33+AsH3→GaAs+3CH4 …(1) の反応によつてGaAsを気相成長させるためのも
のであり、Cr(CO)6は第3図におけるバツフア層
10を成長させるためのドーパントまたH2SはN
型動作層11を成長させるためのドーパントであ
る。
Here, the reaction tube is made of quartz, and a plurality of gas inlets (four in this example) are provided on the outer peripheral side of the upper reaction tube 12 . 16. Trimethyl gallium Ga
Raw material gases such as (CH 3 ) 3 17, hydrogen sulfide (H 2 S) 18, and chromium carbonyl Cr (CO) 6 19 are supplied, and are mixed in the upper reaction tube 12 and sent to the heating table 2. It is designed to be supplied perpendicularly to the GaAs wafer 1 placed above. Here
AsH 3 and Ga(CH 3 ) 3 are used for vapor phase growth of GaAs through the reaction Ga(CH 3 ) 3 +AsH 3 →GaAs+3CH 4 (1), and Cr(CO) 6 is used as a third The dopant or H 2 S for growing the buffer layer 10 in the figure is N
This is a dopant for growing the type operation layer 11.

第2図において上部反応管12が細く作られて
いる理由はガスの導入口16〜19よりウエハ1
までの反応管の容積を少くすることによりガスの
交換を容易とするもので、これにより急峻な立上
り分布をもつ多層構造が可能となる。すなわち第
3図に示すGaAsFETのバツフア層10は上部反
応管12に設けられている4個の導入口の内
AsH316、Ga(CH3317およびCr(CO)619
の3つ導入口より供給される原料ガスにより行わ
れまた動作層11は16〜18の3つの導入口よ
り供給される原料ガスを用いてエピタキシヤル成
長を行はしめて形成される。さて実施例の場合、
反応容器は総べて石英製であるが、本発明の第2
の特徴として前記上部反応管12に連続する下部
反応管13の内側にライナ管14が設けられてい
ることで、これは容器と同様に石英製であつてこ
の上端は上部反応管12に緩く嵌合するようにな
つている。このライナ管14を設ける目的は原料
ガスの流通路を規制してガスの容積を少くし不純
物濃度分布の急峻な変化を可能とすると共に下部
反応管13が熱分解生成物によつて汚染されるこ
とを防いでいる。すなわち原料ガスはライナ管1
4の内側を通りウエハ1に導かれるために細管を
用いてウエハの直上まで原料ガスを導いたのと同
様な結果となり急峻な濃度勾配が可能となる。
The reason why the upper reaction tube 12 is made thin in FIG. 2 is that the wafer 1
By reducing the volume of the reaction tube, gas exchange is facilitated, and this enables a multilayer structure with a steep rise distribution. In other words, the buffer layer 10 of the GaAsFET shown in FIG.
AsH 3 16, Ga(CH 3 ) 3 17 and Cr(CO) 6 19
The active layer 11 is formed by epitaxial growth using source gases supplied from three inlets 16 to 18. Now, in the case of the example,
The reaction vessels are all made of quartz, but the second
A feature of this is that a liner tube 14 is provided inside the lower reaction tube 13 that is continuous with the upper reaction tube 12, and this liner tube 14 is made of quartz like the container, and its upper end is loosely fitted into the upper reaction tube 12. It's starting to match. The purpose of providing this liner tube 14 is to restrict the flow path of the raw material gas, reduce the gas volume, and enable a steep change in impurity concentration distribution, while also preventing the lower reaction tube 13 from being contaminated by thermal decomposition products. It prevents that. In other words, the raw material gas is in the liner tube 1.
4 to the wafer 1, the result is the same as when the raw material gas is guided directly above the wafer using a thin tube, and a steep concentration gradient is possible.

次に第3の特徴は上部反応管12の頭頂部15
を透明体(この場合透明石英)で形成することに
より赤外線温度計20を用いて直接にウエハ1の
温度制御が行える点である。なおこれは第1図に
示す従来例のように保持棒3の内部に熱電対を備
える構造でもよいが、直接にエピタキシヤル成長
面の温度を測定する方が正確に結晶成長を制御す
ることができる。なお第2図において、21はウ
エハ1を加熱する高周波誘導加熱用コイルであ
る。
Next, the third feature is the top portion 15 of the upper reaction tube 12.
By forming the wafer 1 from a transparent material (transparent quartz in this case), the temperature of the wafer 1 can be directly controlled using the infrared thermometer 20. Note that this may be a structure in which a thermocouple is provided inside the holding rod 3 as in the conventional example shown in FIG. 1, but it is better to directly measure the temperature of the epitaxial growth surface to control crystal growth more accurately. can. In FIG. 2, reference numeral 21 denotes a high-frequency induction heating coil for heating the wafer 1. As shown in FIG.

かかる構成によれば、ウエハ面に均一に成長を
行うために保持棒を回転させることが容易である
が熱電対を備える構造ではそれに対応することが
困難である。
According to such a configuration, it is easy to rotate the holding rod in order to uniformly grow on the wafer surface, but it is difficult to handle this with a structure including a thermocouple.

以上のような、本発明は不純物濃度分布が急峻
に変化するエピタキシヤル成長層を得るための装
置であり、GaAsFETの製造について説明したが
第2図の本発明に係る装置において導入口の数を
増すことにより組成の異なる多層構造を作ること
ができる。例えば導入口よりトリメチールアルミ
ニウムAl(CH33をGa(CH33およびAsH3と同時
に導入すればGaAlAsの組成をもつ半導体層をエ
ピタキシヤル成長させることができるし、これら
の多層構造は光学素子の作製に有効である。な
お、前記実施例にあつては、縦型の結晶成長装置
について述べたが、本発明はこれに限られるもの
ではなく、横型の結晶成長装置に対しても適用す
ることができる。
As described above, the present invention is an apparatus for obtaining an epitaxially grown layer in which the impurity concentration distribution changes sharply, and although the manufacturing of GaAsFET has been explained, the number of introduction ports in the apparatus according to the present invention shown in FIG. By increasing the number of layers, it is possible to create a multilayer structure with different compositions. For example, if trimethylaluminum Al(CH 3 ) 3 is introduced through the inlet at the same time as Ga(CH 3 ) 3 and AsH 3 , a semiconductor layer having a composition of GaAlAs can be epitaxially grown, and these multilayer structures Effective for producing optical elements. Although the above embodiments have been described with respect to a vertical crystal growth apparatus, the present invention is not limited thereto, and can also be applied to a horizontal crystal growth apparatus.

(g) 発明の効果 本発明によれば、上部反応管を細長く形成する
と共に下部反応管にライナ管を設け、また頭頂部
を透明にして赤外線温度計を用いて温度調整を行
うことにより急峻な濃度勾配をもつ多層な化合物
半導体層の成長を可能とする成長装置が提供され
る。
(g) Effects of the Invention According to the present invention, the upper reaction tube is made elongated, the lower reaction tube is provided with a liner tube, the top of the head is made transparent, and the temperature is adjusted using an infrared thermometer. A growth apparatus is provided that enables the growth of multilayer compound semiconductor layers with concentration gradients.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の結晶成長装置、第2図は本発明
に係る結晶成長装置また第3図は電界効果トラン
ジスタの実施例である。 図において1はウエハ、2は加熱台、4は熱電
対、5は反応容器6,16,17,18,19は
導入口、9はGaAsウエハ、10はバツフア層、
11は動作層、12は上部反応管、13は下部反
応管、14はライナ管。
FIG. 1 shows a conventional crystal growth apparatus, FIG. 2 shows a crystal growth apparatus according to the present invention, and FIG. 3 shows an embodiment of a field effect transistor. In the figure, 1 is a wafer, 2 is a heating table, 4 is a thermocouple, 5 is a reaction vessel 6, 16, 17, 18, 19 is an inlet, 9 is a GaAs wafer, 10 is a buffer layer,
11 is a working layer, 12 is an upper reaction tube, 13 is a lower reaction tube, and 14 is a liner tube.

Claims (1)

【特許請求の範囲】 1 保持棒3により保持されている加熱台2の上
にウエハ1を固定し、該加熱台2を中心として内
壁部に緩く嵌合するライナ管14を備え、外周部
に高周波誘導加熱用コイル21を備える下部反応
管13と、 該下部反応管13よりも内径が小さく、側面に
種類の異なる反応ガスが導入される複数のガス導
入管16,17,18,19を備え、上部に赤外
線温度計20によりウエハ1の温度測定を可能と
する頭頂部15を備えた上部反応管12とが接続
して設けられており、 前記複数のガス導入管16,17,18,19
より装置内に流入する反応ガス種の切り換えを行
うことにより急峻な濃度勾配をもち、多層構造を
した化合物半導体層をエピタキシヤル成長させる
ことを特徴とする結晶成長装置。
[Claims] 1. A wafer 1 is fixed on a heating table 2 held by a holding rod 3, and a liner tube 14 is provided that fits loosely into the inner wall around the heating table 2, and a liner tube 14 is provided on the outer periphery. A lower reaction tube 13 equipped with a high-frequency induction heating coil 21, and a plurality of gas introduction tubes 16, 17, 18, 19 having a smaller inner diameter than the lower reaction tube 13 and into which different types of reaction gases are introduced into the side surfaces. , an upper reaction tube 12 having a top portion 15 that enables temperature measurement of the wafer 1 with an infrared thermometer 20 is connected to the upper reaction tube 12, and the plurality of gas introduction tubes 16, 17, 18, 19 are connected to each other.
A crystal growth apparatus characterized by epitaxially growing a compound semiconductor layer having a steep concentration gradient and a multilayer structure by switching the type of reactive gas flowing into the apparatus.
JP3003482A 1982-02-26 1982-02-26 Crystal growth device Granted JPS58147112A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3003482A JPS58147112A (en) 1982-02-26 1982-02-26 Crystal growth device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3003482A JPS58147112A (en) 1982-02-26 1982-02-26 Crystal growth device

Publications (2)

Publication Number Publication Date
JPS58147112A JPS58147112A (en) 1983-09-01
JPH0136691B2 true JPH0136691B2 (en) 1989-08-02

Family

ID=12292530

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3003482A Granted JPS58147112A (en) 1982-02-26 1982-02-26 Crystal growth device

Country Status (1)

Country Link
JP (1) JPS58147112A (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5527241Y2 (en) * 1974-05-20 1980-06-30

Also Published As

Publication number Publication date
JPS58147112A (en) 1983-09-01

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