JPH01319841A - Buffer storing system - Google Patents

Abstract

PURPOSE:To execute the high speed of the subsequent series of the access by storing a series of the data word access related to the data describing wore, etc., and the access channel of the instruction word fetching for supplementing the instruction word. CONSTITUTION:The title system is composed of a data storing part 1a, a buffer storing part 1 composed of an address tag part 1b and a control part, a succeeding address storing part 2, a control information storing part 3, an address register 4, a request code register 5, a writing address register 6 of the succeeding address storing part 2 and the control information storing part 3, a writing data register 7 of the control information storing part 3, selectors 8-10 and a decoder 11. Here, the series of the data word access and the access channel of the instruction word fetching related by the data describing word, etc., are stored into the succeeding address storing part. Thus, the subsequent series of the access can be performed at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a buffer storage system, and particularly to a buffer storage system used in a central processing unit in a digital information processing device such as an electronic computer.

[Conventional technology]

In a central processing unit in a digital information processing device such as a computer, in order to substantially shorten the data access time to the main memory, data once read from the main memory and its address are provided near the central processing unit. A buffer memory device is used in which data is stored in a high-speed memory circuit, and data is retrieved from the memory circuit at high speed from the second and subsequent accesses.

Conventionally, in this type of buffer storage, only the address of the main memory access from the central processing unit, its data, and its control information are held, and the address of the main memory access from the central processing unit directly indicates the location of the data. If so, the central processing unit can immediately obtain the data necessary for execution.

However, in the case of indirect addressing, for example, where a data word is obtained via more than 11 data description words, the transfer of the data description word to the central processing unit, the data description using that data description word or the next data description. This requires overhead such as re-requesting words.

In other words, in conventional buffer storage devices, it is difficult to repeatedly access a series of data words related by data descriptors using the same address pattern, or to supply instruction words to the central processing unit in an instruction sequence with a loop structure. , required procedures such as address calculation and request for each access.

[Problems to be Solved by the Invention] The conventional buffer storage device described above stores only the address of main memory access from the central processing unit, its data, and its control information, so it cannot be associated with data descriptors or the like. For repeated accesses using the same address pattern for a series of data word accesses or for supplying instruction words to the central processing unit in a loop-structured instruction sequence, procedures such as address calculation and request are required for each access. This has the disadvantage that it cannot contribute to reducing overhead.

In view of the above-mentioned points, an object of the present invention is to store, in a subsequent address storage section, access paths for a series of data word accesses and instruction word replenishments that are related by data descriptor words, etc. The object of the present invention is to provide a buffer storage method that can speed up a series of subsequent accesses.

[Means to solve the problem]

The buffer storage system of the present invention includes a buffer storage section having a data storage section that holds a copy of a part of data in the main memory and an address tag section that holds a corresponding address, and each data in the data storage section. a subsequent address storage section that holds an address for a subsequent access following each data access corresponding to an entry in the data storage section; an address writing means that writes an address for a subsequent access into the subsequent address storage section; After accessing each data corresponding to a data entry, a control information storage section that holds control information for subsequent access, a data writing means that writes control information to this control information storage section, and a and data transfer means for successively transferring subsequent data from the data storage section to the central processing unit using the corresponding address in the subsequent address storage section at the time of access.

[Effect]

In the buffer storage system of the present invention, the buffer storage section has a data storage section that holds a copy of a part of data in main memory and an address tag section that holds a corresponding address, and the subsequent address storage section is a data storage section. 7 addresses of subsequent accesses are held in response to each data entry in the memory, the address writing means writes the address of the subsequent access to the subsequent address storage section, and the control information storage section holds control information for subsequent access following access to each data corresponding to each data entry in the data entry;
The data writing means writes control information to the control information storage section, and the data transfer means performs one data access in a series of data accesses.
At the time of data access, the corresponding address in the subsequent address storage section is used to successively transfer subsequent data from the data storage section to the central processing unit.

(Example〕 Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a circuit block diagram showing a buffer storage system according to an embodiment of the present invention. a buffer storage section 1, a subsequent address storage section 2, a control information storage section 3, an address register 4, a request code register 5, a write address register 6 of the subsequent address storage section 2 and the control information storage section 3, Write data register 7 of control information storage section 3 and selector 8
．． 9 and 10, and a decoder 11.

The address register 4 is a register for setting an address for main memory access, and is set when either an address from the central processing unit (CPU; not shown) or an address from the subsequent address storage unit 2 is selected by the selector 8. be done.

The request code register 5 is a register for setting a request code indicating the access type of the main memory access, and either the request code from the central processing unit or the request code generated by the decoder 11 is selected by the lid 9. is set.

The subsequent address storage section 2 has the same entry structure as the data storage section 1a of the buffer storage section 1, and each address in the subsequent address storage section 2 corresponds to each data in the data storage section la of the buffer storage section 1. The data access that corresponds to the entry and follows the access to each data (hereinafter, 9i
n access) is set.

The control information storage section 3 is a data storage section 1a of the buffer storage section 1.
It has the same entry structure as , corresponds to each entry in the subsequent address storage section 2, and various control information such as valid bits are set.

For example, the control information storage unit 3 uses one bit as a valid bit to identify whether the request is a data description word fetch or a data word fetch when fetching data, and checks the valid bit of the corresponding entry when making a write request. However, if the data description word indicating the position of the data word is rewritten, this valid bit is reset to maintain the validity of the data word. Also, when fetching an instruction word, one bit is used as an effective pin to identify whether the instruction word is fetched immediately after a branch instruction or the instruction word fetched on the branch destination side. bit “1”
”, and when the instruction word from this entry is transferred, it is reported to the central processing unit that it is the first instruction of the branch destination.

This allows the central processing unit to check the validity of the command.

Next, the operation of the buffer storage system of this embodiment configured as described above will be explained.

Now, when the central processing unit issues a request for data word access or instruction word fetch in continuous mode using a data description word, etc., the address is sent to the address register 4 via the selector 8, and the request code is sent to the selector 9.
The buffer storage unit 1 is accessed using this information, and if a matching address is registered in the address tag unit 1b, the corresponding entry in the data storage unit 1a is set. data words or command words are transferred to the central processing unit as read data.

On the other hand, at this time, the address register 4 which is the address used to access the data storage section la of the buffer storage section 1
The contents of are sent to the write address register 6 as the write address of the subsequent address storage section 2 and control information storage section 3. Further, the matching information of the request code from the request code register 5 and the address tag section 1b from the buffer storage section 1 is sent to the write data register 7 via the decoder 11 as write data to the control information storage section 3. .

Thereafter, when the central processing unit issues a request for data word access or subsequent instruction word fetch using the data description word obtained from the previous request, the previous access address whose address is held in the write address register 6 is issued. The contents of the address register 4, which is the address of the subsequent access, are set in the entry of the subsequent address storage unit 2, and the valid bit of the subsequent access is set in the entry of the control information storage unit 3 of the previous access whose address is held in the write address register 6. The contents of the write data register 7 including control information such as the following are set.

At this time, if the subsequent access is again a data word access or instruction word fetch in continuous mode, the address and request code of the subsequent access are set in the write address register 6 and write data register 7, respectively, as in the case of the previous access. Ru.

After the address and control information for the subsequent access are set in the subsequent address storage section 2 and the control information storage section 3 in this way, the central processing unit again stores the data at the same address in the continuous mode associated by the data descriptor, etc. When a request for word access or instruction word fetch of the same address is issued, the address is set in the address register 4 via the selector 8, the request code is set in the request code register 5 via the selector 9, and these pieces of information are set. The buffer storage unit 1 is accessed using the buffer storage unit 1, and the read data is transferred to the central processing unit.

At the same time, the entries in the subsequent address storage section 2 and control information storage section 3 corresponding to the read data are read out via the selector 10 using the address that is the contents of the address register 4.

The address of the subsequent access read from the subsequent address storage section 2 is sent to the address register 4 via the selector 8.
is set to Further, the decoder 11 can transfer subsequent data using the control information such as the valid bit of the subsequent access read from the control information storage section 3 and the matching information of the address tag section 1b from the buffer storage section 1. It detects this, generates a request code, and sets it in the request code register 5 via the selector 9.

Therefore, the buffer storage unit 1 is immediately accessed from the subsequent access address set in the address register 4, and the subsequent instruction word or data word can be transferred to the central processing unit together with the address.

Further, the decoder 11 notifies the central processing unit that it is a continuous data reply using the subsequent address storage unit 2, and suppresses subsequent unnecessary requests.

FIG. 2 is a diagram showing an example of accessing a data narrative via two data description words II and I2.
Procedures for data descriptor requests REQ1 and REQ2 and data request REQ3 are required.
In the second and subsequent accesses to the data narrative, two data description words 1 and I2 and the data narrative can be obtained with one request REQI.

FIG. 3 shows a list structured data word (11, DI).

(12, N2), N3. N3), . . . with reference to the data word group DI, D2. D3. . . . In the second and subsequent accesses, a series of list-structured data words (It, D
I), (12,N2), (13°N3),...
・Can be obtained immediately.

Figure 4 shows the data description word table (II, 12°[3,
...) with reference to the data word group DI, D2°N3.・
. . . In the second and subsequent accesses, a series of data words T is received with one request REQI.
I, DI, I2. N2. I3°N3.・
... can be obtained immediately.

FIG. 5 is a diagram showing an example of fetching instruction words A to F including a conditional branch instruction talker, and in the second and subsequent accesses, the delay in fetching the instruction word due to waiting for confirmation of the branch condition of the conditional branch instruction talker is shortened. be able to.

〔Effect of the invention〕

As explained above, the present invention stores a series of data word accesses and instruction word fetch access paths related by data description words etc. in the subsequent address storage unit, thereby providing a series of data word accesses and instruction word fetches related by data description words etc. When accessing data words repeatedly with the same address pattern or supplying instruction words to the central processing unit in an instruction sequence with a loop structure, it is no longer necessary to perform procedures such as address calculation and requests for each access from the second time onwards. This has the effect of speeding up a series of subsequent accesses.

[Brief explanation of the drawing]

Fig. 1 is a circuit block diagram showing a buffer storage system according to an embodiment of the present invention, Fig. 2 is a diagram for explaining an example of data word access via a data description word, and Fig. 3 is a list structure. FIG. 4 is a diagram for explaining an example of accessing a data word group by referring to a data word table. FIG. 4 is a diagram for explaining an example of accessing a data word group by referring to a data description word table. FIG. 3 is a diagram for explaining an example of an instruction word including a conditional branch instruction word. In the figure, 1... buffer storage section, 1a... data storage section, 1b... address tag section, 2... subsequent address storage section, 3... control information storage section, 4-7. register, 8 ~10 Selector, 11 Decoder.

Claims (1)

[Scope of Claims] A buffer storage section having a data storage section that holds a copy of a portion of data in main memory and an address tag section that holds a corresponding address; and an entry for each data in the data storage section. a subsequent address storage section that holds an address for a subsequent access following each data access corresponding to the data storage section; an address writing means for writing an address for a subsequent access into the subsequent address storage section; an entry for each data in the data storage section; a control information storage section that holds control information for subsequent access following each data access in response to the data access, and a data writing means that writes control information into the control information storage section that corresponds to one data access in a series of data accesses. A buffer storage system comprising: data transfer means for successively transferring subsequent data from the data storage section to a central processing unit using addresses in the subsequent address storage section.