JPH01318355A - Television receiver - Google Patents

Television receiver

Info

Publication number
JPH01318355A
JPH01318355A JP63150663A JP15066388A JPH01318355A JP H01318355 A JPH01318355 A JP H01318355A JP 63150663 A JP63150663 A JP 63150663A JP 15066388 A JP15066388 A JP 15066388A JP H01318355 A JPH01318355 A JP H01318355A
Authority
JP
Japan
Prior art keywords
blanking
horizontal
circuit
capacitor
video signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63150663A
Other languages
Japanese (ja)
Other versions
JP2770323B2 (en
Inventor
Makoto Kawachi
誠 河内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP63150663A priority Critical patent/JP2770323B2/en
Publication of JPH01318355A publication Critical patent/JPH01318355A/en
Application granted granted Critical
Publication of JP2770323B2 publication Critical patent/JP2770323B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To eliminate the blanking disturbance by switching the frequency characteristic of a video signal amplifying circuit so that its band in the horizontal scanning time is wider than that in the horizontal flyback time. CONSTITUTION:A horizontal blanking pulse applied to a blanking circuit 30 is divided by resistances 2 and 3 and passes a speed up capacitor 1 to switch a transistor TR 5. A capacitor 7 connected to the collector of the TR 6 performs the integral action together with a resistance 32 only in the horizontal flyback time of an R signal. While the TR 5 is turned on, the leading edge is made wider than the horizontal blanking time by the speed up capacitor 1 and the trailing edge is made wider than that by increasing the extent of base drive of the TR 5 to use the delay from switching-on to switching-off. Thus, higher harmonics generated in leading and trailing edge parts of blanking pulses are reduced.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、テレビジョン受像機等における映像信号増幅
回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a video signal amplification circuit in a television receiver or the like.

従来の技術 近年、テレビジョン受像機は、大画面化及び高画質化の
方向にある。特に水平解像度の向上は著しいものがある
。また、最近では、デジタル技術(メモリー)を駆使し
て、倍密方式のテレビジョン受像機が開発されている。
BACKGROUND OF THE INVENTION In recent years, television receivers are becoming larger in screen size and in higher image quality. In particular, the improvement in horizontal resolution is remarkable. Recently, double-density television receivers have been developed by making full use of digital technology (memory).

これは従来の525本インターレース走査よシ、信号及
び走査スピー−りに【 ドを2倍にして行う525本ノンインターレース方式の
ものである。
This is a 525-line non-interlaced system in which the signal and scanning speed are doubled compared to the conventional 525-line interlaced scan.

以下図面を参照しながら、上述した従来のテレビジョン
受像機の一例について説明する。
An example of the conventional television receiver mentioned above will be described below with reference to the drawings.

第3図、第4図は従来の倍密方式のテレビジョン受像機
のブロック図及び映像信号増幅回路の一例を示すもので
ある。第3図において、2oはアンチf (ANT )
 、 21はチt −−j−、22idVIF回路で、
放送されている電波を受信し所望のチャンネルのビデオ
信号を得る。23はローパスフィルタ(LPF)、24
はアナログ/デジタル変換器(A/D)、25はメモリ
、26はデジタ/I//アナログ変換器(D/A)、2
7はローパスフィルタ(LPF )で、525本のノン
インターレーヌ走査を行うために、ビデオ信号を2倍の
スピードにするためのものである。これはA/D変換器
24でデジタル値に変換された信号をメモリ25にクロ
ック周波数fWのサンプリング周波数で書き込み、クロ
ック周波数fRのサンプリング周波数で読み出すように
し、fWとfRの関係を2fw=fRにすることによっ
て行っている。まり、ローパスフィルり23及U27は
、A/D変換器24及びD/A変換器26で発生する折
シ返し雑音を防止するためのもので、その特性は各ブロ
ックの中に示した周波数−振幅特性が一般的である。
FIGS. 3 and 4 show a block diagram of a conventional double-density television receiver and an example of a video signal amplification circuit. In Figure 3, 2o is anti-f (ANT)
, 21 is a t--j-, 22id VIF circuit,
Receive the broadcast radio waves and obtain the video signal of the desired channel. 23 is a low pass filter (LPF), 24
is an analog/digital converter (A/D), 25 is a memory, 26 is a digital/I//analog converter (D/A), 2
7 is a low pass filter (LPF) for doubling the speed of the video signal in order to perform 525 non-interlaced scans. This is done by writing the signal converted into a digital value by the A/D converter 24 into the memory 25 at the sampling frequency of the clock frequency fW, and reading it out at the sampling frequency of the clock frequency fR, so that the relationship between fW and fR becomes 2fw=fR. This is done by doing. In other words, the low-pass filter 23 and U27 are for preventing aliasing noise generated in the A/D converter 24 and the D/A converter 26, and their characteristics are based on the frequencies shown in each block. Amplitude characteristics are common.

28は映像信号増幅回路、29は陰極線管(CRT)で
ある。映像信号増幅回路28は2倍のスピードにされた
信号に帰線消去パルスを加え、CRT 29を駆動する
に必要な振幅(約5o倍のゲインで百数士ボルト)まで
増幅する。また周波数特性は525本インターレーヌ方
式のテレビジョン受像機のものと比べて2倍以上の帯域
(少なくともカットオフ周波数、fR以上)をもつ。
28 is a video signal amplification circuit, and 29 is a cathode ray tube (CRT). The video signal amplification circuit 28 adds a blanking pulse to the doubled speed signal and amplifies it to the amplitude necessary to drive the CRT 29 (more than 100 volts with a gain of about 50 times). Furthermore, the frequency characteristic has a band that is more than twice as large as that of a 525-line interlane television receiver (at least the cutoff frequency, fR or more).

第4図は第3図の映像増幅回路28の一例を示すもので
あシ、30は帰線消去回路、32〜37は抵抗、38〜
41はトランジスタで、R信号プリアンプ回路を構成す
る。42〜44は抵抗。
FIG. 4 shows an example of the video amplification circuit 28 in FIG.
A transistor 41 constitutes an R signal preamplifier circuit. 42 to 44 are resistances.

45はコンデンサ、46及び47はダイオード。45 is a capacitor, 46 and 47 are diodes.

48〜51はトランジスタで、R信号メインアンプ回路
を構成するものである。
Reference numerals 48 to 51 indicate transistors, which constitute an R signal main amplifier circuit.

52はR信号プリアンプ回路の電源、53はR信号メイ
ンアンプ回路の電源、54はトランジスタ49のペース
に加える直流バイアス電源である。
52 is a power supply for the R signal preamplifier circuit, 53 is a power supply for the R signal main amplifier circuit, and 54 is a DC bias power supply that is added to the pace of the transistor 49.

尚、G信号及びB信号のプリアンプ及びメインアンプは
R信号のものと同じ回路構成なので図面への記載は省略
している。
Note that the preamplifier and main amplifier for the G signal and B signal have the same circuit configuration as that for the R signal, so their description in the drawings is omitted.

発明が解決しようとする課題 しかしながら、上記のような構成では、ブランキング妨
害が発生し、画面中央部に縦線の妨害が発生して非常に
見づらくなるという問題点を有していた。このブランキ
ング妨害発生の理由について、第2図の波形図を参照し
ながら説明する。第2図において、Aはノーマ/L/R
信号波形、Bは倍速R信号波形、Cは帰線消去パルスで
ある。   ・帰線消去パルスCによシ倍速R信号波形
すの破線信号部(水平帰線期間)は実線のように第4図
の帰線消去回路30でブランキングされる。
Problems to be Solved by the Invention However, the above configuration has the problem that blanking interference occurs and vertical line interference occurs in the center of the screen, making it extremely difficult to see. The reason why this blanking interference occurs will be explained with reference to the waveform diagram in FIG. 2. In Figure 2, A is normal/L/R
The signal waveform, B is a double speed R signal waveform, and C is a blanking pulse. - The dotted line signal portion (horizontal blanking period) of the double-speed R signal waveform is blanked by the blanking pulse C as shown by the solid line by the blanking circuit 30 in FIG.

この倍速R信号波形すは、第4図のプリアンプ回路で数
倍、メインアンプ回路で数十倍増幅され5 ・ るが、特にプランキングパルヌの立ち上シ、立ち下シは
、帯域制限されていないので周波数特性に秀れ、さらに
、その振幅も数十ボtl−〜数百ボルトは常にある。よ
って、このプランキングパルヌの立ち上シ、立ち下りで
高調波が発生し、テレビジョン受像機のRF入カケ−プ
ルやチューナ21゜VIP22等、A/D変換されるま
でのステージに飛び込み、第2図のノーマ/L/R信号
波形中の■で示すブランキング妨害となシ、さらに倍速
R信号波形中の■で示す位置に妨害として現れる。
This double-speed R signal waveform is amplified several times by the preamplifier circuit in Figure 4, and several tens of times by the main amplifier circuit5. It has excellent frequency characteristics, and its amplitude is always in the range of several tens of volts to several hundred volts. Therefore, harmonics are generated at the rising and falling edges of this planking pulse, and they flow into the RF input cable of the television receiver, the tuner 21° VIP 22, etc., and enter the stages before A/D conversion. The blanking disturbance shown by ■ in the normal/L/R signal waveform in FIG. 2 further appears as a disturbance at the position shown by ■ in the double speed R signal waveform.

以上のことから、秀れた周波数特性と、なおかつ妨害の
出ない映像信号増幅回路をもつテレビジョン受像機の開
発が望まれていた。
For these reasons, it has been desired to develop a television receiver that has excellent frequency characteristics and a video signal amplification circuit that does not cause interference.

本発明は上記問題点に鑑み、所望する信号の周波数帯域
を十分に保ちながら増幅することができるとともに、こ
の秀れた周波数特性が要因となって発生する不要なブラ
ンキング妨害を防止した映、像信号増幅回路をもつテレ
ビジョン受像機を提供することを目的とするものである
In view of the above-mentioned problems, the present invention has been developed to amplify a desired signal while sufficiently maintaining its frequency band, and to prevent unnecessary blanking interference caused by this excellent frequency characteristic. The object of the present invention is to provide a television receiver having an image signal amplification circuit.

課題を解決するだめの手段 66、、、ノ 上記問題点を解決するために、本発明のテレビジョン受
像機は、映像信号増幅回路を備え、この映像信号増幅回
路の周波数特性を水平帰線期間中よシ水平走査期間中の
方を広帯域にするように切換える制御回路を備えた構成
にしたものである。
Means for Solving the Problems 66. In order to solve the above problems, the television receiver of the present invention is provided with a video signal amplification circuit, and the frequency characteristics of the video signal amplification circuit are adjusted to the horizontal retrace period. The configuration is equipped with a control circuit that switches to a wide band during the middle and horizontal scanning periods.

作  用 本発明は、上記した構成によって、所望する信号の周波
数帯域をもつ広い周波数特性を水平走査期間のみに持た
せ、不要なブランキング妨害発生の要因となる水平帰線
期間、特に水平帰線消去信号の立ち上シ/立ち下9部分
では、前記第1の周波数帯域よシ狭い周波数特性を持た
せるようにしたことにより、不要なブランキング妨害の
出ない映像信号を映出できることとなる。
Effect of the Invention With the above-described configuration, the present invention provides a wide frequency characteristic with a desired signal frequency band only in the horizontal scanning period, and eliminates the horizontal retrace period, especially the horizontal retrace line, which is a cause of unnecessary blanking interference. Since the rising edge/falling edge 9 portion of the erasing signal has a narrower frequency characteristic than the first frequency band, it is possible to display a video signal without unnecessary blanking interference.

実施例 以下、本発明の一実施例のテレビジョン受像機について
、図面を参照しながら説明する。
Embodiment Hereinafter, a television receiver according to an embodiment of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例におけるテレビジョン受像機
の映像信号増幅回路の回路図を示すものである。第1図
において、1はスピードアソプコ7、、−。
FIG. 1 shows a circuit diagram of a video signal amplification circuit for a television receiver according to an embodiment of the present invention. In FIG. 1, 1 is Speed Asopco 7, -.

ンデンサ、2〜4は抵抗、5はトランジスタ、6はダイ
オード、7はコンデンサである。その他第4図と同一機
能の部品には同じ番号を付記し説明は省略する。
2 to 4 are resistors, 5 is a transistor, 6 is a diode, and 7 is a capacitor. Other parts having the same functions as those in FIG. 4 are given the same numbers and their explanations will be omitted.

以上のように構成されたテレビジョン受像機の映像信号
増幅回路について、以下その動作について説明する。ま
ず、帰線消去回路3oに加える水平帰線消去パルスを、
抵抗2及び3で抵抗分割し、スピードアンプコンデンサ
1を介することでトランジスタ6をスイッチングさせる
。このトランジスタ5のコレクタに接続しであるコンデ
ンサ7は、抵抗32とともにR信号の水平帰線期間のみ
、積分動作を行う。ダイオード6はトランジスタ5のオ
ン期間に交流ヌイノチとして動作させるものである。
The operation of the video signal amplification circuit of the television receiver configured as described above will be explained below. First, the horizontal blanking pulse applied to the blanking circuit 3o is
The resistance is divided by resistors 2 and 3, and the transistor 6 is switched via the speed amplifier capacitor 1. A capacitor 7 connected to the collector of the transistor 5, together with a resistor 32, performs an integrating operation only during the horizontal retrace period of the R signal. The diode 6 is operated as an AC diode during the on period of the transistor 5.

尚、トランジスタ50オン期間は、帰線消去回路3oで
行う水平帰線消去期間より幅広いものとするため、水平
帰線消去パルスの前縁はスピードアンプコンデンサ1に
より、また外縁は、トランジスタ5のベースドライフ量
をオーバー目にし、スイッチングのオンからオフのデレ
ーを利用スることで確保している。
Note that since the on-period of the transistor 50 is wider than the horizontal blanking period performed by the blanking circuit 3o, the leading edge of the horizontal blanking pulse is connected to the speed amplifier capacitor 1, and the outer edge is connected to the base voltage of the transistor 5. It is secured by seeing the amount of life exceed and using the delay from switching on to off.

尚、R信号系のみについて説明しだが、同様に、G信号
及びB信号についても第1図中の破線で示す水平帰線期
間周波数特性切換回路が必要である。
Although only the R signal system has been described, the horizontal retrace period frequency characteristic switching circuit shown by the broken line in FIG. 1 is also required for the G and B signals.

以上のように、本実施例によれば、水平帰線期間のみ周
波数特性を狭くするように切換えることにより、信号の
内帯域制限を受けていないブランキングパルスの立ち上
り及び立ち下シエノジ部で発生する高調波を低減するこ
とができ、この高調波により発生するブランキング妨害
のないテレビジョン受像機を提供することができる。
As described above, according to this embodiment, by switching to narrow the frequency characteristics only during the horizontal retrace period, the blanking pulse that is not subject to the inner band restriction of the signal can be suppressed at the rising and falling edges. It is possible to provide a television receiver that can reduce harmonics and is free from blanking interference caused by these harmonics.

なお、本実施例では、抵抗とコンデンサを使用して周波
数特性を切換えたが、他の手段でもよい。
In this embodiment, the frequency characteristics are switched using a resistor and a capacitor, but other means may be used.

また本実施例では、帰線消去回路の直後で行い一番好し
いが、後段でもか捷わない。但し大振幅に増幅される以
前が好ましい。
Further, in this embodiment, it is most preferable to perform the switching immediately after the blanking circuit, but it may also be performed at a later stage. However, it is preferable before the signal is amplified to a large amplitude.

発明の効果 以上のように、本発明は、映像信号増幅回路の周波数特
性を水平帰線期間中より水平走査間中の9 /、− 方で広帯域にするように切換える制御回路を備えること
により、所望の映像信号増幅回路の周波数特性を制限さ
れることなく自由に選べ、なおかつ、帰線消去パルスの
前縁あるいは後縁部より発生する高調波が原因のブラン
キング妨害をなくすることができ、その実用的効果は大
なるものがある。
Effects of the Invention As described above, the present invention includes a control circuit that switches the frequency characteristics of the video signal amplification circuit to a wider band during horizontal scanning than during the horizontal retrace period. The frequency characteristics of the desired video signal amplification circuit can be freely selected without being restricted, and blanking interference caused by harmonics generated from the leading or trailing edge of the blanking pulse can be eliminated. Its practical effects are significant.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例におけるテレビジョン受像機
の映像信号増幅回路の回路図、第2図はその動作説明用
の波形図、第3図は従来例のテレビジョン受像機のブロ
ック図、第4図は従来例のテレビジョン受像機の映像信
号増幅回路の回路図である。 1・・・・・・スピードアップコンデンサ、2〜4゜3
2〜37及び42〜44・・・・・・抵抗、6,38〜
41及び48〜51・・・・・トランジスタ、7.45
・・・・・・コンデンサ、6,46.47・・・・・・
ダイオード、29・・・・CRTo
FIG. 1 is a circuit diagram of a video signal amplification circuit of a television receiver according to an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining its operation, and FIG. 3 is a block diagram of a conventional television receiver. , FIG. 4 is a circuit diagram of a video signal amplification circuit of a conventional television receiver. 1...Speed up capacitor, 2~4゜3
2-37 and 42-44...Resistance, 6,38-
41 and 48-51...transistor, 7.45
・・・・・・Capacitor, 6,46.47・・・・・・
Diode, 29...CRTo

Claims (1)

【特許請求の範囲】[Claims] 陰極線管を駆動する映像信号増幅回路を備え、前記映像
信号増幅回路の周波数特性を水平帰線期間中よりも水平
走査期間で広帯域にするように切換える制御回路を備え
たことを特徴とするテレビジョン受像機。
A television comprising a video signal amplification circuit that drives a cathode ray tube, and a control circuit that switches the frequency characteristics of the video signal amplification circuit to have a wider band during a horizontal scanning period than during a horizontal retrace period. receiver.
JP63150663A 1988-06-17 1988-06-17 Television receiver Expired - Lifetime JP2770323B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63150663A JP2770323B2 (en) 1988-06-17 1988-06-17 Television receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63150663A JP2770323B2 (en) 1988-06-17 1988-06-17 Television receiver

Publications (2)

Publication Number Publication Date
JPH01318355A true JPH01318355A (en) 1989-12-22
JP2770323B2 JP2770323B2 (en) 1998-07-02

Family

ID=15501766

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63150663A Expired - Lifetime JP2770323B2 (en) 1988-06-17 1988-06-17 Television receiver

Country Status (1)

Country Link
JP (1) JP2770323B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH021019U (en) * 1988-06-14 1990-01-08
JPH021170U (en) * 1988-06-14 1990-01-08

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH021019U (en) * 1988-06-14 1990-01-08
JPH021170U (en) * 1988-06-14 1990-01-08

Also Published As

Publication number Publication date
JP2770323B2 (en) 1998-07-02

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