JPH0131806B2 - - Google Patents

Abstract

1. A consumer electronics receiver - with an electronically tunable tuner circuit (1), - also with an automatically settable tuning circuit (7, 51) connected to one tuning input (2) of the tuner circuit, comprising a start input (11) for tripping a new tuning setting, - furthermore with a data separating circuit (16) connected to a signal path (5) connected after the tuner circuit (1) which, from a composite signal present on the signal path (5), separates a station program data record (12) marked by a special type-of-record identification word (13) containing station identification words (14) and station program words (15) in digital signal form and which, moreover, transmits at one data output (D16) the data words contained in the data record, and produces at one clock output (T16) the call clock required for the data output, - and with an evaluating circuit connected to the data output and the call clock output of the data separating circuit (16), in which selected station program data are stored and in which the data of the received station program data record are evaluated with the aid of the selected station program data, characterized in - that the evaluating circuit contains a first storage circuit (18) connected to the data output (D16) of the said data separating circuit (16), for the received station program data (14, 15), with a connected read-in control circuit (20), a second storage circuit (34) for storing the selected station program data, with, connected to it, a readout control circuit (39) which is controlled by a clock pulse generator (40), and a comparator (31) connected between the data outputs (29, 33) of said two storage circuits, - that the output (T16) for the call clock of the data separating circuit is connected to one clock input (T20) of the read-in control circuit (20), - that to the read-in control circuit (20) there is connected a pulse delay circuit (26, 54) which is capable of being triggered by a signal from said read-in control circuit (20) and, after a time delay (T26) which is equal to or greater than the sum of the time remaining after the trigger signal for reading into the first storage circuit for the received station programm data and the read-out time of the two storage circuits, produces an output signal, - that the output of said pulse delay circuit (26, 54) is connected, via a gate circuit (47), to the start input (9, 52) of said tuning circuit (7), - that there is connected to the output (37) of the comparator (31) a pulse expander circuit (38) which, at its output, expands each pulse on the input side to a pulse width which is greater than the time between the beginning of two successive processes of reading into the first storage circuit (18) for the received station program data, - that the output of the pulse expander circuit is connected to the blocking input (Sp) of the gate circuit (47) and - that to one read signal output (53) of the read-in control circuit (20) and to the output of the pulse expander circuit (38) there is connected a logic operation circuit (42) which, in response to a signal appearing at one of the two outputs, puts said comparator (31) into operation.

Description

TECHNICAL FIELD The present invention relates to a consumer electronic device receiver having an electronically tunable tuner circuit.

Prior Art Such receivers are known, for example, from German Open
It is known from No. 3020787. Here, a data separation circuit for detecting a data recorder contained in the video signal and separating it from the video signal is connected to a signal path for video signal transmission in a known receiver via an amplifier. In known receiving circuits, the data separation circuit is controlled by a window circuit which scans the data separation circuit according to the time interval of the video synchronization pulse, so that the data separation circuit is sensitive to the additional information transmitted in the rows of association. only respond. The data records separated by the data separation circuit contain, in addition to a record identification word that identifies the type of separated data record, receiving station identification information, station program identification information, and, in some cases, the transmitting station and its broadcasts. Also includes other information about the program. The information sorted in the data separation circuit and the ring clock pulses formed from this information are transmitted to the arithmetic circuitry in a known receiving circuit, which includes a keyboard for programming the arithmetic circuitry.

A video text (teletext) decoder used in conjunction with a television receiver, including a data separation circuit that connects to the signal path of the television receiver, is described in the Volvo publication ``Technician Informatsionen Fuerdei''. Technische Informationen fu¨r
die Industrie) No. 800407. A call clock pulse generator is synchronized to the video text (teletext) data and the video text (teletext) data is compared with constant data in a remotely programmable storage device (memory) while passing through a comparison circuit. and controls input to the data storage device based on the result of this comparison.
For this input or write operation, a read control circuit is provided in the data storage device. The readout of the data storage device to a signal generator of known construction is controlled by a readout control circuit to which a readout clock generator is connected.

OBJECT OF THE INVENTION The object of the present invention is to provide a receiver as described above.
To provide an arithmetic circuit that calculates data sentences (or records) separated from a mixed signal appearing in a signal path of a receiver by a data separation circuit in order to identify a station program in light of a preselected station setting. be.

Structure and Effects of the Invention In the present invention, this object is achieved by the constituent elements described as features in Claims 1 and 2.

Adopting the idea of the invention, it is possible to call up transmitting station programs at short time intervals, and to make automatic calls to the selected station as soon as a match between the selected program data and the received station data is detected in the comparator circuit. It is possible to extremely easily configure an arithmetic circuit that enables precise tuning. The circuit arrangement of the present invention can also be configured to be part of a microprocessor.

Preferred embodiments of the present invention are described in the second and subsequent claims.

Embodiments The present invention will be described in detail below based on preferred embodiments shown in FIGS. 1 to 5 of the accompanying drawings.

The embodiment of the radio and/or television program receiver shown in FIG.
It includes a tuning circuit 1 which is able to tune to the (transmission) station of the carrier wave received at the antenna input 3 by U _Abst and which is further able to transfer the intermediate frequency signal to a subsequent intermediate frequency and demodulation circuit 4. circuit 4
forms a mixed signal in the signal path 5 passing to the regeneration circuit 6. A tuning output 8 of a tuning circuit 7 is connected to a tuning input 2 of the tuning circuit 1 . In the embodiment shown, the tuning circuit 7 is activated by a signal appearing at the activation input 9, for example from the circuit 4 to the line 10.
This is an automatic tuning circuit that is stopped and readjusted by a discrimination signal that appears at the stop input 11 through the above.

The mixed signal formed in the signal path 5 in response to the broadcast transmitted from the station to which the tuning circuit 1 is tuned includes a record (sentence) identification code for identifying the type of data record. A transmitting station program data record 12 as shown schematically in FIG. 2 is included in a special signal waveform. This record identification code is followed by a station identification code 14 which identifies the transmitting station from which it was received. Following the station identification code 14 is a station program word 15, which identifies the broadcast program of the identified (transmitting) station by, for example, data regarding the program number or broadcast date and time contained in the program transmitted from the station. A data separation circuit 16 is connected to the signal path 5 to separate this data sentence or record from the mixed signal. In the illustrated embodiment, this data separation circuit 16 is a data separation circuit of a videotext (teletext) decoder 17, which in the case of videotext (teletext) data sentences or records forms an output signal at the output KV and In the case of program data sentences or records 12, an output signal is formed at the output KS. This data separation circuit also forms, at a data output D16, the ordered data words contained in the data record 12 and, at a clock output T16, separates the data record for storage in a storage circuit 18 connected to the data output D16. form a ring clock based on the transmission of The calling clock of the data separation circuit is supplied via the gate circuit 19 to the clock input T20 of the read control circuit 20 of the storage circuit 18. During the operation of the automatic tuning circuit 7, this reading control circuit is blocked by the blocking circuit 21, and in the unblocked state is controlled by the data separation circuit 16 via the control circuit 22.
This read control circuit 20 controls reading (storage) to the storage circuit 18 in accordance with the call clock and the control signal appearing at the output KS of the data separation circuit. As soon as the storage circuit 18 is ready for reading, the read control circuit 20 forms a short all-select recall pulse 24 at the output 23, which triggers the pulse delay circuit 26 via the line 25 and triggers the bistable trigger circuit. (Flip-flop) 27 is switched to set position S. Circuits 26, 27, and circuit 2
The gate circuits 28 following 6 all form part of the read control circuit 20.

Storage circuit 1 for program data of received stations
A comparator circuit 31 is connected to the data input 30 on the data output 29 side of the comparator 8, and the second data input 3 of the comparator circuit
2 is connected to a data output 33 of a storage circuit 34 for selected station program data. Data relating to the programs and stations selected by the user from the radio and TV channels and stored in the receiver are stored in the storage circuit 36 via the data input 35 in a manner not described in detail here. When a control signal appears at control input 35, comparator circuit 31 outputs its output 37 if the data at data inputs 30, 32 match at the time of comparison.
generates a signal. Each output signal of the comparator circuit 31 is expanded to the adjusted pulse width t38 in a subsequent pulse expansion circuit 38. A clock pulse generator 40 generates a clock signal via a gate circuit 41.
A readout control circuit 39 controlled by a pulse input T39 controls the selected program data storage circuit 34, and in response to each clock, the program data of a new storage line of the storage circuit 34 is supplied to the data input 32 of the comparison circuit 31. . A logic circuit 42 is interposed between the outputs of the read control circuits 20 to 28, the control inputs of the comparison circuit 31, the inputs and outputs of the read control circuits 39 and 41, and the output of the pulse expansion circuit 38, and in the illustrated embodiment,
This logic circuit 42 mainly consists of an OR circuit 43 and an electronic switch 44 including an electronic final control element 45.

The all-select call pulse 24 of the read control circuit 20 resets the read control circuit 39 to its initial position at its reset input RS. Since the triggered bistable trigger circuit 27 unblocks the block input S _p 41 of the gate circuit 41, the clock pulse generator 40 times the readout control circuit 39 and thus the clock pulses stored in the storage circuit 34. The selected program data is sequentially supplied to the data input 32 of the comparison circuit 31. At the same time, the clock of clock pulse generator 40 forms a read clock signal at read clock output LT39 of read control circuit 39, which clock signal is applied via switch 44 to clock input 36 of comparator circuit 31. . If a match is not detected in the comparator circuit 31, the read control circuit 39 passes through all memory rows occupying the memory circuit 34 and forms a control signal at the final output 46 as soon as the pass is completed; The bistable trigger circuit 27 is reset to the RS position and blocks the clock pulses of the clock pulse generator 40 at the block input S _p 41 of the gate circuit 41, and the control signal is passed through the gate circuit 47 to the tuned circuit 7. Trigger a new automatic tuning operation as an activation signal at activation input 9 of.

When a match in the station program data is detected by comparison and an output signal is generated at the output 37 of the comparison circuit 31 and supplied to the data inputs 30 and 32, the pulse expansion circuit 38
The output signal of the clock pulse generator 40 reaches the storage circuit 34 through the OR circuit 43 and the gate circuit 41, and the control input 36 of the comparison circuit is read through the switch 44. It is connected to the read output 23 and makes the gate circuit 28 conductive with respect to the output signal of the pulse delay circuit 26. The output pulse of the pulse delay circuit 26 resets the bistable trigger circuit 27 to the RS position, thereby triggering a new read operation in the read control circuit 20 via the previously blocked gate circuit 19. The time delay t26 of the pulse delay circuit 26 determines the time interval between two storage operations to the storage circuit 18 performed one after the other. In the illustrated embodiment, the pulse width t38 of the pulse stretching circuit 38 corresponds to a multiple of the time interval t26, so that the circuit remains inactive in the event that no comparison signal appears at the output 37 of the comparison circuit 31. can do.
The gate circuit 47, which is blocked in this state, prevents the termination signal appearing at the output 46 of the read control circuit 39 from reaching the activation input 9 of the tuning circuit 7.

Once the selected program broadcast by the station to which the tuning circuit 1 is tuned ends, the program word transmitted by the station to identify the broadcast program will no longer be transmitted, so that from this point onwards the output of the comparison circuit 31 is No output pulse appears at 37, and after the pulse extension time t38 has elapsed, the output signal of the pulse extension circuit is cut off. The trailing edge of the output signal of the pulse stretching circuit 38 generates an output pulse in the differentiating circuit 48 which, in the illustrated embodiment, is applied to the erase input Lo 39 of the read control circuit 39 and is present at the output of the storage circuit 34. Erase memory rows.

The receiver shown as an embodiment in FIG. 3 has the following features: the data output 33 of the selected station program data storage circuit 34 is connected to the data input 32 of the comparison circuit 31 via the electronic switch 50 during the comparison operation; 7
It differs from the receiver shown in FIG. 1 in that it is of the continuous switching type with a fixed station storage circuit 51 at clock input 52 in which each clock pulse calls for tuning the next stored fixed station. The read control circuit 20' forms a read signal at its read output 53, which read signal is transmitted to the program storage circuit 1.
8 is always on standby as long as the station program data stored in 8 is available at its data output 29. In place of the pulse delay circuit 26 in the embodiment shown in FIG. 1, the embodiment of FIG.
After 26, an output signal is formed for resetting the read control circuit 20' and for acting as a step signal appearing at the clock input 52 of the continuously switchable fixed station storage circuit 51. Therefore, because of the tuning voltage circuit, this step signal is different from the embodiment shown in FIG.
Not formed by.

While the comparison operation of the comparison circuit is awaited, that is,
While the read control circuit is generating a signal at its read output 53 or while the pulse stretching circuit 38 is generating a signal, the data output 33 of the storage circuit 34 is connected via the electronic switch 50 to the data input of the comparator circuit. 32, and the read clock output LT39 is connected to the control input 3 of the comparator circuit 31 via an electronic switch 55.
Connect with 6. The switching operation of the two switches 50 and 55 takes place via the OR circuit 43 and the final control element 45. Since the selected station program data storage circuit 34 is continuously timed by the clock pulse generator 40, each time it passes through the storage circuit 34, if the receiving station program data storage circuit 18
If the storage circuit 34 stores the same station program data in a readable storage line, an output signal will appear at the output 37 of the comparison circuit 31. When the electronic switches 50 and 55 are not switched, the readout control circuit 39 of the storage circuit can be freely used by other devices (not shown in detail) in the receiver.

FIG. 4 shows the record identification code 13 of the station transmitting the data record 57 and the station program data 14,
15, a station program data record (sentence) 57 is shown which also includes station program data 58 and 59 of other stations for identifying simulcast programs of other stations.
To evaluate such station program data records 57, a receiver as shown in FIG. 5 may be used as an embodiment of the present invention. Circuit elements common to the embodiments shown in FIGS. 1 and 3 are given the same reference numerals. Storage circuit 18' for receiving station program data
is the station identification code 14 and station program word 15 of each station
is the data output 2 of the storage circuit by the readout circuit 60.
9 is arranged to include readable storage rows supplied to the memory. In this embodiment, on the other hand, the tuning circuit 7 is a (transmitting) station data analog converter circuit 61 which includes, for example, a station identification word supplied to a data input 62 and a control input 6.
Based on the control pulse 64 supplied to Abst 3, the associated tuning voltage Abst
to occur. In this embodiment, the storage circuit 34 for storing selected station program data also includes an intermediate or buffer storage device 65 at its data output 33, which device 65 is controlled by the control output 33 and which is controlled by the data input 67 of the device. is the data output 3 of the memory circuit 34
Connect with 3. The data input 32 of the comparison circuit 31 is optionally input to the storage circuit 34 by the final electronic control element 68.
or to the data output 70 of the intermediate (buffer) storage 65.

When the receiving station program data is read into the storage circuit 18', the read control circuit 20' forms a read signal at its read output 53, which signal is activated by two electronic switches 55 which switch the read control circuit 39 of the storage circuit 34.
and 72 as the gate circuit 71 and the final control element 45
The final output 46 of the readout control circuit 39 for the storage circuit 34 is connected to the clock input T60 of the readout control circuit 60 acting on the storage circuit 18', and the readout clock output LT39 is connected to the comparator circuit 31 control input 36. Also, a reset signal 74 for the two readout control circuits 60 and 39 is generated under the action of a differentiating circuit 73 that differentiates the leading edge of the readout signal of the readout control circuit.
A clock pulse generator 40 times the read control circuit 39 of the storage circuit 34 and outputs a read clock output LT.
The control input 36 of the comparator circuit 31 is also timed via the switch 39 and the switch 72. First read control circuit 39
The signal generated at the final output 46 after one pass through the memory circuit 18 times the second read control circuit 60 of the storage circuit 18. If no signal occurs at the output 37 of the comparison circuit, the second readout control circuit 60 forms an output signal at its final output 80, which output signal resets the reset input RS20 of the readout control circuit 20' to its initial state. . However, when the comparator circuit 31 forms a comparison signal at its output 37, the leading edge of the output signal that immediately thereafter appears at the output of the pulse stretcher circuit 38 causes
Via the control circuit 66 , the data supplied to the data output 33 of the storage circuit 34 is stored in a buffer or intermediate storage 65 and in the differentiating circuit 75 .
A control pulse 64 is generated to generate a tuning voltage. The output signal of the pulse stretching circuit 38 is transferred to the data input 32 of the comparator circuit 31 via a final control element 68 and a switch 69 to a buffer (intermediate) storage device 6.
At the same time, the control signal to the final control element 45 of the electronic switches 55 and 72 is blocked via the gate circuit 71. This frees up the storage circuit 34 for loading selected station program data and leaves the associated readout control circuit available for other possible uses within the illustrated receiver. While the output signal of the pulse stretching circuit continues, the gate circuit 7
6 prevents the read control circuit 39 from being reset. Another gating circuit 77 connects the output of the clock pulse generator to the clock input T60 of the read control circuit 60 of the storage circuit 18', and a similarly controlled gating circuit 78 connects the output of the clock pulse generator to the read clock output of the second read control circuit 60. Control input 3 of comparison circuit 31 for LT60
Connect to 6. Under the action of an AND circuit 79 arranged in advance of the control input of a gate circuit 77, the second input of which is connected to the readout output 53 of the readout control circuit 20', the second readout control circuit 60 is connected to the output of the pulse stretching circuit. During the duration of the signal, the read control circuit 20'
is timed by the clock pulse generator 40 for the time that the read control circuit 20' is inactive, that is, the time that the read control circuit 20' is inactive. After passing through the second read control circuit 60, the second read control circuit 60 forms at its final output 80 a reset signal for resetting the read control circuit 20'.

While passing through the second read control circuit 60, the comparison circuit 31
forms an output signal during the transmission of program data in station program data record 57 stored in buffer storage 65 by a station to which tuning circuit 1 is tuned. The pulse width t38 of the pulse expanded by the pulse expansion circuit 38 is a multiple of the sum of the transit time of the read control circuit 20' and the transit time of the second read control circuit 60 in the illustrated embodiment. The trailing edge of the output signal of the pulse expansion circuit 38 is passed through the control circuit 66 to erase the station program data stored in the buffer storage device 65.

If, in another embodiment of the receiver according to the invention, the output of the storage circuit 34 is not provided with a buffer storage 65, then during the duration of the output signal of the pulse stretching circuit 38, each time the read control circuit 20' stops the reading operation. , a read control circuit, e.g. 39, is timed by a clock pulse generator 40, and a second read control circuit, e.g. 60, is timed by a termination signal generated upon completion of read of the first read control circuit. . Therefore, each memory row of one memory circuit is compared in comparison circuit 31 with each memory row of the other memory circuit.

[Brief explanation of drawings]

1 and 3 are block diagrams each schematically illustrating a receiver for evaluating receiving station program data sentences or records as schematically illustrated in FIG. 2; 4 is a block symbol that schematically represents a station program data sentence regarding broadcast programs of multiple stations, and FIG. 5 is a block symbol that schematically represents a receiving station program data sentence as shown in FIG. 4. 1 is a block diagram schematically illustrating a receiver for evaluating 1... Tuner tuning circuit, 2... Tuning input, 3
...Antenna input, 4...Intermediate frequency/demodulation circuit, 5...Signal pulse, 6...Regeneration circuit, 7...
Tuning circuit, tuner, 8... Tuning output, 9... Starting input, 10... Line, 11... Stop input, 12
...(Sending) Station program data record (sentence), 13...Sentence or record identification code, 14...(Sending) Station identification code, 15...
(Transmission) Station program word, 16...Data separation circuit,
17... Video text (teletext) decoder, 18... Memory circuit, 19... Gate circuit, 2
0...Reading control circuit, 21...Block circuit, 2
2... Control circuit, 23... Read output, 24... All selection call pulse, 25... Line, 26... Pulse delay circuit, 27... Bistable trigger (flip/
flop) circuit, 28... gate circuit, 29...
Data output, 30...Data input, 31...Comparison circuit, 32...Data input, 33...Data output, 34...Storage circuit, 35...Data input, 3
6...Data output, 37...Output, 38...Pulse expansion circuit, 39...Reading control circuit, 40...Clock (pulse) generator, 41...Gate circuit,
42...Logic circuit, 43...OR circuit, 44...
Electronic switch, 45...Electronic final control element, 46
... Final output, 47 ... Gate circuit, 48 ... Differential circuit, 49 ... Electronic switch, 51 ... Fixed station memory circuit, 52 ... Clock input (clock pulse input), 53 ... Read output, 54 ...Time switch, 55 ...Electronic switch, 57 ... (transmission) station program data record (sentence), 5
8...(transmission) station program data, 59...(transmission)
Station program data, 60...readout circuit, 61...transmission station data analog converter circuit, 62...
Data input, 63... Control input, 64... Pulse, 65... Buffer (intermediate) storage device, 66... Control circuit, 67... Data input, 68... Electronic final control element, 69... Electronic switch, 70...Data output, 71...Gate circuit, 72...Electronic switch, 73...Differentiating circuit, 74...Reset pulse, 75...Differentiating circuit, 76...Gate circuit,
77...Gate circuit, 78...Gate circuit, 79
...AND circuit, logical AND circuit, 80...final output.

Claims (1)

Claims: 1. An electronically tunable tuner circuit; an automatically adjustable tuner circuit having a start input for connecting to a tuning input of said tuner circuit and initiating a new tuning adjustment; an output of said tuner circuit; a transmitting station program data record connected to a signal path connecting to the side and comprising a transmitting station identification word and a transmitting station program word as a digital signal from a mixed signal present in said signal path, characterized by a record recognition word; a data separation circuit for separating data words contained in a data record at a data output and generating a call clock necessary for data output at a clock output; connect, store selected station data,
A receiver for a consumer electronic device comprising an arithmetic circuit for calculating data of a receiving station program data record based on the selected station program, the arithmetic circuit being connected to data output D of the data separation circuit 16.
A storage circuit for selected station program data comprising a storage circuit 18 for receiving station program data 14 and 15 connected to 16 and a corresponding reading control circuit 20, and a reading control circuit 39 controlled by a clock pulse generator 40. 34, and data outputs 29 and 33 of both memory circuits.
a comparison circuit 31 connected between the two, and a call clock output T of the data separation circuit;
16 is connected to the clock input T20 of the reading control circuit, and each time a pulse appears on the input side, it is transmitted at its output to the time interval between the start of two successive reading operations in the storage circuit for receiving station program data. A pulse stretching circuit 38 for stretching the pulse width to a width greater than 1 is connected to the output of the comparator circuit; the output of the pulse stretching circuit is connected to the start input 63 of the tuning circuit 61; and the read signal of the read control circuit. a logic circuit 42 which activates the comparator circuit when a signal appears at either output 23 and the output of the pulse stretching circuit;
A receiver for a consumer electronic device, characterized in that the receiver is connected to a consumer electronic device. 2 The output of the pulse stretching circuit 38 is transmitted to the tuning circuits 7 and 5.
1. The receiver according to claim 1, wherein the receiver is connected to a block input SP47 of a gate circuit 47 connected upstream of the activation inputs 9, 52 of the receiver. 3. A time delay that is released by the signal of the read control circuit and is equal to or longer than the reading time remaining in the receiving station program data storage circuit even after the release signal and the sum of the reading time of both storage circuits. A time switch 54 that generates an output signal after t26 is connected to the reading control circuit 20, and the output of the time switch is connected to the starting inputs 9, 52 of the tuning circuit 7 via a gate circuit 47. 2. The receiver according to any one of paragraphs 1 and 2. 4 The output of the time switch 54 connected to the reading control circuit 20 is the reset input RS of the reading control circuit.
3. A receiver according to claim 3, connected to 20. 5 The control circuit 20 reads the time switch 54
5. The receiver according to claim 3, wherein the receiver is connected to a read signal output 53 of the receiver. 6. connecting the output of said pulse stretching circuit to a starting input 63 of a tuning circuit 61 via a differentiating circuit 75 for differentiating the leading edge of the stretched pulse; and that tuning circuit 61 has a tuning data input 62; ,
The tuning circuit converts the tuning data input to its input into a tuning voltage when the signal 64 appears at the start input, and the tuning circuit is connected to the data output 33 of the storage circuit 34 for selected station program data. A receiver according to claim 1, characterized in that: 7. Another readout circuit 60 is also connected to the receiving station program data storage circuit 18, and the logic circuit 42
includes a switch 55 for connecting the clock input T60 of one read control circuit 60 to the end-of-operation signal output 46 of the other read control circuit 39 during the duration of the read control signal at the read signal output 53 of said read control circuit. A receiver according to any one of claims 1 to 6, characterized in that: 8 read control circuit 39 or read control circuit 39,
The serial circuit 60 also serves as the time switch 54, and the operation end signal output 46, 8 of the first read control circuit or the second read control circuit constituting the series circuit
8. The receiver according to claim 7, wherein 0 also serves as the output of the time switch. 9. A reset input which the readout control circuits 39, 60 connect to the readout output 53 of the readout control circuit 20 via a differentiation circuit 73 that differentiates the leading edge of the input signal.
Claim 1 characterized by including RS
8. The receiver according to any one of paragraphs 8 to 8. 10. A receiver according to any one of claims 1 to 9, characterized in that the comparator circuit (31) includes a clock input (36) connected to the output of the logic circuit (42). 11. The data output 33 of the storage circuit 34 for selected station program data is connected to the data output 32 of the comparison circuit 31 via a switch 50, and the output signal of the pulse expansion circuit 38 or the read control circuit 20 is 11. A receiver as claimed in any one of claims 1 to 10, characterized in that the switch is in a conducting closed state during the duration of the read signal. 12 The storage circuit 34 for selected station program data includes a buffer storage device 65 connected to the data output 33 of the storage circuit 34, and the data output 70 of the buffer storage device 65 is connected to the output signal of the pulse expansion circuit 38. during the duration, the control circuit 66 of the buffer is connectable to the data input 32 of the comparator circuit 31 and the control circuit 66 of the buffer is connected to the output of the comparator and the buffer is connected at the leading edge of the pulse stretcher circuit output signal. 11. Receiver according to claim 1, characterized in that it forms a storage signal at its trailing edge and a reset signal at its trailing edge.