JPH01317021A - Voltage comparison holding circuit - Google Patents

Abstract

PURPOSE:To reduce the current consumption and to make the operation stable by conducting alternately two MOS switches and two CMOS switches. CONSTITUTION:CMOS switches 17, 24 are used for two switches applying input control of a reference voltage Vref and an analog input voltage Vin and when an injection current is generated at P-channel MOS transistors(TRs) 3, 4, it is extracted via N-channel MOS TRs 5, 6 to prevent the current from flowing into inverter circuits 1, 2. In case of comparison of both voltages, two MOS switches 8, 10 are turned off, the impedance of the TRs in the CMOS inverter circuits 1, 2 is set in response to the quantity of both the voltages and a current from the power supply does not flow. Thus, the input level of the comparison voltage is lowered near the threshold value of the inverter circuits 1, 2. In case of holding the result of comparison, the two MOS switches 8, 10 are operated to hold the state based on the result of comparison. Thus, the circuit operation is made stable and the current consumption is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a voltage comparison and holding circuit used in an analog-to-digital conversion circuit.

(Prior Art) An analog-to-digital conversion circuit (hereinafter referred to as an AD conversion circuit) incorporates a voltage comparison and holding circuit that identifies a quantization boundary.

For example, FIG. 3 is a block diagram showing a parallel comparison type AD conversion circuit. This A-D conversion circuit consists of a reference voltage generation resistor 3 connected in series between reference power supplies VRT and VRB.
A number of comparison circuits 32 corresponding to the reference voltages obtained at each node of 1 are installed, and each comparison circuit 32 is configured to compare the analog signal voltage Vin with these reference voltages. The output of the comparator circuit 32 is input to the latch circuit 34 via the encoder 33, and a digital output Dout is obtained from the latch circuit 34. The performance of the A/D conversion circuit using this type of system is particularly dependent on the comparator circuit 32.

A conventional configuration of the comparator circuit 32 in FIG. 3 is shown in FIG. 4.

P-channel MO3) transistor 43 and N-channel MOS transistor 44, P-channel MO3) transistor 45 and N-channel MOS) whose respective gates and respective drains are commonly connected to each other and constitute CMOS inverter circuits 41 and 42. Among the transistors 46, the sources of the transistors 43 and 45 are connected to the power supply voltage VC.
The sources of the transistors 44 and 46 are connected to the ground voltage Vss through the source and drain of an N-channel MOS transistor 47. Also, CMo
The common gate of the 5-inverter circuit 41 is connected to the common drain of the CMOS inverter circuit 42 and one end of the P-channel MOS transistor 48, and the common gate of the CMOS inverter circuit 42 is connected to the common drain of the CMOS inverter circuit 41 and one end of the P-channel MOS transistor 48. 49, and the other ends of each of the transistors 48.49 are connected to an input terminal 50.51.

Gates of transistors 48 and 49 and transistor 47
The gates of the two are commonly connected and connected to the control terminal 52. Also, a connection node between the transistor 49 and the common drain of the CMOS inverter circuit 41 and the transistor 4
8 and the common drain of the CMOS inverter circuit 42 are connected to output terminals 53 and 54, respectively.

In the above circuit, the clock signal C supplied to the control terminal 52
When K switches from “H” to “L”, transistor 47
is off, and transistors 48 and 49 are on. As a result, the reference voltage Vref and analog input voltage V that are supplied to the input/output terminals 50 and 51, respectively.
in is input to the inverter circuits 41 and 42. next,
When the clock signal CK switches from the "L" level to the "H" level, the transistor 47 is turned on and the transistor 48 is turned on.
and 49 are turned off. Here, Vin>Vref
Then, in the CMOS inverter circuits 41 and 42, the gate-to-source voltage of the transistor 43 and the gate-to-source voltage of the transistor 46 are the same as the transistor 44.4.
5, the voltages between the gates and sources of both transistors 43 and 46 increase each other, and when the transistors 43 and 46 reach their threshold voltages, the transistor 43 is turned on in the inverter circuit 41, and the voltage in the inverter circuit 42 is turned on. Transistor 4B turns on.

As a result, the drain voltage of the transistor 43 rises to the power supply voltage VCC, and the drain voltage of the transistor 46 rises to the ground voltage vs.
5, the comparison result is obtained from the output terminals 53 and 54, and the result is held while the clock signal CK is at the 11 Hl'' level (holding mode).Then, the clock signal CK goes back to the “H” level. When the level changes from "L°" to "L°", the transistor 47 is turned off and the transistor 48 is turned off.
and 49 are turned on. As a result, the output terminal 53
．． 54 returns to each level of Vin and Vref again and enters the comparison mode.

However, in the above circuit, the clock signal CK is “L”.
” to “H” level and the transistor 48.4
9 turns off and enters the holding mode from the comparison mode, each inverter circuit 4
The injection current flows into the terminal 51.42, and the voltage at the output terminal 51.54 temporarily rises. As a result, if the voltages to be compared are close to each other, an erroneous comparison result may be obtained due to the presence of parasitic capacitance and parasitic resistance.

By the way, the analog input voltage Vin supplied to the input terminal 51 (or 50) needs to be set to a level as close to the VCC level as possible. For example, Vin is VCC
If the comparison reference voltage Vref is set at a level considerably lower than the current level, the comparison reference voltage Vref will naturally be set at a corresponding level. When the transistors 48 and 49 are turned on by the clock signal CK, current flows into the input terminals 50 and 51 from the power supply voltage VCC through the transistors 45.48 and 43.49. As a result, if the voltages to be compared are close, the transistors 43, 45, 4
Depending on the threshold value and size of 8.49, that is, variations in on-resistance, the voltage of the output terminal 53.54 in the comparison mode may be opposite to the magnitude relationship of Vin and Vref, and an incorrect comparison result may be obtained. . Furthermore, current is consumed during the comparison mode.

For this reason, when the level of the analog input voltage Vin is set near the power supply voltage VCC and the operation is performed, the voltage at the output terminals 53 and 54 becomes "Ho."

The problem is that when branching to "Lo", these two voltage levels temporarily try to be lowered to the level of the most sensitive circuit threshold of the inverter circuits 41 and 42, and then branch to "Ho" and "Lo". Due to this phenomenon, if the voltages to be compared are close to each other, there is a risk that the comparison results will be reversed depending on the variations in the transistors.To prevent this, increase the circuit threshold of the inverter circuits 41 and 42.
In other words, it is conceivable to increase the size of the transistors 43 and 45. However, in this method, an imbalance causes a time difference in operating speed between the rise and fall of the output signal, and current consumption also increases.

(Problems to be Solved by the Invention) As described above, in the conventional circuit configuration, there is a risk of malfunction due to the presence of parasitic resistance and parasitic capacitance due to the influence of the injection current. On the other hand, when the comparison voltage is set near the power supply voltage, the voltage at the terminal that outputs the comparison result is lowered to near the threshold of the inverter circuit and branches. Therefore, there is a risk of malfunction. On the other hand, if the size of the transistor is increased in order to raise the inverter circuit threshold value, a time difference occurs in the operating speed between the rise and fall of the output signal, leading to an increase in current consumption.

This invention was made in consideration of the above circumstances,
The purpose is to reduce current consumption and provide a stable voltage comparison and holding circuit.

[Structure of the Invention] (Means for Solving the Problems) A voltage comparison and holding circuit of the present invention includes two CMOS inverter circuits whose input and output terminals are cross-connected, and both of the above-mentioned CMs.
Two MOS switches connected between the OS inverter circuit and each of the power supply terminal and the ground terminal, and both of the above CMs.
Two CMOS switches connected between each input node of the OS inverter circuit and a node to which a reference voltage is supplied and a node to which an analog input voltage is supplied, the above two MOS switches, and the above two MOS switches. and means for alternately conducting the CMOS switches.

(Function) By using CMOS switches for the two switches that input and control the reference voltage and analog input voltage, when an injection current is generated on the P-channel MO3) transistor side, it is pulled out via the N-channel MOS transistor. This prevents it from flowing into the inverter circuit. When the two voltages are compared, the two MOS switches are off, the impedance of the transistor in the CMOS inverter circuit is only set according to the magnitude relationship between the two voltages, and no current flows from the power supply.

Therefore, the input level of the comparison voltage can be lowered to around the threshold of the inno(-) circuit.When holding the comparison result, two MOS switchboards are activated to maintain the state based on the comparison result. Then, the comparison results are taken out from the output node of each CMOS inverter circuit. In this way, it is possible to stabilize the circuit operation and reduce current consumption.

(Examples) Hereinafter, the present invention will be explained by examples with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the voltage comparison and holding circuit of the present invention. The CMOS inverter circuit 1.2 is constructed by connecting P-channel MOS transistors 3.4 and N-channel MO transistors 5.6 in series, and the gates and drains of transistors 3 and 5 are commonly connected. , transistor 4
The gates and drains of and 6 are connected in common.

The node 7 of the common source of both transistors 3.4 is P
Power supply voltage VCC via channel MOS transistor 8
A common source node 9 of both transistors 5 and 6 is connected to a terminal of ground voltage VSS via an N-channel MOS transistor IO.

An input node 11 of the CMOS inverter circuit 1 is connected to an output node 12 of the CMOS inverter circuit 2, and this output node 12 is provided with an output terminal 13. Between the output node 12 of this CMOS inverter circuit 2 and the input terminal 14 to which the reference voltage Vref is supplied, there is a P-channel MO3) transistor 15 and an N-channel MOS transistor 16 whose sources and drains are connected in parallel. A CMOS switch 17 is connected. Further, the input node 18 of the CMOS inverter circuit 2 is connected to the output node 19 of the CMOS inverter circuit 1, and the output node 19 is provided with an output terminal 20. Between the output node 19 of the CMOS inverter circuit 1 and the input terminal 21 to which the analog input voltage Vin is supplied, a P-channel MOS transistor 22 and an N
A CMOS switch 24 made up of a channel MOS transistor 23 is connected. And the above N channel M
OS) transistor 10 and both CMOS switches 17 above
．． Each P-channel MOS transistor 15 constituting 24
．． The clock signal CK supplied to the control terminal 25 is input to each gate of 22, and each N-channel MO3) transistor 1B, 23 which constitutes the P-channel MOS transistor 8 and both CMOS switches 17 and 24.
A clock signal CK supplied to the control terminal 26 is input to each gate.

In the voltage comparison and holding circuit, both the comparison mode and the holding mode are alternately operated depending on the levels of the clock signals CK and CK supplied to the control terminals 25 and 28.

FIG. 2 is a diagram showing voltage waveforms at each point in the circuit of the embodiment described above, and the operation of the circuit of the embodiment described above will be explained below using this waveform diagram.

When the clock signal CK is at "L" level and CK is at "H" level, the comparison mode is entered, and the CMOS switch 17.
24 is turned on, P channel MOS transistors 8 and N
Channel MOS transistor 10 is turned off. Note that in the holding mode before this comparison mode, the P channel MO
S transistor 8 and N channel MOS transistor I
By turning on O, node 7 goes to VCC level,
Nodes 9 are each set to the VSS level. In this comparison mode, the reference voltage Vref supplied to the input terminal 14.21 and the analog input voltage Vin are CM
It is taken into each input node 11.1B of OS inverter 1.2. Here, for example, it is assumed that there is a relationship of Vin>Vref. Then, on the P-channel MO3) transistor side of the CMOS inverter circuits 1 and 2, the voltage between the gate and source of transistor 3 becomes larger than the voltage between the gate and source of transistor 4, and the impedance between the drain and source of transistor 3 becomes higher than that of transistor 4. It is smaller than that of 4. Furthermore, on the transistor side (N-channel MOS), the voltage between the gate and source of the transistor 5 becomes larger than the voltage between the gate and source of the transistor 5, and the voltage between the gate and source of the transistor 6 increases.

The source-to-source impedance becomes smaller than that of transistor 5.

In this state, when the clock signal CK is inverted to "H" level and CK is inverted to "L" level, it enters the holding mode, and the CMOS
Switches 17 and 24 are turned off, and P channel MOS transistor 8 and N channel MOS transistor 10 are turned on. At this time, two CMOS inverter circuits 1 and 2
In the comparison mode ζ (by turning on the P-channel MOS transistor 3 which is in a low impedance state, the potential of the output node 19 rises.
S) By turning on Ranjistaro, output node 1
The potential of 2 drops. Furthermore, CMOS inverter circuit 1
, 2 to the input node 11.18 of
The potential of output node 12.19 is finally 'L' of VSS.
Level and V. It stabilizes at the 'H level of C, is held in that state, and is output from output terminals 13 and 20.

By the way, in the above embodiment circuit, when the reference voltage Vref and the analog input voltage Vin are taken into the input nodes 11.1g of the CMOS inverter circuits 1 and 2 in the comparison mode, they are controlled by the clock signals CK and CK of opposite phases, respectively. CMOS switches 17 and 24 made up of P-channel and N-channel MOS transistors are used. Therefore, the injection current due to the feed-through phenomenon that occurred in the conventional circuit is reduced by each CMO.
P channel and N channel MO of S switch 17.24
3) Cancelled by transistor. For this reason, CMO
The phenomenon in which the potential of each node of the S inverter 1.2 temporarily rises (as shown in the middle of FIG. 2) can be prevented, and erroneous comparison results will no longer be output as in the conventional case. Furthermore, in this comparison mode, transistor 8. The two CMOS inverter circuits 1.2 are connected to the power supply voltage V by IO. C and the ground voltage VSS, so even if the analog input voltage Vin and the reference voltage Vref are set considerably lower than the VCC level, no current will flow from the power supply voltage VCC as in the conventional case. Therefore, in this embodiment circuit, as shown by the solid line in FIG. 2, the analog input voltage Vin and the reference voltage Vref can be lowered to approximately the middle between VCC and vss, which are the circuit thresholds of the CMOS inverter circuits 1 and 2. As a result, the waveform abnormality (B in FIG. 2) where the voltage tends to suddenly drop to the threshold of the inverter circuit at the time of voltage comparison, which conventionally occurred due to the need to maintain the voltage close to the power supply voltage, is eliminated.

In this way, a more stable operating waveform than that of the conventional circuit can be obtained. The configuration of the circuit that performs the switch operation of the circuit of this invention can be modified in various ways, but the switch that inputs the comparison voltage must always have a CMOS configuration like 17.24 in this embodiment circuit. be.

[Effects of the Invention] As described above, according to the present invention, it is possible to reduce current consumption and provide a stable voltage comparison and holding circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a configuration according to an embodiment of the present invention;
FIG. 2 is an operating waveform diagram of the circuit shown in FIG. 1, FIG. 3 is a block diagram showing the configuration of an A/D conversion circuit, and FIG. 4 is a circuit diagram showing the configuration of a conventional voltage comparison and holding circuit. 1.2...CMOS inverter circuit, 3,4.8°1
5, 22...P channel MOS transistor, 5, 6
゜10, 16.23...N channel MO3) transistor, 7, 9. 11. 12. 18. 19...
Node, 13. 20...output terminal, 14.21...
・Input terminal, 17.24...CMOS switch, 25
．． 28...Control terminal. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Scope of Claims] Two CMOS inverter circuits whose input and output terminals are cross-connected; two MOS switches connected between both of the CMOS inverter circuits and a power supply terminal and a ground terminal, respectively; two CMOS switches connected between each input node of both CMOS inverter circuits and a node to which a reference voltage is supplied and a node to which an analog input voltage is supplied; CM of
1. A voltage comparison and holding circuit characterized by comprising means for alternately conducting conduction between an OS switch and an OS switch.