JPH01312649A - Cache purge circuit - Google Patents

Abstract

PURPOSE:To speed up purge by always outputting a miss hit in the middle of purge and permitting a CPU to make an access to a main memory with assuming a cache to be disable. CONSTITUTION:The purge of a cache memory is usually executed when power is supplied or when a task is switched. The former is executed when the power of a system is turned on and the latter is executed before the execution of the new task when the content of the main memory 11 is updated for switching the task under the environment of a multi task by DMA. When a purge signal P is inputted to the title circuit, a system comes the middle of purge while a flip flop FF1 outputs a disable signal DE, and the circuit always outputs the 'miss hit' M in the middle of purge. The access from the CPU12 is unconditionally performed to the main memory 11 with assuming cache to be disable. Thus, the purge action can be speeded up.

Description

[Detailed Description of the Invention] [Summary] Regarding a cache purge circuit that purges the contents of a cache memory, the purpose of this invention is to shorten the purge time with a relatively simple circuit configuration without using software. a cache purge circuit for purging, a tag RAM for storing addresses and valid/invalid bits;
a flip-flop circuit that outputs a disable signal until all areas of the tag RAM are cleared when receiving a purge signal; a counter that counts and amplifies the address of the tag RAM every clock during purge; a multiplexer that switches the address of the tag RAM from the CPU address to the output of the counter; a comparison circuit that compares the CPU address and the address output from the tag RAM; and a comparator circuit that receives the disable signal during purge. and a control circuit that sends a write signal to the tag RAM.

(Field of Industrial Application) The present invention relates to the configuration of a cache purge circuit that purges the contents of a cache memory for a CPU.

[Problems to be solved by conventional techniques and inventions] Conventionally,
Typical methods for purging the contents of the cache memory include a method in which the tag 5-RAM is cleared for all addresses using predetermined software, and a method in which a tag RAM with a clearing function is used.

The former is purged by software, for example, by writing "0" into the cache memory. In this case, there is a cost advantage because no hardware is required, but there are problems such as the software becoming complicated and the purging process taking a long time.

The latter has an address comparison circuit, a purge function, etc. This increases costs, and furthermore, these circuits cannot increase the speed of operation. Another problem is that the degree of integration is low, making it difficult to increase capacity.

An object of the present invention is to speed up the purge operation by using a relatively simple circuit configuration without using software.

[Means to solve the problem]

FIG. 1 is a diagram showing the basic configuration of the present invention. The present invention is a cache barge circuit that purges the contents of a cache memory, and includes a tag RAM (TAG) that stores addresses and valid/invalid bits, and an entire area of the tag RAM when a purge signal (P) is received. A flip-flop circuit that outputs a disable signal (DE) until the
FF), a counter (CNT) that counts up the address of the tag RAM every clock during purging;
A multiplexer (MPX) that switches the address of the tag RAM from the CPU address (CPU-ADD) to the output of the counter during purging, and a comparison circuit that compares the CPU address and the address output from the tag RAM. (CMP) and a write signal (W) to the tag RAM upon receiving the disable signal during purging.
E) and a control circuit (CTL) that sends out the signal.

[For production]

Cache memory purging is typically performed when power is turned on or when a task is switched. The former is performed when the system is powered on, and the latter is performed before executing a new task when the contents of the main memo ν are updated by DMA in order to switch tasks in a multitasking environment. When the purge signal P is input to this circuit, the purge is in progress while the flip-flop FF outputs the disable signal DE.
During this purge, this circuit always detects a “mishit” M.
is output, the cache is assumed to be disabled, and the CP
All accesses from U are made to main memory unconditionally.

〔Example〕

FIG. 2 is a configuration diagram of an embodiment of the present invention. In the figure, l is a flip-flop circuit, 2 is a counter, 3 is a multiplexer, 4 is a tag 5-RAM, 5 is a comparison circuit, and 6
1 is a tag control circuit, 7 is a multiplexer, 8 is a cache 5-RAM, 9 is a main memory control circuit, 10 is a transfer gate, 11 is a main memory (MS), and 12 is a processor (CPU). 1 to 7 are cash barge circuits of the present invention. 5-RAM4 for tag is address, valid/
An invalid bit is stored for each entry, and upon receiving the purge signal P, the flip-flop circuit 1 outputs a disable signal DE until the entire area of the 5-RAM 4 is cleared. When this signal DB is "1", the cache is in a disabled state. Counter 2 is 5-RAM during purge
4 address is counted and amplified for each block. Multiplexer 3 changes the address of 5-RAM4 to C during purge.
Switches from the PU address CPU-ADD to the output of the counter 2.The comparison circuit 5 compares the address of the CPU 12 and the address output from the 5-RAM 4.The tag control circuit 6 outputs the disable signal DE during purge. Sends the write signal WE to the receiving 5-RAM 4 and writes "0".The cache 5-RAM 8 is for storing data, and stores data for each entry.The MS control circuit 9 Connect the CPU 12 to the main memory 11.

The transfer game 1-10 controls the direction of data and address transfer using a control signal TR from the control circuit 9.

In this embodiment, the same single-function high-speed 5-RAM is used for tags and caches.

Further, 13 is a driver which is turned on when a "hit" signal H is received from the comparator circuit 5, and reads out data in the cache RAM 7 to the CPU 12.

In addition, ADD is an address line, DATA is a data line, and RAS
, CAS are strobe signals. The multiplexer 7 switches between the "O" output CPU address during purging and the disable signal DE. That is, the driver 14
“Purge” or “mishit” depending on the output of R gate 15
The disable signal DE and the control signal TR are input to the input of the OR gate 15, and the driver 14 is driven by the output thereof. Note that WD is write data and RD is read data.

FIG. 3 is a signal timing chart of the circuit of FIG. 2.

First, when the purge signal P is input to the flip-flop 1, the signal DE becomes "1" and this signal DE is input to the counter 2.
The counter 2 counts up the address of the 5-RAM 4 every clock CLK. During purging, a write signal WE is sent from the control circuit 6 to the 5-RAM 4, and a disable signal DE writes "0" in the contents of a register, etc. (not shown), and each entry is purged. During this time, the CPU address (CPU-ADD) accesses the main memory 11 via the control circuit 9, and
The data (MS-DATA) is transferred to the CPU 2 via the transfer game 10.

5-RAM4 for tag is not "hinted", so there is no signal during this time, and 5-RAM8 for cache is not accessed, so its data (CHE-DATA)
is not output either.

FIG. 4 is a diagram illustrating the execution of purge. When the cache and main memory MS are occupied by task 1, when switching to task 2, first update the MS to task 2 using O3 (operating system) DMA, and then switch the task. After that, purge task 1 in the cache. As a result, the cache is cleared and task 1 is moved to the external storage device.

〔Effect of the invention〕

As explained above, according to the present invention, a single-function high-speed 5
- It is possible to achieve high-speed purging with a relatively simple circuit configuration using -RAM, and it is also possible to reduce costs because it does not use 5-RAM with special functions, and it is also possible to increase capacity.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing the configuration of an embodiment of the present invention, FIG. 3 is a signal timing chart of the present invention, and FIG. 4 is a diagram explaining the execution of purge. (Explanation of symbols) 1: Flip-flop circuit, 2: Counter, 3.7: Multiplexer, 4: 5-RAM for tag, 5: Comparison circuit, 6: Control circuit for tag, 8: 5-RAM for cache. 9: MS control circuit, 10: Transfer gate, 11
: Main memory, 12: CPU. 13.14: Driver, 15: OR gate. A diagram explaining the principles of the present invention: groove formation, execution, and execution of the groove.

Claims (1)

[Claims] 1. A cache purge circuit that purges the contents of a cache memory, which includes a tag RAM (RAM) that stores addresses and valid/invalid bits.
TAG), a flip-flop circuit (FF) that outputs a disable signal (DE) when receiving the purge signal (P) until the entire area of the tag RAM is cleared, and a flip-flop circuit (FF) that outputs a disable signal (DE) until the entire area of the tag RAM is cleared; a counter (CNT) that counts up every clock; a multiplexer (MPX) that switches the address of the tag RAM from the CPU address (CPU・ADD) to the output of the counter during purge; a comparator circuit (CMP) that compares the addresses output from the tag RAM; and a comparator circuit (CMP) that compares the addresses output from the tag RAM;
A cache purge circuit comprising: a tag control circuit (CTL) that sends a write signal (WE) to an AM;