JPH0131251B2 - - Google Patents

Info

Publication number
JPH0131251B2
JPH0131251B2 JP54156674A JP15667479A JPH0131251B2 JP H0131251 B2 JPH0131251 B2 JP H0131251B2 JP 54156674 A JP54156674 A JP 54156674A JP 15667479 A JP15667479 A JP 15667479A JP H0131251 B2 JPH0131251 B2 JP H0131251B2
Authority
JP
Japan
Prior art keywords
electrode
switch
transparent
transparent dielectric
capacitance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54156674A
Other languages
Japanese (ja)
Other versions
JPS5679816A (en
Inventor
Toshihiko Yamamoto
Ryoichi Ochiai
Yoshio Nakano
Naofumi Nagai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP15667479A priority Critical patent/JPS5679816A/en
Publication of JPS5679816A publication Critical patent/JPS5679816A/en
Publication of JPH0131251B2 publication Critical patent/JPH0131251B2/ja
Granted legal-status Critical Current

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  • Switches That Are Operated By Magnetic Or Electric Fields (AREA)
  • Push-Button Switches (AREA)
  • Electronic Switches (AREA)
  • Position Input By Displaying (AREA)

Description

【発明の詳細な説明】 本発明は電気光学的表示装置(CRT、PDP及
びEL等)の表示パネルに載置して発光表示の情
報から所望事項を選択するための透明な静電容量
結合型マトリツクススイツチに関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention is a transparent capacitively coupled display device that is mounted on a display panel of an electro-optical display device (CRT, PDP, EL, etc.) and used to select a desired item from information displayed on a light-emitting display. Regarding matrix switches.

従来のこの種静電容量結合型マトリツクススイ
ツチ例えば透明スイツチ(単にスイツチと呼ぶ)
の構成並びに動作につき第1図の断面図により説
明する。
Conventional capacitively coupled matrix switches of this type, such as transparent switches (simply referred to as switches)
The structure and operation of the device will be explained with reference to the sectional view of FIG.

スイツチはガラスまたはプラスチツク等の透明
誘電体基板1の表裏両面に透明電極、例えば酸化
錫や酸化インジウムの蒸着薄膜を被着して静電容
量電極2並び3を形成し、これをスイツチ極とし
たものである。しかしてスイツチは表示装置のパ
ネル面上に載置させるかあるいはパネル前面に取
付けるかしてセツトすれば、パネル表示になる
数・文字等が透かして見られるよう構成される。
The switch is made by depositing transparent electrodes, such as vapor-deposited thin films of tin oxide or indium oxide, on both the front and back surfaces of a transparent dielectric substrate 1 made of glass or plastic, forming capacitance electrodes 2 and 3, which are used as switch poles. It is something. When the switch is placed on the panel surface of the display device or attached to the front surface of the panel, the switch is configured so that the numbers, characters, etc. displayed on the panel can be seen through it.

スイツチ極2の上方には透明な誘電体保護層
4,他方の極3の下側には同様の透明な絶縁保護
層5が付加してある。
A transparent dielectric protection layer 4 is provided above the switch pole 2, and a similar transparent insulating protection layer 5 is provided below the other pole 3.

かかる構成のスイツチをマトリツクス状に配置
したマトリツクススイツチは表示パネル6上に載
置され、表示パネル面の多数の表示項目中の所望
事項に対応するスイツチを指圧操作すればスイツ
チ極間の容量がその間変化することによつて検知
され表示項目を選択することができる。
A matrix switch in which switches with such a configuration are arranged in a matrix is placed on the display panel 6, and by operating the switch corresponding to a desired item among the many display items on the display panel surface with finger pressure, the capacitance between the switch poles can be increased. Changes during this time can be detected and display items can be selected.

しかしてかかる従来構成の静電容量変化形スイ
ツチではその電極2と3がスイツチ軸7上に重複
して形成されているためスイツチ操作に伴う信号
入力源側(電極2側)と信号検知回路側(電極3
側)との結合容量変化が少なく、その結果スイツ
チ性能指数としての伝達遮断比(スイツチONの
ときとスイツチOFFのときとの出力比)が小さ
く、しかも表示パネル面からの雑音を遮断出来ず
機能面からの改良が必要とされていた。
However, in such a conventional capacitance variable switch, the electrodes 2 and 3 are formed overlappingly on the switch shaft 7, so that when the switch is operated, the signal input source side (electrode 2 side) and the signal detection circuit side (Electrode 3
As a result, the transfer cut-off ratio (output ratio when the switch is ON and when the switch is OFF) as a switch performance index is small, and the noise from the display panel surface cannot be blocked. Improvements were needed from the front.

本発明の目的は前記問題点を除去することであ
り、スイツチ性能指数の高い以下のスイツチ構成
を提供することにある。
An object of the present invention is to eliminate the above-mentioned problems, and to provide the following switch configuration with a high switch performance index.

かかる本発明による静電容量結合型マトリツク
ススイツチの特徴とする所は透明誘電体基板の一
方の全面には接地接続される共通電極としての第
1電極を有し、該基板の他面側にはX、Yのマト
リツクス交点に対応するスイツチ位置にY列方向
に回路パターンで結合された第3電極が、又第3
電極に対し、更に他の透明誘電体基板を介してマ
トリツクススイツチ位置にX方向に回路パターン
で結合された第2電極が夫々配置され、第2電極
と第3電極とは重複しないように位置がずらさ
れ、対となつてスイツチを構成し、第2電極上に
は更に透明誘電体保護層が設けられ、各電極は透
明電極よりなり、しかも誘電体保護層上で第2電
極と第3電極とが重複しないスイツチ位置を指で
押下した時に第2電極と第3電極間に大なる静電
容量が形成されるように、又第1電極と第2電
極、第1電極と第3電極も静電容量電極を構成す
る如く第1電極、第2電極、第3電極が配置され
ている点にある。
The capacitively coupled matrix switch according to the present invention is characterized by having a first electrode as a common electrode connected to ground on one entire surface of the transparent dielectric substrate, and a first electrode as a common electrode connected to the ground on the other surface of the substrate. A third electrode is connected in a circuit pattern in the Y column direction to the switch position corresponding to the intersection of the X and Y matrices.
Second electrodes are connected to the electrodes in a circuit pattern in the X direction at the matrix switch position through another transparent dielectric substrate, and the second electrodes and the third electrodes are located so as not to overlap. A transparent dielectric protective layer is further provided on the second electrode, and each electrode is made of a transparent electrode. In order to create a large capacitance between the second electrode and the third electrode when the switch position where the electrodes do not overlap with each other is pressed down with a finger, Also, the first electrode, the second electrode, and the third electrode are arranged so as to constitute a capacitance electrode.

以下第2図〜第4図の本発明のスイツチの実施
例にもとづき説明する。尚第5図は本スイツチの
電気等価回路である。
Embodiments of the switch of the present invention shown in FIGS. 2 to 4 will be explained below. FIG. 5 shows the electrical equivalent circuit of this switch.

第2図の実施例において、イはスイツチ上面図
又ロはイのA−A′断面図である。
In the embodiment shown in FIG. 2, A is a top view of the switch, and B is a sectional view taken along line A-A' of A.

ロ図においてガラス等透明誘電体基板1の表裏
両面に酸化インジウム(In2O3)等を蒸着生成し
た透明第2電極2並びに透明第3電極3が示され
る。しかし透明電極2と3とはスイツチの押圧位
置である図示スイツチ軸7に対し互いに偏位しか
つ電極面が重複しない位置、例えば電極2の側が
左であれば電極3の側は右に偏する関係位置とな
る様な静電容量電極をなす電極パターンの形とな
つている。電極パターンはイ図に示される。
In the figure, a transparent second electrode 2 and a transparent third electrode 3 are shown, which are formed by vapor-depositing indium oxide (In 2 O 3 ) or the like on both the front and back surfaces of a transparent dielectric substrate 1 such as glass. However, the transparent electrodes 2 and 3 are offset from each other with respect to the switch axis 7 shown in the figure, which is the switch pressing position, and the electrode surfaces do not overlap, for example, if electrode 2 is on the left, electrode 3 is on the right. It is in the form of an electrode pattern that forms a capacitance electrode at a related position. The electrode pattern is shown in Figure A.

又透明誘電体基板1の下部の透明誘電体基板5
の下面にIn2O3等を前記同様の方法で地気接続さ
れる透明第1電極8が全面に設けられており、前
記第2電極2と第3電極3との対電極となつてい
る。
Also, a transparent dielectric substrate 5 below the transparent dielectric substrate 1
A transparent first electrode 8 to which In 2 O 3 or the like is connected to the earth in the same manner as described above is provided on the lower surface of the electrode, and serves as a counter electrode for the second electrode 2 and the third electrode 3. .

本静電容量結合型マトリツクススイツチは、前
記手段で製作した透明誘電体基板1並びに透明誘
電体基板5とを図示の如く積層して構成したもの
である。ただしスイツチ表面にはポリエステル等
からなる透明な誘電体絶縁層4が付加され、スイ
ツチ押圧表面を形成すると共に電極2の外部から
の機械的擦傷保護の機能を有している。
This capacitive coupling type matrix switch is constructed by laminating the transparent dielectric substrate 1 and the transparent dielectric substrate 5 manufactured by the above method as shown in the figure. However, a transparent dielectric insulating layer 4 made of polyester or the like is added to the switch surface, which forms a switch pressing surface and also has the function of protecting the electrode 2 from external mechanical scratches.

第3図は本発明の他の実施例を示す。 FIG. 3 shows another embodiment of the invention.

即ち、第3図の静電容量結合型マトリツクスス
イツチでは透明第2電極2は透明誘電体絶縁層
1′の下面に、又透明第3電極3は透明誘電体基
板1″の下面に夫々蒸着形成されており、更に透
明第1電極8が下面に設けられた透明誘電体基板
5と図の如く積層接着されている。
That is, in the capacitively coupled matrix switch shown in FIG. 3, the transparent second electrode 2 is deposited on the lower surface of the transparent dielectric insulating layer 1', and the transparent third electrode 3 is deposited on the lower surface of the transparent dielectric substrate 1''. Further, a transparent first electrode 8 is laminated and bonded to a transparent dielectric substrate 5 provided on the lower surface as shown in the figure.

第3図の構成によれば第2電極2が下面に蒸着
されている透明誘電体絶縁層1′の上面がスイツ
チ押圧表面を形成し、かつ機械的擦傷保護層を構
成する。
According to the arrangement of FIG. 3, the upper surface of the transparent dielectric insulation layer 1', on which the second electrode 2 is deposited, forms the switch pressing surface and constitutes a mechanical scratch protection layer.

第4図は更に他の実施例を示し、ここでは透明
な第2電極2と透明な第3電極との重複しない関
係配置の他の例である。イ図はスイツチ上面図、
又ロはイ図のA−A′の断面図である。
FIG. 4 shows yet another embodiment, in which the transparent second electrode 2 and the transparent third electrode are arranged in a non-overlapping relationship. Figure A is a top view of the switch.
B is a sectional view taken along line A-A' in FIG.

透明第2電極は透明誘電体基板1の表面に櫛歯
上パターンに形成され、他方透明第3電極3は透
明誘電体基板1の裏面側に形成されるが、これら
電極2と3の形状はイ図から明らかな様に互いに
偏位して対向する面積部分がない様な配置となつ
ている。
The transparent second electrode is formed in a comb-like pattern on the surface of the transparent dielectric substrate 1, and the transparent third electrode 3 is formed on the back side of the transparent dielectric substrate 1, but the shapes of these electrodes 2 and 3 are as follows. As is clear from Figure A, the arrangement is such that there are no opposing areas that are offset from each other.

透明第1電極8を下面に設けた透明誘電体基板
5と透明誘電体基板1との積層構造は第2図と同
じである。
The laminated structure of the transparent dielectric substrate 5 and the transparent dielectric substrate 1 having the transparent first electrode 8 provided on the lower surface is the same as that shown in FIG. 2.

尚、図中9は第2電極と第3電極の回路パター
ンが基板1を介して交叉する個所である。
Note that 9 in the figure is a location where the circuit patterns of the second and third electrodes intersect via the substrate 1.

前記第2〜第4図の本発明スイツチの電気的機
能につき第5図の等価回路で説明する。図中の番
号2,3および8は前記の電極に該当する。
The electrical functions of the switches of the present invention shown in FIGS. 2 to 4 will be explained using the equivalent circuit shown in FIG. Numbers 2, 3 and 8 in the figure correspond to the aforementioned electrodes.

本スイツチは表示パネル面から入来する雑音を
遮断する接地13導体面を兼ねる透明第1電極8
と対向して異なる距離D3並びにD2(D3は透明誘電
体基板5の厚さ、D2は透明誘電体基板5と透明
誘電体基板1の厚さに該当する。第2図参照)に
透明第3電極3並びに透明第2電極2が設けら
れ、第1電極と第2電極、第1電極と第3電極間
は静電容量を形成し、一方第2電極と第3電極間
の静電容量(図示10)は微小である。
This switch has a ground 13 that blocks noise coming from the display panel surface; a transparent first electrode 8 that also serves as a conductor surface;
and different distances D 3 and D 2 (D 3 corresponds to the thickness of the transparent dielectric substrate 5, and D 2 corresponds to the thickness of the transparent dielectric substrate 5 and the transparent dielectric substrate 1. See FIG. 2) A transparent third electrode 3 and a transparent second electrode 2 are provided, and a capacitance is formed between the first electrode and the second electrode, and between the first electrode and the third electrode, while a capacitance is formed between the second electrode and the third electrode. The capacitance (10 shown in the figure) is minute.

他方、本スイツチを駆動する高周波信号源11
は第1電極8と第2電極2間に接続され、スイツ
チ動作を検知する検知回路12は第1電極8と第
3電極3間に接続されている。しかして第2図〜
第4図に示すスイツチ操作の指が接触すれば、二
つの静電容量間の図示結合容量10が発生する。
これに伴ない高周波信号源11はスイツチされ右
方の検知回路12に大きい信号出力が伝達される
ことになる。かくして指圧の有無で出力のレベル
変化が顕著なスイツチ機能がえられる。
On the other hand, the high frequency signal source 11 that drives this switch
is connected between the first electrode 8 and the second electrode 2, and a detection circuit 12 for detecting a switch operation is connected between the first electrode 8 and the third electrode 3. However, Figure 2~
When a finger touches the switch shown in FIG. 4, an illustrated coupling capacitance 10 between two capacitances is generated.
Along with this, the high frequency signal source 11 is switched and a large signal output is transmitted to the right detection circuit 12. In this way, a switch function is provided in which the output level changes significantly depending on the presence or absence of acupressure.

第6図はスイツチ性能比較グラフであり本スイ
ツチAと従来スイツチBとの伝達・遮断比、
(ON/OFF比)で見たスイツチ性能の比較をし
たものである。
Figure 6 is a switch performance comparison graph, showing the transmission/cutoff ratio between this switch A and the conventional switch B.
This is a comparison of switch performance in terms of (ON/OFF ratio).

図から本スイツチは格段に優れた性能であるこ
とは明らかである。この理由は前記の如く透明第
1電極8(接地13の導電層)上に互いに偏在配
置されかつ重複のない電極積層構造の採用によ
り、遮断(OFF時)のさいの相互間結合静電容
量が小とされているからである。
It is clear from the figure that this switch has significantly superior performance. The reason for this is that, as mentioned above, by adopting a laminated structure of electrodes that are unevenly distributed and do not overlap each other on the transparent first electrode 8 (conductive layer of the ground 13), the mutual coupling capacitance during cutoff (when OFF) is reduced. This is because it is considered small.

即ち本発明によれば第1電極8は全面に被着さ
れ、地気接続されるので表示パネル面からの雑音
信号を遮断することが出来るばかりでなく第2、
第3電極は重複しないように互いに位置がずらさ
れ、しかもスイツチ位置を指で押圧した場合には
第2電極と第3電極間の静電容量は大となるよう
に配置されているので上述の如く大きな検知信号
が得られ、スイツチ表面は誘電体絶縁層となつて
いるので、機械的擦傷にも十分耐えることが出
来、指による押圧の場合にも高周波信号に直接触
れることはなく、又各電極と基板等も総て透明材
料より構成されるので表示パネル面に載置して
も、表示パネルの表示を見て、その必要個所に対
応するスイツチ位置を押下することが容易とな
る。
That is, according to the present invention, since the first electrode 8 is coated on the entire surface and connected to the ground, it is possible not only to block noise signals from the display panel surface, but also to block the second electrode 8.
The positions of the third electrodes are shifted from each other so that they do not overlap, and the positions are arranged so that when the switch position is pressed with a finger, the capacitance between the second and third electrodes becomes large. As the switch surface is made of a dielectric insulating layer, it can withstand mechanical scratches, and even when pressed with a finger, it does not come into direct contact with the high-frequency signal, and each Since the electrodes, substrate, etc. are all made of transparent materials, even when placed on the surface of the display panel, it is easy to see the display on the display panel and press the switch position corresponding to the required location.

前記本発明のスイツチを電気光学的表示装置の
パネル面に縦横に格子配列した静電容量結合型マ
トリツクススイツチの全体図を第7図と第8図に
掲げる。図例は共に縦・横夫々3列に配した状態
である。第7図は第2図の電極形状のパターン
を、又第8図は第4図の電極形状パターンを使用
したマトリツクススイツチであり、イ図は斜視
図、イ図はスイツチ単体部の上面図である。
FIGS. 7 and 8 show general views of a capacitively coupled matrix switch in which the switches of the present invention are arrayed in a grid array on the panel surface of an electro-optical display device. In the illustrated example, the devices are arranged in three rows each vertically and horizontally. Fig. 7 shows a matrix switch using the electrode shape pattern shown in Fig. 2, and Fig. 8 shows a matrix switch using the electrode shape pattern shown in Fig. 4. Fig. A is a perspective view, and Fig. A is a top view of the switch unit. It is.

該マトリツクススイツチの底面は透明第1電極
8が全面に蒸着生成され地気接続される。又透明
第2電極2はX列(横列)接続のための回路パタ
ーン14と連結接続される。他方透明第3電極3
はY列(縦列)接続のための回路パターン15
(点線で示す回路)と連結接続される。
A transparent first electrode 8 is deposited on the entire bottom surface of the matrix switch and connected to earth. Further, the transparent second electrode 2 is connected to a circuit pattern 14 for connecting X rows (horizontal rows). The other transparent third electrode 3
is circuit pattern 15 for Y column (vertical) connection
(circuit shown by dotted line).

しかしながらX列とY列各回路パターンの交叉
個所では、スイツチON、OFF動作の結合静電容
量変化を小とするような静電容量が生ずるのを避
けるためロ図の上面図にある回路パターン交叉部
9において、切欠き16を設けて対向面積を小と
し回路パターン間の静電容量(通称の漂遊容量)
を小としている。
However, at the intersections of the circuit patterns in the X and Y columns, in order to avoid the generation of capacitance that would reduce the change in coupling capacitance during switch ON and OFF operations, the circuit pattern intersections shown in the top view of Figure B are used. In section 9, a notch 16 is provided to reduce the opposing area and reduce the capacitance (commonly known as stray capacitance) between the circuit patterns.
is considered small.

尚X列接続の回路パターン14、Y列接続の回
路パターン15は、前記透明第2電極並びに透明
第3電極3の蒸着時に同時に形成することが可能
である。
Note that the circuit pattern 14 connected in the X column and the circuit pattern 15 connected in the Y column can be formed at the same time when the transparent second electrode and the transparent third electrode 3 are deposited.

かかる配列になるマトリツクススイツチは面内
の何れかのスイツチが指圧されると回路パターン
15の側に接続されるスイツチ検知回路(第5図
の12)における図示されていないゲート回路及
びエンコーダ回路により指圧のスイツチが検知さ
れることとなる。
The matrix switches in such an arrangement are operated by a gate circuit and an encoder circuit (not shown) in a switch detection circuit (12 in FIG. 5) which is connected to the circuit pattern 15 side when any switch in the plane is finger pressed. The shiatsu switch will be detected.

以下本発明の静電容量結合型マトリツクススイ
ツチはスイツチ伝達遮断比が高いこと、これに関
連する信号検知回路が簡易となること、表示パネ
ル面よりの雑音信号が遮断されること、指の押圧
位置が直接電極面ではなく誘電体表面であり高周
波信号に直接触れることなく、耐機械的擦傷性も
大となること等からスイツチの信頼性も向上す
る。かかる点から本スイツチは広汎な応用が期待
され、その工業的効果大なるものがある。
The capacitive coupling type matrix switch of the present invention has the following features: a high switch transmission cutoff ratio, a simple signal detection circuit related to this, a noise signal from the display panel surface being blocked, and a finger press. The reliability of the switch is also improved because it is located on the dielectric surface rather than directly on the electrode surface, so it does not come into direct contact with high-frequency signals, and has greater mechanical scratch resistance. From this point of view, this switch is expected to have a wide range of applications, and its industrial effects will be significant.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のスイツチ構成を示す断面図、第
2図〜第4図は本発明のスイツチ構成実施例を示
す上面図並びに断面図、第5図は第2〜第4図ス
イツチの等価回路図、第6図はスイツチ性能比較
グラフ及び第7図と第8図は本発明による静電容
量結合型マトリツクススイツチの全体図としての
実施例の斜視図である。 図中、1,1″,5は透明誘電体基板、1′,4
は透明誘電体保護層、2は透明第2電極、3は透
明第3電極、7はスイツチ軸、8は透明第1電
極、9は回路パターン交叉部、10は結合静電容
量、14はX列接続の回路パターン、15はY列
接続の回路パターン、16は切欠きを夫々示す。
FIG. 1 is a sectional view showing a conventional switch configuration, FIGS. 2 to 4 are top views and sectional views showing embodiments of the switch configuration of the present invention, and FIG. 5 is an equivalent circuit of the switch shown in FIGS. 2 to 4. 6 is a switch performance comparison graph, and FIGS. 7 and 8 are perspective views of an embodiment as an overall view of the capacitive coupling type matrix switch according to the present invention. In the figure, 1, 1'', 5 are transparent dielectric substrates, 1', 4
is a transparent dielectric protective layer, 2 is a transparent second electrode, 3 is a transparent third electrode, 7 is a switch axis, 8 is a transparent first electrode, 9 is a circuit pattern intersection, 10 is a coupling capacitance, and 14 is X Reference numeral 15 indicates a circuit pattern of column connection, 15 indicates a circuit pattern of Y column connection, and 16 indicates a notch.

Claims (1)

【特許請求の範囲】[Claims] 1 透明誘電体基板の一方の全面には接地接続さ
れる共通電極としての第1電極を有し、該基板の
他面側にはX、Yのマトリツクス交点に対応する
スイツチ位置にY列方向に回路パターンで結合さ
れた第3電極が、又第3電極に対し、更に他の透
明誘電体基板を介してマトリツクススイツチ位置
にX方向に回路パターンで結合された第2電極が
夫々配置され、第2電極と第3電極とは重複しな
いように位置がずらされ、対となつてスイツチを
構成し、第2電極上には更に透明誘電体保護層が
設けられ、各電極は透明電極よりなり、しかも誘
電体保護層上で第2電極と第3電極とが重複しな
いスイツチ位置を指で押下した時に第2電極と第
3電極間に大なる静電容量が形成されるように、
又第1電極と第2電極、第1電極と第3電極も静
電容量電極を構成する如く第1電極、第2電極、
第3電極は配置されてなることを特徴とする静電
容量結合型マトリツクススイツチ。
1. A first electrode as a common electrode connected to ground is provided on one entire surface of the transparent dielectric substrate, and switches are provided on the other surface of the substrate in the Y column direction at switch positions corresponding to the intersections of the X and Y matrices. a third electrode coupled with a circuit pattern; and a second electrode coupled with a circuit pattern in the X direction at the matrix switch position via another transparent dielectric substrate, and a second electrode coupled with the circuit pattern in the X direction, respectively; The second electrode and the third electrode are shifted in position so as not to overlap, and form a switch as a pair, and a transparent dielectric protective layer is further provided on the second electrode, and each electrode is made of a transparent electrode. Moreover, when a switch position on the dielectric protective layer where the second electrode and the third electrode do not overlap is pressed down with a finger, a large capacitance is formed between the second electrode and the third electrode.
In addition, the first electrode and the second electrode, and the first electrode and the third electrode also constitute a capacitance electrode.
A capacitive coupling type matrix switch characterized in that a third electrode is arranged.
JP15667479A 1979-12-03 1979-12-03 Transparent switch Granted JPS5679816A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15667479A JPS5679816A (en) 1979-12-03 1979-12-03 Transparent switch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15667479A JPS5679816A (en) 1979-12-03 1979-12-03 Transparent switch

Publications (2)

Publication Number Publication Date
JPS5679816A JPS5679816A (en) 1981-06-30
JPH0131251B2 true JPH0131251B2 (en) 1989-06-23

Family

ID=15632825

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15667479A Granted JPS5679816A (en) 1979-12-03 1979-12-03 Transparent switch

Country Status (1)

Country Link
JP (1) JPS5679816A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101190276B1 (en) * 2009-10-28 2012-10-12 주식회사 애트랩 Input device and touch position detecting method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52151063A (en) * 1976-06-11 1977-12-15 Seiko Instr & Electronics Ltd Touch switch for electronic wristwatches
JPS53129874A (en) * 1977-04-19 1978-11-13 Matsushita Electric Ind Co Ltd Touch switch
JPS54116677A (en) * 1978-03-02 1979-09-11 Yamatake Honeywell Co Ltd Touch board
JPS54160136A (en) * 1978-06-09 1979-12-18 Panafacom Ltd Touch keyboard

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52151063A (en) * 1976-06-11 1977-12-15 Seiko Instr & Electronics Ltd Touch switch for electronic wristwatches
JPS53129874A (en) * 1977-04-19 1978-11-13 Matsushita Electric Ind Co Ltd Touch switch
JPS54116677A (en) * 1978-03-02 1979-09-11 Yamatake Honeywell Co Ltd Touch board
JPS54160136A (en) * 1978-06-09 1979-12-18 Panafacom Ltd Touch keyboard

Also Published As

Publication number Publication date
JPS5679816A (en) 1981-06-30

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