JPH01311321A - Adder - Google Patents

Abstract

PURPOSE:To remove delay in the propagation time of a signal even when an adder is formed as an LSI by constituting the adder of addition blocks of 1st to n-th digits (n>=2) each of which consists of m (m>=2) bits, and only when carry propagation outputs are generated from carry forecasting circuits of respective digits and carries to the forecasting circuits exist, correcting an addition value. CONSTITUTION:The adder is divided into plural addition blocks 1-4 consisting of 2 bytes in each digit, bit 63 (B48-63) out of bit 48 in data A is added to bit 63 (B48-63) out of bit 48 in data B by the least significant digit adder and the added result is outputted as D48-63. At that time, a carry-out signal C52 is outputted from bit 52 to the 2nd stage block 2 and the block 2 inputs A48-51, B48-51 and C52 in addition to A32-47 and B32-47 and outputs the added result D52-47 and carry C36 from bit 36. Similarly, blocks 3, 4 output respective added results and carries D20, D0-15.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the configuration of an adder that adds binary data.

[Conventional technology]

Conventionally, in order to add binary data at high speed, a carry prediction (Look Ahead Carry) has been used.
The method (hereinafter abbreviated as LAC) was used.

The principle of the carry prediction method will be explained below.

The carry-in manpower C in the addition of the first digit is the (i-th
-1) Carry G1-1 when adding data input to the digit and carry propagation state (carry prediction/dirt: the result of addition of data input to the (i-1)th digit is all “l”) It is generated as follows from the state) Pi-1 and the carry-in input C1-1 to the (i-1)th digit.

C1=Gt1+Pl-1°C,.

That is, the carry-in human power C to the first digit is when there is a carry generated by addition of data input to the (i-1)th lower digit.

Or, there is a carry-in human power C1-1 in the (i-1)th digit, and the added value of the data input to the (i-1)th digit is all "1", and the carry-in C, -□ becomes the This is when propagating (f-1) digits.

The LAC method uses this principle to perform multi-digit addition at high speed, and an example is shown in Figure 3.

Figure 3 shows a 4-digit adder for data A and H.

31, 32, 33, and 34 are adder circuits corresponding to each digit, and each data Ai is input to each digit.

B, (i=1.2.s, 4) has a carry output G and a carry propagation output P.

At this time, the carry C2 from the least significant digit to the second digit is:

C2=01° The carry-in human power C3 to the third digit is.

C3=G2+P2・C2 =G2+G,・P2゜ The carry-in human power C4 to the fourth digit is.

C4=G3+P3・C3=G3+G2・P3+G1・P2・P3 And the carryout C3ut of the one adder is.

35.36.37゜3
8, a 4-digit adder can be realized.

[Problem to be solved by the invention]

Adder like above iJ? Socage (or LSI)
When implementing, if all the circuits are to be implemented in one package (or LSI), the longer the adder is for long data, the worse the pin/gate ratio (the lower the number of pins compared to the number of darts). (Mostly) Nosecage (or LSI).

To solve this problem, as shown in Figure 3.

It is possible to implement slices for each digit.

In this case, the carry from the lower digit needs to be input to the upper digit via the LAC circuit, so the register 39f holding the adder output and another tJ? When mounted on a package (or LSI), regarding the above carry signal, f
The problem with this signal crossing twice between two cages (or LSIs) is that the propagation time (delay time) of this signal is delayed compared to other signals even if the LAC method is adopted.

[Means to solve the problem]

The adder according to the present invention includes an addition block of 1st to nth (n≧2) digits in which m (m≧2) bits are one digit,
The first digit addition block among the (n-1) addition blocks excluding the first digit addition block is the upper J pip of the (i-1)th digit addition input) (1≦J≦m ) is input to predict the carry to the first digit, and the (i-th
1) means for correcting the addition result of the first digit depending on the presence or absence of a carry to the J-th bit from the higher order digit;

〔Example〕

Two embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 and FIG. 2 are diagrams showing two embodiments of the present invention.

In this embodiment, 2 bytes are converted into 1 digit, that is, m=
16, 4 digits and 8 bytes, ie.

Consider configuring an adder with n=4. Also.

Consider the case where J=4.

Here, it is assumed that a 1-digit 2-byte addition block is implemented as one circuit block in one package (or LSI). 1.2 and 3°4 in Figure 1 are respectively,
This is the addition block.

As shown in Fig. 1, addition block 1 is an addition circuit for the least significant digit, and is from bit 48 to bit 63 of data A (
A4B-63) and bit 48 of data B) 6
3 (B48., ) is added and the addition result is D4B.
Output as -65.

At this time, carry-out signal C5□ from bit 52
is output to addition block 2 of the second digit.

Also, the second digit addition block 2 is l A32-47 and B
In addition to 52-47, A48-51, B48-51 and the above C52 are input, and the second digit addition result D52
-47 and carry C36 from Binot 36 are output.

Similarly, the third digit addition block 3 is j A16-51
and B16-31 plus l A32-551 B52-
55 and the above-mentioned C36 as inputs, and outputs the addition result D+6-51 of the third digit and the carry C2o from bit 20.

Furthermore, the fourth digit addition block 4 has +Ao-15 and Bo
In addition to -15, l A16-19 # B16-19 and the above C2° are input, and the result is the addition of the fourth digit.

-15 is output.

FIG. 2 is a diagram showing details of each of the addition blocks.
is a 2-byte adder circuit corresponding to each digit.

6 is a carry prediction circuit for the adder circuit 5, which calculates the upper 4 bits a4/Al- of the lower digit input data.
1 (each” l A16-191 As2-551 A4
8-51) and H (14/B, -, (each "l B16
-191 B52-55 'B4B-51> Outputs carry and carry propagation when added as all inputs.

Now, what is the carry to the first digit in the two-adder?

The upper 4 bits α'/A of the (i-1)th digit input data,
, , α'/s, -1 is predicted to be present when there is a carry when added as input.

The signals on signal line 100 in FIG. 2 implement this logic.

At this time, this prediction is performed by the carry prediction circuit.
-Ci (C20 or C36 or C
52) is correct except when it exists.

Therefore, in this case, the correct output from the adder circuit 5 is obtained as the addition result of the first digit.

If the prediction is correct for each digit, a correct result will be obtained from the output of the adder circuit for each digit, and an 8-byte addition result will be obtained.

On the other hand, the prediction is incorrect because the carry prediction circuit is in the carry propagation state and the 4th bit from the uppermost bit of the (1-1)th digit is a carry! This is the case when J Ci exists.

The signal line 101 in FIG. 2 is for sending the carry signal C1 to the 4th bit from the higher order of the lower digits. The condition is detected, the invalidity of the addition result is reported, and the fact that the condition in this case has occurred is held in the flip-flop 8.

On the other hand, the result of addition in the adder circuit 5 is a result in which the carry in this case is not added.

This output is held in register IO.

And according to Flip Fronno 8's instructions.

A 9-carry circuit 11 is prepared for the value held in the register IO, and the output of the carry circuit 11 is selected by the switching circuit 12.

By the above correction, the addition result of the first digit in this case is obtained.

A carry-out signal (a carry signal to the fourth bit from the higher order bit) is also sent out, and one of these carry-out signals is selected by the switching circuit 12, and the selected carry-out signal is sent to the addition block of the upper digit. It is sent as a carry signal Ci+ to the fourth bit from the higher order.

Here, the performance decreases due to the time required for correction.

In the example of Figures 1 and 2, assuming that the input data is a completely random value, the 4-bit carry prediction circuit is in the carry pro gate state and there is a carry to the carry prediction circuit. It is.

Therefore, if the number of divisions by one is reduced or the number of inputs to the carry prediction circuit is increased, the above performance deterioration rate will be further reduced.

With the above configuration, ・Mother cage (or LSI
) If it is possible to improve the pin/gate ratio during implementation, thereby reducing the signal propagation time by more than the above-mentioned performance deterioration rate.

It is expected to be sufficiently effective.

〔Effect of the invention〕

As explained above, the present invention corrects the added value only when there is a carry zoropa r-) output from the carry prediction circuit of each digit and there is a carry to the carry prediction circuit. As shown in Figure 1, the adder is divided into circuit blocks for each digit, and
), and the adder can be configured without having a signal path whose propagation time becomes extremely long.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an adder according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the addition block in FIG. 1, and FIG. 3 is a block diagram showing the configuration of a conventional adder. It is a block diagram. 1.2, 3.4...addition block, 5...addition circuit. 6... Carry prediction circuit, 7... And date, 8
...Fritno flop, 10...Register, 11.
...Carry circuit, 12...Switching circuit.

Claims (1)

[Claims] The first to nth (n
≧2) digit addition block, of the (n-1) addition blocks excluding the first digit addition block, the i-th digit addition block is composed of the (i-1) digit addition input block. Upper J bits (1≦J≦m
) is input and predicts the carry to the i-th digit, and the calculation result in the carry prediction circuit and the (i-th
-1) An adder characterized by having means for correcting the addition result of the i-th digit depending on the presence or absence of a carry to the J-th bit from the higher order of the digit.