JPH01307957A - Search controller - Google Patents

Abstract

PURPOSE:To enable the stable retraction when a constant relative speed control loop is disconnected at the time of a high speed search control by holding a correction value of a speed error correcting means for the constant relative speed control loop at the previous value. CONSTITUTION:When data are not correctly reproduced by a reproducing data discriminator 24, while an output level of an equalizer 7 is more than a fixed value, it is decided that the speed control loop is disconnected, so that a changeover circuit 27 is changed, and the number of revolutions of a cylinder motor is forcibly changed up and down by a sweep control circuit 26. In this case, the correction value of the speed error correcting means 12 is held at the previous value by a previous value holding control circuit 11. Then, when the number of revolutions of a cylinder is turned by the sweep control circuit 26 into such a number of revolutions that a relative speed between a tape and a head is constant, the changeover circuit 27 is changed by the reproducing data discriminator 24, and a constant relative speed control is carried out by the speed control loop, while the speed error correcting means 12 is released from holding at the same time. By this method, the stabel retraction can be performed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a single-rotation head type digital audio cheap recorder (hereinafter referred to as DAT), and in particular to a high-speed search control device that performs a high-speed search when selecting a single song. Regarding.

[Conventional technology]

One method for controlling the relative speed between the tape and a head attached to the cylinder by changing the rotational speed of the cylinder according to the running speed of the tape is described, for example, in Japanese Patent Application Laid-Open No. 61-214164. has been done. In the above publication, a signal recorded on a tape is reproduced, a clock is extracted from the reproduced signal, and the cylinder rotation speed is controlled so that the frequency of the clock is constant. The relative speed of the was controlled to be constant.

In addition, as a method for correcting steady-state errors,
This is stated in Publication No. 7. In the above publication.

The steady phase error was corrected by calculating the average value of the steady phase error and adding the value and applying it to the motor.

[Problem to be solved by the invention]

However, in the prior art, the tape speed and the relative speed of the rotary head are controlled to be constant while reproducing the signals recorded on the tape. Relative speed - foot braking.

- No consideration was given to the case of stably retracting the power after it has gone out of order.

An object of the present invention is to be able to stably retract even if the relative velocity/foot braking is once removed. The purpose of the present invention is to provide a satay control device.

[Means for Solving the Problem] The above purpose is to set the correction value of the speed error correction means for correcting the speed error of the relative speed-foot braking loop to the front when the relative speed-foot braking loop is disconnected during high-speed search control. This is achieved by holding the value.

[Effect]

The speed error correction means corrects the speed error by detecting the average value of the speed error and adding it to the relative speed/reverse foot control loop. Also, if the relative speed-foot braking loop is disconnected, K
In order to hold the average value of the previous speed difference, the speed error correction means is removed.
Re-drawing can be performed stably at the central value.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which 1 is a cylinder, 2 is a cylinder, and 2 is a cylinder.
Numerals 2B and 2B are magnetic heads, 5 is tape, 4° 5 is a playback amplifier, 6 is a switching circuit for switching the magnetic head outputs of 2B and 2B, 7 is an equalizer that equalizes the waveform of the playback signal, 8 is a comparator, 9 10 is a frequency-voltage converter CF-V converter; 11 is a previous value hold control means; 12 is a speed error correction means; 16 is an adder; and 14 is a cylinder motor controller. Drive circuit, 15 is cylinder motor, 16.17
IJ19 is a reel that takes up two windings from the edge of the tape.
2 is a reel PG, 20 is a reel motor, 21 is a tape speed control circuit, 22 is a head switching signal generation circuit, 2
5 is a reference frequency of 10. 24 is a discrimination gain for determining whether or not reproduced data is correct; 25 is a cylinder FG; 26 is a Nisweep control circuit; and 27 is a switching circuit. or.

FIG. 2 shows the relationship among the cylinder rotational speed, cylinder motor terminal voltage, drive circuit input voltage, and PLL reproduction clock frequency.

First, a control operation for keeping the relative speed between the tape and the rotary head constant will be explained. Magnetic heads 2A and 2B attached to the rotating cylinder 1 reproduce recording signals from the tape 5, and P+ raw amplifiers 4 and 5 amplify the signals read by the heads. The switching circuit 6 selects the reproduction amplifier output for reproducing the output of the head in contact with the tape according to the output of the head switching signal generation circuit 22. This selected signal is ρ-shaped equalized by the equalizer 71C, binarized by the comparator 8, and sent to the PLL 9. In the PLL, a clock synchronized with the data is regenerated from the binarized data. Here, the frequency of the clock generated by M is proportional to the tape running speed controlled by the tape speed control circuit and the relative speed of the rotary head. That is, if the relative speed of the head with respect to the tape running speed is larger than the original speed, the frequency of the reproduced clock will be larger than the frequency corresponding to the transmission rate, and vice versa. becomes smaller. Therefore, in order to keep the frequency of the reproduced clock constant, the frequency of the reproduced clock is converted into a voltage by the p-v converter 10, and by controlling the number of rotations of the cylinder with this voltage, the relative speed of the tape and the head is increased. control so that it remains constant. Second
Figure (1) shows the motor drive voltage when the cylinder rotation speed changes from N to N, or N due to relative speed - foot braking as the tape running speed changes. To vary the motor drive voltage, v
.

It is necessary to change from V,,V,. Therefore, (2
] If there is no speed correction, the input voltage of the drive circuit 14? . ρ1 et al? ,,? , regenerate α to change it to
The clock frequency changes from fo to f2, causing a shift in the reproduced clock frequency. Therefore, the reproduced clock deviation Δf
1. F −V ffi conversion i output ΔvI for Δ/,
eΔv2 is detected by the speed error correction means 12&C and F
- Output of V converter 10 [2) 17 and drive circuit 14
As shown in (5), the regenerated clock frequency remains constant at 10 even if the cylinder rotation speed changes. Further, FIG. 5 shows a conversion method for converting the PLL reproduction clock frequency into a voltage. A gate signal is created based on the head switching signal, and when the envelope level of the reproduced signal is above a certain value within the time of the gate signal,
Further, the PLL reproduction clock when the reproduced data discriminator 24IC determines that the V reproduced data is correct is counted within the reference time, and an output voltage is generated according to the counted value.

FIG. 4 shows the timing of counting data for the head switching signal and the output of the F-V converter, and the clock is counted once for each valley head.
Convert to analog signal.

In this way, the signal on the tape is folded.

To control the relative speed of the tape and head at a constant level.

Due to sudden load fluctuations or disturbances in the tape running system, the relative speed becomes large and the PLL comes off, causing the control roof to come off by a degree.The PLL output frequency is independent of the relative speed error between the tape and the head. becomes. For this reason, the reproduced data discriminator 24 uses the output level of the equalizer 7 when the output level is above a certain level.

If the data cannot be reproduced correctly, it is determined that the speed control loop is out of order, the switching circuit 27 is switched, and the sweep control circuit 26 forcibly increases or decreases the rotational speed of the cylinder motor.

At this time, at the same time, the previous value hold control means 11 holds the correction value of the speed error correction means 12 at the previous value. When the cylinder rotational speed reaches a rotational speed at which the relative speed of the tape and the head becomes a constant value, the sweep control circuit 26iC switches the circuit 27iC to the reproduction data discriminator so that the reproduction data can be reproduced correctly. Then, the speed control loop performs relative speed constant control, and at the same time, the hold of the speed error correction means is released. During this switching, 2
Since the correction voltage by the speed error correction means is held at ℃, Δ71 (or Δft) in FIG. 2 is 7q, and the center of the speed control loop is always
It is possible to perform stable h-pulling.

Next, a simple embodiment of the speed error correction means of the present invention will be described using the fifth factor. FIG. 5 26 is an adder, 29
is a register, and 50 is a digital/analog converter. The speed error data d is the result of addition up to just before. By adding up the output of the register 29 and storing it again in the register, the average value of the speed fA difference data is extracted. This average value is converted into an analog signal f by a digital-to-analog converter, and the adder 15 in FIG. By driving the silicator motor 15 via the drive circuit 14, errors in the speed control loop can be corrected. The addition operation control signal e is converted to PLI by an F-V converter in order to prevent incorrect error data from being added when the signal cannot be obtained temporarily due to a loss of signal on the cheese.
, when the reproduced clock can be measured correctly, it becomes OK, and the register controls whether or not to output all the outputs of the m'JK device.

Next, another embodiment of the speed error detection means of the present invention will be described with reference to FIG. 62 is an up/down counter; 51 converts the input speed error data into the number of clocks according to the size of the data, and also changes the up/down counter according to the polarity of the data.
This is a data/clock number converter that outputs a T1/D switching signal that controls counting. The speed error data d is converted into a clock number by a data/clock number converter 61, and integrated by a U/D counter to extract the average value of speed errors. The addition control operation control signal e is
Similarly to the embodiment shown in FIG. 5, whether or not the U/D counter performs the counting operation is controlled.

Next, one embodiment of the previous value hold control means 11 of the present invention will be described using FIG. 7. 7. 65μ in FIG. 7 is a center value generating LE circuit that generates the center value of the speed error, that is, data with zero speed error. 64 is a switching circuit. When the speed control is off, the speed control off information C indicates that the speed control is off! l
The center value is output as the speed data d which is switched by the l switching circuit 34. For this reason, the speed error correction means 12:
Since the misplacement data is zero, there is no change in the additional value, and the previous value is held for the first correction period.

Next, another embodiment of the previous value hold control means will be described using FIG. 35 is a non-addition state signal circuit, and 66 is S! This is an ll switching circuit. Similar to FIG. 7, when the speed control is released, the switching circuit 66 switches 9.
A non-addition state signal is output as the increase operation control signal e&C. In this case, the speed error correction means 12 stops the addition operation no matter how many input data values there are, and holds the correction value at its previous value.

〔Effect of the invention〕

According to the above aspect of the present invention, in the relative speed-inverse control of the tape and the rotary head, even if the control is once lost, it can be pulled in at the center value of the speed control loop, so that re-drawing can be stably realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram of control contents of the embodiment of the present invention, and FIG. FIG. 4 is a waveform diagram of the % section of the F-V conversion circuit of the present invention. 5 and 60 are block diagrams of examples of speed error correction means,
7 and 6 are block diagrams of the previous value hold controller stage. 11...Previous value hold control means. 12...Speed error correction means. Figure 2 also shows 3 ku 4 1, 1, 2, 1, 5 5 ku, b,

Claims (1)

[Claims] 1. A clock reproducing means for reproducing a clock from a reproduced digital signal, and a frequency-voltage converting means for generating a voltage according to the frequency of the reproduced clock, and an output voltage of the frequency-voltage converting means. A search control device that controls the relative speed of the rotary head and tape to a constant value by applying voltage to a rotary head driving motor includes a speed error correction means, and a speed error correction means that detects when the speed control is off and corrects the speed error. A search control device comprising a control means for holding a correction value of the correction means at a previous value. 2. The control means for holding the correction value of the speed error correction means at the previous value, the speed error input to the speed error correction means,
2. The search control device according to claim 1, wherein control is performed to hold a previous value by using a center value of the speed error system instead of the speed error sent from the speed control system. 3. The control means for holding the correction value of the speed error correction means at a previous value is controlled to hold the previous value by stopping the correction value detection operation of the speed error correction means. Search control device.