JPH01307342A - Data terminal equipment - Google Patents

Abstract

PURPOSE:To prevent system-down due to switching setting error or the like by monitoring a clock signal in each signal group inputted via plural line interfaces and generating a switching signal to a switch automatically depending on the changing state of each clock signal. CONSTITUTION:A switching signal generator 3 always monitors the changing state of received clock signals 6A, 6B in a signal group inputted from line interfaces 1A, 1B so as to discriminate which of the line interfaces 1A, 1B has the change to be detected. When any change is detected in a received clock signal from the line interface 1A, a signal of a state to select the line interface 1A as a switching signal 8 is given to a changeover device 2, while a signal of a state selecting the line interface 1B is sent to the changeover device 2 when there any change is detected in the reception clock signal from the line interface 1B. Thus, the system-down due to switch setting error is not caused.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data terminal device that transmits and receives digital data via a communication line.

[Conventional technology]

FIG. 4 is a block connection diagram showing a conventional data terminal device. In the figure, IA and IB are two line interfaces that interface with a communication line, and 2 is one of a plurality of received signal groups. 4 is an internal processing circuit, 5A and 5B are multiple systems (
Here, 7 is a transmission signal group, and 9 is a switch that outputs a switching signal to the switch 2. In FIG.

Furthermore, FIG. 5 shows an example of the internal configuration of the switching device 2.
a, , 2al *2bl *2bl is an and gate,
2Qlt2cl is an OR gate, and 2d is an inverter.

Next, the operation will be explained. In Fig. 4, line interfaces IA and 1B have configurations with different standards; for example, line interface 1A is EIA R8.
-449M, and line interface 1B is CCIT.
It is TX, type 21. Normally, only one of these different line interfaces IA and IB is used, and which one is used is determined by the applied system. When the line interface IA is used, the received signal group 5A is subjected to electrical level conversion and other treatments at the line interface 1A, and then output to one input section of the switch 2. In addition, when line interface 1B is used, received signal group 5B is sent to line interface I.
After undergoing processing such as electrical level conversion at B, the signal is output to the other input section of the switch 2.

Switcher 2 has line interface 1! , and line interface 1B to be used, and if line interface 1A is used, the output signal from one line interface is used as the output of switch 2. Further, when the line interface 1B is in use, the output signal from the line interface 1B is outputted to the internal processing circuit 4 as the output of the switch 2. The internal processing circuit 4 performs signal processing on the output of the switching device 2 according to a predetermined procedure, and outputs it to the line interface 1A or 1B as a transmission signal group I as necessary, where it performs electrical level conversion, etc. After receiving the data, it is output to the communication line side.

Further, the settings of the switch 9 are manually set in a semi-fixed manner depending on the form to which the data terminal device is applied.

The switch 2 in FIG.
．． Second AND gates 2b, 2b, and yF7'j-
It has a configuration in which basic components consisting of 1'2c and e2cl are arranged side by side. When the output of the inverter 2d is at IHI level, the first AND gate 2al+2al outputs the output signal group of one line interface as it is to the OR game) 2c1.2cl, and the output of the inverter 2d becomes I
When it is at LI level, the 'L' level is used regardless of the state of the output signal group of one line interface MK) 2c, t
Output to 2cl. On the other hand, the second AND gate 2bt,
2bt is when the input of inverter 2d is at lH'' level,
The output signal group of line interface 1B is output as is to base agate 2c1e2C1, and inverter 2d
When the input is at 'IL' level, it outputs 'L' level to 2c and e2cl regardless of the state of the output signal group of line interface IB.
outputs the lHI level when the input is at the ILI level, and outputs the lL'' level when the input is at the lH'' level.

Further, the OR gates 2c and *2c output the %'H' level if either one of the two inputs is at the @H' level.

Next, when the contact of the switch 9 is closed, the input of the inverter 2d is set to the ILI level, and when the contact is open, the input of the inverter 2d is set to the IH'' level.

Now, set the contact status of switch 9 to close when selecting one line interface, so that line interface 1B
If you open it when you select the above, the first AND gate 2ale2ml + the second AND gate 2b,, 2b,, or game) 2cl.

Due to a series of operations of 2cl and inverter 2d, line interface 1 is connected to the output of 2cl+2c.
Only one of the human output signal and the line interface 1B output signal is selectively output. [Problem to be Solved by the Invention] Since the conventional data terminal device is configured as described above, each Depending on the standards of the systems connected to the line interfaces IA and IBK, switching settings for switch 9 must be performed manually, and a simple switch setting error may cause the terminal device or the above system to go down. There were problems such as:

This invention was made to solve the above-mentioned problems, and it automatically determines the line interface to be applied according to the signal status of a signal group without human intervention.
It is an object of the present invention to provide a data terminal device capable of performing a switching operation so as to input an optimal signal group to an internal processing circuit.

[Means to solve the problem]

By providing a switching signal generator, the data terminal device according to the present invention monitors specific signal states among a group of signals input via a plurality of line interfaces, and depending on the signal state, A switching signal for controlling switching of the switching device is generated.

[Effect]

The switching signal generator according to the present invention generates a switching signal according to each state of a group of output signals of a monostable multivibrator activated by change information of an input clock signal, and by this switching signal, Controls a switch for selectively outputting a group of signals from each interface with different standards.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, IA and IB are two line interfaces that interface with a communication line, and 2 is a received signal group 5A.
, 5B, 3 is the switch 2
4 is an internal processing circuit, 6 is a reception clock signal, T is a group of transmission signals, and 8 is a switching signal.

FIG. 2 is a circuit diagram of the switching signal generator 3, 3a.
, 3b are first and second retriggerable monostable multivibrators (hereinafter referred to as MM2, respectively);
3c is an AND gate, and 3d is an inverter. Also,
FIG. 3 is a truth table diagram showing the operation of the circuit shown in FIG. 2.

Next, the operation will be explained. In FIG. 1, the operations of line interface IA, line interface 1B, and switching device 2 are the same as in the conventional example, and therefore, redundant explanation thereof will be omitted here. The switching signal generator 3 receives received clock signals 6A and 6B from the signal group output from the line interface 1 and the line interface 1B, respectively. These reception clock signals 6A and 6B are used to indicate the delimitation point for each bit of the reception data in the signal group, and normally have two logic change points within one bit time width. In other words, if the data transmission rate is 1200 bps, the received clock signal will change 2400 times per second.

In the switching signal generator 3, these received clock signals 6A,
6B is constantly monitored, and it is determined from which line interface IA or IB a change is detected, and if a change is detected in the received clock signal from one line interface, a switching signal is sent. 8, a signal indicating that the line interface IAI-M is selected is output to the switch 2. On the other hand, if a change is detected in the received clock signal from the line interface 1B, a signal indicating that the line interface 1B is selected is output to the switch 2. Output each to 2.

Note that normally there are two line interfaces IA.

1B will not be connected to the outside at the same time, but if such a situation occurs, the switching signal will be switched as a result of priority determination within the switching signal generator 3 so that the state of the switching signal 8 will not become undefined. Signal 8 is output.

Next, the operation of the switching signal generator 3 will be described.
I3a and MM23b each detect a change point in the input signal, operate using this as a trigger signal, and output an lH'' level pulse with a predetermined constant time width T seconds.Note that MMI3a and MM23 Both triggers are possible for both l: >, lal Even if a level pulse is being output, if a new trigger signal (change point of the input signal) is received, IH will be activated again for 1 second from that point. Operates to maintain level output. Now, receive clock signal 6
A, 6B period 11 (seconds), MMI 3 a and MM
23 b's output pulse width is T (seconds), T ) t.

If the relationship is set so that
The outputs of MMI3a and MM23b continue to maintain the 1H'' level.The outputs of MMI3a and MM23b are as follows:
Priorities are assigned between the inverter 3d and the controller 3c, and the output of the MM23b is processed more preferentially than the output of the MMI3a. FIG. 3 shows the truth value of this priority determination, and shows the correspondence between the output states of MMI 3 a and MM 23 b and the signal output as the switching signal 8. In this case, when the switching signal 8 is at lL@ level, the MM23b side is selected, and when it is at "H" level, the MM23b side is selected.
The I3a side is selected and the MM23b side is given high priority.

The switching signal 8 thus generated is supplied to the switch 2 of FIG. 1 to control the operation of the switch 2. The operations of this switch 2 and internal processing circuit 4 are the same as in the conventional example.

Note that in the above embodiment, there are two line interfaces IA,
Although the one with IB is shown, when it has three or more line interfaces, the number of input systems of the switch 2 increases,
As the number of switching signals 8 increases, a larger number of signal monitoring circuits in the switching signal generator 3 are arranged in parallel, but the basic operation is the same as in the above embodiment.

Further, a reception clock signal 6A is used as the monitoring signal.

Although an example using 6B was shown, a transmission clock signal may also be used.

Further, in the above embodiment, the signal group to be switched by the switch is a line interface IA having a different standard.

Although we have explained the case where the received signal group is input to 1B, each line interface IA, I
A group of transmission signals may be transmitted through B, and the same effect as in the above embodiment can be achieved.

〔Effect of the invention〕

As described above, according to the present invention, the clock signals in each signal group input via a plurality of line interfaces are monitored, and a switching signal is generated for the switching device according to the change state of each clock signal. By simply adding this switching signal generator, the required signal group can be input into the internal processing circuit without any troublesome manual operation, which is much easier than conventional switching signal generators. This has the advantage of being able to prevent system failures due to incorrect switch settings.

[Brief explanation of the drawing]

FIG. 1 is a block connection diagram showing a data terminal device according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing the internal configuration of the switching signal generator in FIG. 1, and FIG. 3 is the circuit shown in FIG. 2. FIG. 4 is a truth table diagram showing the operation, FIG. 4 is a block connection diagram showing a conventional data terminal device, and FIG. 5 is a circuit diagram showing the internal configuration of the switch in WJ4. IA and IB are line interfaces, 2 is a switch, 3 is a switching signal generator, 4 is an internal processing circuit, 5A and 5B are signal groups (received signal groups), and 8 is a switching signal. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Figure 1 No. 21 No. 8 Shisa 1 No. 2 Figure 2 s 3 Figure

Claims (1)

[Claims] A plurality of line interfaces connected to a communication line and having different standards; a switching device that selects and outputs one signal group from among the plurality of signal groups inputted via each of these line interfaces; In a data terminal device equipped with an internal processing circuit that processes the signal group selected by the switch according to a predetermined procedure, a switching signal is sent to the switch according to the signal state of the signal group of multiple systems from each line interface. A data terminal device characterized by being provided with a switching signal generator for outputting.