JPH01304534A - Digital multiplier - Google Patents

Abstract

PURPOSE:To decrease the number of stages of a full adder and to avoid the increase of a circuit scale despite the increase of the number of bits by using plural shift registers, a latch circuit and a full adder and storing the interim arithmetic results in the shift registers. CONSTITUTION:A multiplicand 11 and a multiplier 12 are loaded into a latch circuit 1 and a shift register 2 respectively by a load/shift switching signal 21. At the same time, a shift register 4 is cleared. The multiplicand loaded into the circuit 1 is inputted to one of two inputs of a full adder 3 as a signal 16. The register 4 is cleared by the signal 21 and therefore both outputs 13 and 14 are equal to 0. While the other input of the adder 3 is equal to the output 13 that lacks the lowest rank bit of the register 4 and therefore smaller than the signal 16 by an extent equal to one bit. On the contrary, the signal 16 has the double value and therefore the signal 17 has the value 3/2 times as much as the multiplicand 11.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital multiplier, and particularly to a digital multiplier using a shift register or a latch circuit.

[Conventional technology]

Conventionally, digital multipliers have tended to require high-speed operation, and in the case of a multiplier with n hits (n is a natural number), nXn full adders or a second-order Booth (B o
o th ) using the algorithm of n, X n÷
Multiplication is performed using 2+2Xn full adders while maintaining high speed.

FIG. 4 is a circuit diagram of a conventional multiplier, and FIG. 5 is an enlarged view of the unit circuit shown in FIG. 4.

As shown in FIG. 4, this multiplier circuit represents a 3-pixel multiplication circuit and realizes P=xXy.

Here, if a 16-bit 1 multiplier is implemented using a second-order Booth algorithm, approximately 100 4-bit full adders, logic gates, etc. are required in terms of TTL ICs.

[Problem to be solved by the invention]

Since the above-mentioned conventional digital multiplier places emphasis on calculation speed, it has the disadvantage that as the number of bits increases, the circuit scale increases by the square of the number of bits.

An object of the present invention is to provide a digital multiplier that does not require an increase in circuit scale even when the number of bits in the digital multiplication circuit increases.

[Means to solve the problem]

The digital multiplier of the present invention includes: a latch circuit for loading the multiplicand; a first shift register for loading the multiplier;
All output bits of the latch circuit are connected to one input terminal of the two input terminals of a full adder, and the full amount of the full adder is input, and all output bits except the least significant bit are calculated. a second shift register which outputs the result and is connected to the other input terminal of the full adder; and the lowest output pins 1 to 1 of the second shift register.
and a third shift register that outputs all output bits as the operation result, and loads the multiplicand and the multiplier into the latch circuit and the first shift register, respectively, by a load/shift switching signal, and also loads the multiplicand and the multiplier into the second shift register, respectively. 2, and causes the first to third shift registers to perform shift operations by the tarlock signal, and loads the single output pin of the first shift register into the second shift register. / Configured by connecting to the shift switching terminal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a digital multiplier for explaining one embodiment of the present invention.

As shown in FIG.
A shift register 2 to be shifted, a full adder 3 to which all output bits of the latch circuit 1 are connected to one input terminal of the two input terminals, and a full adder 3 to which all output bits of the full adder 3 are input, and the lowest In addition to outputting all output bits except bits as operation results, that is, loading/shifting intermediate results of the operation, the shift register 4 connected to the other input terminal of the full adder 3 and the lowest order of the shift register 4 The shift register 5 receives the output bits of , and outputs all output bits as the operation result, that is, loads the final result of the operation.

First, the latch circuit 1 is activated by the load/shift switching signal 21.
Multiplicand 11 is loaded into shift register 2, multiplier 12 is loaded into shift register 2, and shift register 4 is cleared. The multiplicand 11 loaded into the latch circuit 1 becomes one input of the full adder 3 as a signal 16. Since shift register 4 is cleared by load/shift signal 21, outputs 13 and 14 are all 0.

Further, the output 17 of the full adder 3 has the same value as the signal 16 and becomes an input to the shift register 4. Here, the multiplier 12
Assuming that the lowest output of the shift register 2 loaded with is "H", the signal 18 causes the shift register 4 to load, so the data of the signal ]7 is output to the outputs 13 and 14.
loaded as . At this time, shift I registers 2 and 5 are simultaneously shifted to the lower position by clock 22. That is, although the serial input of the shift register 2 does not need to be particularly specified, the serial input of the shift registers uses the least significant output bit 14 of the shift register 4 as an input signal.

On the other hand, the other input of the full adder 3 is the output 13 of the shift register 4 excluding the least significant bit, so it is one bit smaller than the signal 16. Conversely, the signal 16 is twice the value. Therefore, the signal 17 has a value 3/2 times the multiplicand 11. Here, if the second lowest bit of the multiplier 12 is H''', the signal 18 puts the shift register 4 into the load state, and the three times the value is loaded as the outputs 13 and 14.

However, when the second pick from the bottom is L”,
The signal 18 puts the shift register 4 into a shift state and shifts one bit to the lower order.

When this operation is repeated for the required number of bits, the least significant bits of the addition results for each clock are sequentially loaded into the shift register 5. As a result, the value of the product of the multiplier 12 and the multiplicand 11 is output as outputs 13, 14 and 15.

Next, the above-mentioned embodiment of the present invention will be explained in more detail with reference to FIGS. 2 and 3.

FIG. 2 is a specific circuit diagram when the input in FIG. 1 is 3 bits, and FIG. 3 is a signal waveform diagram for explaining the operation of the circuit shown in FIG. 2. Here, the value of the multiplier 12 shown in FIGS. 2 and 3 is 5 (101), and the value of the multiplicand is 6 (1
, 10), the operation of the circuit will be explained.

First, in section A shown in FIG. 3, when the load/shift signal 21 becomes a load, the shift register 4 is cleared, the multiplicand 11 is loaded into the latch circuit 1 by the clock 22, and the multiplier 12 is loaded into the shift register 2. loaded. When the latch circuit 1 latches the multiplicand 1], the signal 16 becomes 6 (110) and is input to the full adder 3.

Here, since the shift register 4 is cleared, the outputs 13 and 14 are 0. Therefore, signals 1-7
becomes 6...6+0 (0110).

On the other hand, signal 18 is the lowest output of shift 1 to register 2 loaded with multiplier 12, and from section A to B it is "H".
'' and puts the shift register 4 into the load state, so the signal 17 is loaded as outputs 13 and 14.At this time, output 14 becomes output 15 as the input of shift I register 5, but in the final result, The data is discarded as meaningless data. Also, at this time, the shift register 2 is shifted to the lower position.

Next, in section B, the signal 17 is output as the sum of the signal 16 and the signal 13 as 9...6+3 (1001).

However, since the signal 18 is "L'' from section B to C, the shift register 4 does not perform a load operation but performs a downward shift operation, so that outputs 13 and 14 are 6 (01
10) to 3 (0011). At this time, the shift register 5 simultaneously outputs the signal 14 as an output 15.

Next, in section C, signal 17 is 6+1...7(01
11), and signal 1 from section C to D.
8 is H''', shift register 4 performs a load operation, and signal 17 becomes outputs 13 and 14. At the same time, shift register 5 loads signal 14, performs a shift operation internally, and outputs signal 15 as output 15. Output.

As mentioned above, the output from section A to D is 13°14.
15 becomes 30 (01110), which means that 6×5−=30 calculations have been performed.

Note that when a 16-bit multiplier is configured according to this embodiment,
When converted to a TTL IC, it can be configured with about 19 pieces using a 4-bit full adder, an 8-bit D latch, a 4-bit shift register, etc.

〔Effect of the invention〕

As explained above, the digital multiplier of the present invention reduces the number of stages of full adders by using a plurality of shift registers, latch circuits, and full adders and accumulating intermediate results of operations in the shift registers. For example, in the case of a 16-bit multiplier, the scale can be approximately 115.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a digital multiplier for explaining one embodiment of the present invention, FIG. 2 is a specific circuit diagram when the input in FIG. 1 is 3 bits, and FIG. 4 is a circuit diagram of a multiplier showing an example of a conventional multiplier, and FIG. 5 is an enlarged view of the unit circuit shown in FIG. 4. 1... Latch circuit, 2, 4... Parallel load/serial shift register, 3... Full adder, 5... Serial in/serial shift register. Ri7 figure Seri? Factor 6 x 5 = 30 ri3■

Claims (1)

[Claims] a latch circuit for loading a multiplicand, a first shift register for loading a multiplier, a full adder in which all output bits of the latch circuit are connected to one input terminal of two input terminals, and the full adder a second shift register that receives all the output bits of the full adder, outputs all output bits except the least significant bit as an operation result, and is connected to the other input terminal of the full adder; and a third shift register that receives the lowest output bit and outputs all output bits as operation results, and loads a multiplicand and a multiplier into the latch circuit and the first shift register, respectively, by a load/shift switching signal. At the same time, the second shift register is cleared, and a clock signal causes the first to third shift registers to perform a shift operation, and a single output bit of the first shift register is transferred to the second shift register. A digital multiplier characterized in that it is connected to the load/shift switching terminal of the.