JPH01303938A - Power line carrier data transmitter - Google Patents

Abstract

PURPOSE:To reduce the effect of noise by sending the same data again and allowing a receiver side to apply averaging processing to the data. CONSTITUTION:An information signal fed to an input terminal 2 is converted into a base band signal by a data encoder 3 and the signal is sent N times by a continuous data retransmission circuit 4. Then the same data is sent for N times to a modulator 5 and modulated into a biphase PSK modulation signal. Only the main lobe of a spectrum of the modulation signal passes through a BPF 6 and the signal is sent to a power line 1. The undesired frequency component of the modulation signal sent to the power line 1 is eliminated by a BPF 11. Then the result is fed to a synchronizing detector 12, where the signal is subject to synchronizing detection. A carrier component is eliminated from a demodulated continuous retransmission signal by an LPF 13 and averaging is applied by an averaging processing circuit 14. Then the S/N of the output processing for the processing is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a power line carrier data transmission device that utilizes a power line as a data transmission line.

[Conventional technology]

This kind of conventional power line carrier data transmission device performs data transmission using a power line for the purpose of supplying power. This also eliminates the need to lay cables for data transmission, thereby reducing costs.

[Problem to be solved by the invention]

However, in the past, power lines, whose original purpose was to supply power, were used for data transmission, so noise was generated from the loads connected to the power lines.

There has been a problem in that data transmission with a good S/N ratio cannot be obtained due to transmission characteristics having transmission zero points.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a power line carrier data transmission device that can perform good data transmission.

[Means to solve the problem]

Means for achieving the above object in the present invention includes: a data encoder for converting an information signal into a baseband signal; a continuous data retransmission means for converting the baseband signal into a continuous continuous retransmission signal; a modulating means for modulating a continuous retransmission signal and sending it to a power line; a synchronous detection means for detecting the modulated signal modulated from the power line and performing synchronous detection to obtain a demodulated continuous retransmission signal; averaging processing means for performing averaging processing; demodulation means for demodulating the averaged signal obtained by the averaging processing means into a baseband signal; and data for demodulating the baseband signal into data. The present invention relates to a power line carrier data transmission device characterized by comprising a decoder.

[Effect]

In the above configuration, in the transmitter, the data encoder converts the information signal into a baseband signal, the continuous data retransmission means converts the baseband signal into a continuous continuous retransmission signal, and the continuous retransmission signal is modulated and sent to the power line. In the receiving section, a modulated signal is detected from a power line, a periodic detection means performs synchronous detection, an averaging processing means performs averaging processing on the plurality of synchronously detected signals, a demodulation means demodulates the signal into a baseband signal, The data decoder demodulates the data to obtain an information signal, retransmits the same data, and performs averaging processing to reduce the influence of noise.

〔Example〕

Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing a power line carrier data transmission device. 1 is a power line of AClooV, for example, Tx is a transmitter, and Rx is a receiver. Reference numeral 2 denotes an input terminal of the transmitter Tx, to which an information signal is supplied. 3 is a data encoder connected to the input terminal 2, 4 is a continuous data retransmission circuit connected to the subsequent stage of the data encoder 3, and 5 is a 2-phase PSK (Ph
6 is a band-pass filter connected to the output side of the modulator 5, and 7 is a band-pass filter connected to the output side of the band-pass filter 6 for matching with the power line 1. The output side of the interface circuit 7 is connected to the power line 1 via a plug 8. 9
is a frequency synthesizer that operates in synchronization with the power supply, and its output is connected to the data encoder 3゜continuous data retransmission circuit 4, 2.
The signal is supplied to a phase PSK modulator 5.

Reference numeral 10 denotes an interface circuit of the receiving section Rx, which is connected to the power line 1 via a plug 8. 1
1 is a bandpass filter connected to the output side of the interface circuit 1o, 12 is a two-phase PSK synchronous detector (hereinafter referred to as a synchronous detector) connected to the output side of the bandpass filter 11, and 13 is a synchronous detection A low-pass filter 14 is connected after the filter 12, and 14 is a low-pass filter 13.
15 is a data decoder connected to the subsequent stage of the averaging processing circuit 14, 16 is an information signal output terminal, and 17 is a receiving section R.
It is a frequency synthesizer that operates in synchronization with the power supply on the x side,
Its output is a synchronous detector 12, an averaging processing circuit 1
4. The data is supplied to a data decoder 15.

The details of the frequency synthesizers 9 and 17 are shown in Figure 2 (A).
, is shown in (B). Figure 2 (8) shows the transmitter T×
Fig. 2(B) shows the receiving section R.
x frequency synthesizer. 20 is a power supply AC signal separated by an interface circuit 7.10, for example 501
(The input terminal to which z is supplied, 21 is a power supply frequency detection circuit that reduces harmonic distortion and subharmonic components (jitter components) of the power AC signal supplied to the input terminal 20.22.23. ...28 is a PLL circuit connected to the output side of the power supply frequency detection circuit 21, which multiplies the power supply frequency and generates various frequencies as explained below.The PLL circuit 22 is The clock signal fl is sent to the data encoder 3, the PLL circuit 23 sends the clock signal f2 to the continuous data retransmission circuit 4, and the PLL circuit 23 sends out the clock signal f2 to the continuous data retransmission circuit 4.
The circuit 24 is for sending a carrier signal r3 to the modulator 5. Then, the PLL circuit 25 sends out the clock signal f1 to the data decoder 15, the PLL circuit 26 sends out the clock signal f2 to the averaging processing circuit 14, and the PLL circuit 26 sends out the clock signal f2 to the averaging processing circuit 14.
The L circuit 27 sends a carrier signal f3 to the synchronous detector 12.

Next, the operation of one embodiment of the present invention having the above configuration will be explained. The information signal supplied to input terminal 2 is
The data encoder 3 converts the signal into a baseband signal as shown in FIG. 3(A).

This penis band signal is a data signal of time T as shown in FIG. 4(A). This signal is sent out eight times by the continuous data retransmission circuit 4 as shown in FIG. 4(B). This same data is then sent to the modulator 5 eight times, as shown in FIG.
The signal is modulated into a two-phase PSK modulated signal as shown in B). This modulated signal passes only the main lobe of the spectrum through a bandpass filter 6, is supplied to an interface circuit 7, and is sent out to the power line 1. At this time, the frequency synthesizer 9 sends out the clock signals r, , r, and carrier wave signal f3 as described above to control the transmitter Tx.

The modulated signal sent to the power yA1 enters the interface 10 of the receiving section Rx under the influence of noise, as shown in FIG. 3(C). In the modulated signal containing noise components in this way, unnecessary frequency components are removed by the bandpass filter 11. The signal is then supplied to the synchronous detector 12 and subjected to synchronous detection, resulting in a demodulated continuous retransmission signal of the detected baseband signal containing noise, as shown in FIG. 3(D). The carrier wave component of this demodulated continuous retransmission signal is removed by a low pass filter 13. And the average processing circuit 1
Averaging is performed at 4. This arranging process is performed by writing N pieces of the same data into a memory, then reading it out, and performing level addition processing. Therefore, since the noise components within the signal frequency band are basically added by square roots, when N=100, the S/N is improved by 20 dB. The output after this processing is shown in Fig. 4 (
The signal C) is supplied to the data decoder 15 as a signal indicated by C).

Then, it is decoded by the data decoder 15 and output terminal 1
6, an information signal is obtained. Such an operation of the receiving section Rx is performed using the clock signal [1] by the frequency synthesizer 17.
, [2, 1lli12 Sends out the transmission signal f3 and transmits the transmitter Tx
It is synchronized with the operation of

FIG. 5 shows another embodiment in which the present invention is applied to half-duplex communication. In this case, a transmitting section Tx and a receiving section Rx are provided at points a and b. Transmitter Tx.

The receiving units Rx are each controlled to be synchronized by a common frequency synthesizer 30. In addition, the transmitter Tx
, receiving unit Rx have a common interface 31 and are matched with the power line 1. Between the bandpass filter 6 of the transmitter Tx and the interface 31, the receiver R
A switch circuit 32 is provided between x and the bandpass filter 11.
．． 33 is inserted. The switch circuits 32 and 33 are opened and closed by a drive circuit 34, and one of the switch circuits 33 is driven via an inverter 35, so that the switch circuits 32 and 33 are alternately opened and closed.

Reference numeral 36 denotes an identification circuit that detects the presence or absence of the output of the bandpass filter 6 and the output of the interface circuit 31, and identifies whether it is in a transmitting state or a receiving state.

During transmission, the output of the identification circuit 36 drives the drive circuit 34 to close the switch circuit 32 and open the switch circuit 33. On the other hand, during reception, the output of the identification circuit 36 opens the switch circuit 32 and closes the switch circuit 33.

In this way, the data transmission device of FIG.
2.33 is opened and closed to enable bidirectional data transmission in a half-duplex manner, and the data transmission operation is performed in the same manner as in the embodiment of the present invention described above.

FIG. 6 shows the configuration of the frequency synthesizer 30 in FIG. 5. A power frequency detection circuit 41 detects the power frequency from the AC power supplied to the input terminal of the input terminal 40, and the PLL circuits 42, 43, and 44 multiply this power frequency to generate a clock signal fl for the data encoder 3 and continuous data retransmission. A clock signal r2 for the circuit 4 and a carrier wave signal f for the two-phase PS modulator 5 are sent out.

In this way, the PLL circuits 42, 43, and 44 perform synchronization control during transmission by the transmitter Tx. On the other hand, the PLL circuits 45, 46, and 47 perform synchronization control during reception by the receiving section Rx. PLL circuit 45
sends a clock signal f+ for data decoding 15,
The PLL circuit 46 sends out the clock signal f2 for the averaging processing circuit 14, and the PLL circuit 47 sends out the clock signal f2 for the averaging processing circuit 14.
A carrier wave signal f3 for the purpose is transmitted. Then, a power supply frequency detection circuit 41 and a PLL circuit 45°46.
A phase circuit 48 is inserted between the transmitter 47 and the transmitter 47 to give a delay to the power frequency and provide a phase difference in synchronization between the transmitting side and the receiving side to prevent mutual interference from occurring.

According to each of the embodiments of the present invention described above, the same data is retransmitted and sent out to the power line 1, and averaging processing is performed on the receiving side to reduce the influence of noise. And send,
Carrier signal for reception.

Since the clock signal is obtained by transmitting the power supply frequency, synchronization between the transmitter Tx and the receiver Rx is ensured, and accurate data transmission is achieved.

It should be noted that a digital method in which the arranging process is performed by converting the amplitude of the data signal into a numerical value is suitable for implementation in an integrated circuit. Therefore, although digital averaging processing is performed in the embodiment of the present invention, analog averaging processing may also be performed.

〔Effect of the invention〕

As described above, according to the present invention, when transmitting data using power lines that are susceptible to noise, the same data is retransmitted and averaged on the receiving side, thereby reducing the influence of noise. can do.

This can be applied particularly to power lines in factories and the like where a lot of noise is generated to provide a highly effective power line carrier data transmission device.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 (
A) and (B) are block diagrams showing the frequency synthesizer in FIG. 1, FIGS. 3 and 4 are waveform diagrams for explaining the operation in FIG. 1, and FIG. 5 is another embodiment of the present invention. FIG. 6 is a book diagram showing the frequency synthesizer in FIG. DESCRIPTION OF SYMBOLS 1... Power line, 2... Input terminal, 3... Data encoder, 4... Continuous data retransmission circuit, 5... 2-phase PSK modulator, 7... Interface, 9,17.
... Frequency synthesizer, 12... Two-phase PSK synchronous detector, 14... Averaging processing circuit, 15...
Data decoder, 16...output terminal, Tx...transmitter, Rx...receiver. Patent applicant: Victor Japan Co., Ltd. Representative: Kunio Kakiki (B) Figure 2. dB dB B

Claims (1)

[Claims] a data encoder for converting an information signal into a baseband signal; a continuous data retransmission means for converting the baseband signal into a continuous continuous retransmission signal; and a modulation means for modulating the continuous retransmission signal and transmitting it to a power line. , a synchronous detection means for detecting a modulated signal modulated from the power line and performing synchronous detection to obtain a demodulated continuous retransmission signal, an averaging processing means for performing averaging processing on the demodulated continuous retransmission signal, A power line comprising demodulation means for demodulating the averaged signal obtained by the averaging processing means into a baseband signal, and a data decoder for demodulating the baseband signal into data. Transport data transmission equipment.