JPH01303740A - Wiring system between transistors - Google Patents

Abstract

PURPOSE:To contrive the minimization of the area of a wiring region usable in a cell by a method wherein the reference with respect to selecting wirings performed in a wiring region, and a reference with respect to occurrence of feedthroughs are provided. CONSTITUTION:A net that links gate terminals only of transistors on an upper side is wired in an upper channel, a net that links gate terminals only of transistors on a lower side is wired in a lower channel and nets other than these nets are wired in the upper or lower channel forming fieldthroughs. Accordingly, the number of wirings to need the fieldthroughs can be minimized. Moreover, the passing-through positions of the fieldthroughs are limited to gaps, at which diffused layers are isolated from one another, and positions, where the diffused layers are connected to one another, and a wiring length to increase for an increase in the lateral length of a wiring region due to an isolation of the diffused layers and the formation of the fieldthroughs and the sum of the number of the lateral wirings on each (x) coordinate, which is increased for the wiring length, are minimized. Thereby, an increase in the area of the wiring region can be minimized.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a wiring method between terminals of a transistor.

[Conventional technology]

Conventionally, the wiring method within a cell in which the distance between the cell's current and ground wires is fixed has been discussed in Information Processing Society of Japan Design Automation Study Group Material 22-4 (1984), pages 1 to 9. There is.

[Problem to be solved by the invention]

In the above-mentioned conventional technology, in wiring using feed-throughs, the passing position and number of feed-throughs are estimated and secured in advance at the stage of MOS)-transistor placement processing, and the MO
Only these feedthroughs were used for wiring between S transistors.

For this reason, ■ some wiring cannot be completed due to a lack of these feedthroughs, (2) unused feedthroughs are searched and selected even if the wiring takes a large detour, and (2) unused feedthroughs remain and the area of the cell is reduced. The theme was to increase the number of people.

An object of the present invention is to solve the above problems by using a MOS)
- Considering that feed-through occurs in the wiring process between MOS transistors, not in the placement process of transistors, criteria for selecting the wiring to be performed in each wiring area and criteria for generating feed-through are established for the wiring area to be used in the cell. An object of the present invention is to provide a wiring method between MOS transistors that minimizes area.

[Means to solve the problem]

The issues regarding the above feedthrough are (a) dividing a given net into nets that should be routed within the upper channel of each upper and lower row and nets that should be routed within the other channels; (b) dividing the given net into nets that should be routed within the upper channel of each upper and lower row (c) For nets to be routed in channels other than those in (a), determine channels to route these according to the following criteria; ■ Route a net that connects only the gate terminal of the upper transistor in the upper channel, ■ Route a net that connects only the gate terminal of the lower transistor in the lower channel, ■ Route nets other than ■ and ■ through feed-through. (d) For each net belonging to ■ in (c) that is created and routed within the upper or lower channel, place (ni) in the following two selectable positions (i) and (ii).
) Create a feedthrough according to the criteria of (i) The diffusion layer is separated because the adjacent diffusion terminals of adjacent transistors are at different potentials, and the feedthrough can be passed through the gap, ( 5) The adjacent diffusion terminals of transistors arranged adjacent to each other have the same potential, so the diffusion layer is shared, and this shared diffusion layer is separated to secure a position for passing the feedthrough. ) The increase in the lateral length of the wiring area due to the separation of the diffusion layer in (ii), the increase in the wiring length due to the creation of feedthroughs, and the increase in the number of lateral wiring on each X coordinate due to this. Minimize the sum.

This is achieved by:

[Effect]

A net that connects only the gate terminal of the upper transistor is routed within the upper channel, a net that connects only the gate terminal of the lower transistor is routed within the lower channel, and feedthroughs are created for other nets to connect the upper, or route within the bottom channel. As a result, first, the number of wiring lines requiring feedthrough can be minimized.

Furthermore, in determining the feedthrough passage position, all the gaps where the diffusion layers are separated and all the positions where the diffusion layers are connected are considered as candidates, and the horizontal length of the wiring area due to the separation of the diffusion layers is calculated. The sum of the wire length that increases due to increase and feedthrough creation and the number of horizontal wires on each X coordinate that also increases due to this is minimized. Thereby, the increase in area of the wiring region can be minimized.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail using the drawings. FIG. 3 shows a layout model of a cell targeted in this embodiment. 1 is an outer frame of the cell, and 2 is a terminal (referred to as an external terminal) for connecting a signal line from outside the cell. Here, a cell is a functionally organized unit, and is the minimum unit of chip packaging design. Inside the cell, MOS transistors are arranged in two rows (these are called element rows), and wiring is provided between the gates, sources, drains, and external terminals of these MOS transistors. Here, 8 is a gate, 9 and 10 are diffusion layers, and each of them is a source or a drain. These 8, 9 and 10 form a MOS transistor. Here, when adjacent diffusion layers of adjacent MOS transistors have different potentials, the diffusion layers 10 and 14 are arranged separately.

When these are at the same potential, the diffusion layer 15 is shared and the MOS
Place transistors to reduce cell area. For wiring between MOS transistors, after the positions of the MOS transistors are determined, the first aluminum layer 12 and the polysilicon layer 11 are connected.
Gate 8, diffusion terminal 16 and external terminal 2 are formed using two layers of
Wire between.

Here, fixed wiring lines 17 and 18 are a ground line and a power line, respectively. In this embodiment, it is assumed that the intervals between these wirings are fixed. This is because when the cells are arranged adjacent to each other, the power supply line and the ground line can be wired in straight lines between the cells. There are five wiring areas. Wiring regions 4 and 6 on the element rows, wiring regions 5 sandwiched between two element rows, and wiring regions 3 and 7 above and below each element row, respectively.

The vertical lengths of wiring areas 4 and 6 are fixed, and those of wiring areas 3 and 7 are variable and determined when wiring is completed. In wiring regions 4 and 6, only the first aluminum wiring layer can be used. This is because if there is a polysilicon layer on the diffusion layer, there will always be M.
This is because an oS transistor is generated. Therefore, feedthroughs using polysilicon layers must pass through locations where there are no diffusion layers. One is the position 1 where the diffusion layer is separated in advance as shown in Figure 4.
3, there is no change in the area of the cell even if it passes through the feedthrough 19. The other case is when W20, which is connected to the diffusion layer, is newly separated and passed through the feedthrough 19, as shown in FIG. 5, and at this time, the lateral length of the cell increases by one grid.

Here, wiring 12 is required to connect the newly separated diffusion layers. In the embodiment described below, the feed-through passage positions are limited to the two cases shown in FIGS. 4 and 5, and the feed-through passage positions are determined so as to reduce the area of the cell.

FIGS. 9 and 10 show processing flowcharts of the conventional method and the present method. In the conventional method, after determining the relative wiring of MOS transistors 53, the number and position of the MOS transistors are estimated and feedthroughs are inserted between the MOS transistors before wiring processing.54 Next, in the wiring processing, nets are extracted and , the wiring order is determined, and the wiring route is determined for each 56,1 net. At that time, if there is a net that requires a feedthrough, the pre-inserted feedthrough is selected on a first-come, first-served basis to determine the wiring route.The processing above 57° and 58° is performed based on the wiring grid, but the subsequent 59. In this method, the placement and wiring results up to that point are converted into a mask pattern in the mask pattern generation process.In this method, feedthroughs are not inserted in the placement process, but are generated in the wiring process. After extracting the nets, allocate each net to a channel 60 and complete the first layer wiring in the channel on the column 61.Next, for the remaining nets, if feedthrough is required, connect all the nets instead of one by one. Simultaneously generate feedthrough 62, and then perform wiring in the inter-column channel and in the upper and lower channels 63
, 64° The positioning of the mask pattern generation process is the same as the conventional method. 65° FIG. 2 shows the wiring requirements. Here, 5 wiring requests, 22
, 23, 24, 25, and 26. Here, the wiring request refers to one terminal from one terminal to another. Therefore, there is a possibility that multiple wiring requests can be made for one net. First, the wiring request 24 that closes on the element row is wired in the upper channel of the lower row. The 27° wiring request 23 in FIG. 6 is assigned to the upper channel, and the remaining 28° wiring requests 22 and 26 in FIG. 6 cannot be routed without using feedthroughs. Feedthroughs are assigned to these wiring requests to complete the wiring. The wiring request 25 describes the 70° feed-through position determination method shown in FIG. 6, which allows wiring as is. The wiring requirements 22 and 26 in FIG. 2 are set as the feedthrough required positions at the vertices 29 and 30 in FIG. 7, respectively.
Expressed as

Examining the cells of this example, feedthrough candidate positions 35~
38 (Figure 6) is extracted. These are represented by vertices 31 to 34 in FIG. 7, respectively. Next, feed-through candidate positions from which a certain feed-through required position can be selected are represented by sides 39 to 43 of the graph in FIG. The possibility of selection here is
This means whether or not the wiring can be wired within the inter-column channel 4 without short-circuiting. FIG. 8 shows that when the feed-through required position 26 selects the feed-through candidate position 35 and generates a feed-through, a short circuit (49) occurs with the wiring path 6 in the inter-column channel 5. Therefore, there is no edge between vertices 3o and 31 of the graph in FIG. Next, an evaluation value is given to each side of FIG. According to the evaluation value calculation method of the present invention, these values are based on an increase in the lateral length of the cell due to feedthrough position selection (the lateral length increases by 1 pitch in Figure 5) and an increase in the wiring length (Figure 8). , 52
The sum of the length of the wiring and the wiring length of the part 53) and the increase in the degree of congestion (for example, the number of wiring in the horizontal part of layout 1fA50 and 51 in Fig. 1, 2 tracks) are calculated by the sum. be done. After that, select vertex 29 and any of vertices 31 to 32 from sides 39 to 43 of the graph shown in FIG. All you have to do is select one of them without duplication.

By solving this problem, one feedthrough candidate position 37.36, for example, is assigned to each feedthrough required position 22.26 in FIG. 6, and the wiring route 50. 52 is obtained. In cell wiring problems, the number of feed-through candidate positions (the number of vertices on the bottom side of FIG. 7) is always greater than the number of positions requiring feed-through (the number of vertices on the top side of FIG. 7).

〔Effect of the invention〕

As is clear from the above description, according to the present invention, in the wiring between MOS transistors in a cell in which the distance between the power supply line and the ground line is fixed, firstly, it is possible to prevent the wiring from becoming impossible due to insufficient feedthrough; By eliminating the need to take a large detour to select an unused feedthrough, and (2) generating the necessary and sufficient feedthroughs, it is possible to determine feedthroughs that are equivalent to or better than manual feedthroughs. The effect of the present invention on cell area reduction is approximately 25.32.2.
It was 3%.

The present invention described above has the effect of reducing chip area and reducing chip design and manufacturing costs. This leads to high-performance, complete automation of cell layout pattern generation, and further leads to a significant reduction in the number of man-hours required for designing the layout of LSI chips.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing one embodiment of the present invention, and shows the result of two wires being wired with feedthroughs generated. Fig. 2 shows the wiring requirements used in this example, Fig. 3 shows the layout model of 0MO8 logic cell, Figs. The wiring pattern immediately after the first layer wiring is completed is shown. 7th
The figure is a diagram representing the feed-through assignment problem using a graph. FIG. 8 shows an unfeasible feedthrough assignment. FIGS. 9 and 10 are flowcharts of a conventional method and a method of the present invention showing wiring processing taking feedthrough into consideration. DESCRIPTION OF SYMBOLS 1...Cell frame, 2...External terminal, 3...Upper channel, 4...Upper row upper channel, 5...Inter-column channel, 6...Lower row upper channel, 7... lower channel, 8
...Gate, 9.10...Diffusion layer, 11...Polysilicon layer, 12...Aluminum first layer, 13.20...
・Feedthrough candidate position, 14.15...diffusion layer,
16...Diffusion terminal, 17...Grounding wire, 18...Power line.

Claims (1)

[Claims] 1. A wiring method for wiring between the gate (hereinafter referred to as gate terminal), source, and drain (hereinafter referred to as diffusion terminals) of a field effect transistor, which On a plane in which a coordinate system is defined, transistors are arranged in opposing rows, one above the other, and a region sandwiched between these transistor rows (hereinafter referred to as an inter-row channel) and an area above the upper transistor row (hereinafter referred to as an inter-row channel). The regions above each of the upper and lower transistor rows (hereinafter referred to as upper or lower transistor rows, respectively) can be used for wiring using at least two wiring layers. The vertical length of the inter-column channel is fixed, so nets that could not be routed in the inter-column channel (gates that should be connected with the same wiring) can be used for wiring using one wiring layer. set of terminals and diffused terminals)
Vertical wiring (using one wiring layer) across the transistor column to route the
In wiring between gate terminals and diffusion terminals to minimize the wiring area used (hereinafter referred to as feed-through), a given set of nets should be routed in the upper channel of each column above and below, and When divided into a set of nets that should be routed in channels other than the above, create feedthroughs for nets other than those that should be routed in channels other than those on the top and bottom columns, and route them in the upper or lower channel. In this case, feedthroughs are created in the following two selectable positions (1) and (2) according to the criterion (3). (2) The diffusion layer is shared because the adjacent diffusion terminals of adjacent transistors are at the same potential. (3) Increase the horizontal length of the wiring area by separating the diffusion layer in (2) and create a feedthrough. A wiring method between transistors, characterized in that the sum of the wiring length that increases due to this, and the number of horizontal wiring on each x-coordinate that also increases due to this.