JPH0130327B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timing pulse generator in which the individual generation times and pulse widths of a plurality of pulse signals can be arbitrarily set.

This type of timing pulse generator is an important part used in control circuits that control various electronic devices. For example, it is used to generate various timing pulse signals necessary to drive each component of a storage module used in a magnetic bubble memory.

Traditionally, multiple timing signals with different phases and widths
Pulse signal generation was performed by multiple monostable multivibrators relying on RC discharge circuits. However, timing pulse generators using monostable multivibrators have the disadvantage that the phase and width of the pulse signal change due to changes in power supply voltage or temperature.

As a way to deal with this problem, Japanese Patent Application Laid-Open No. 2003-2012 Sho proposed a method of sequentially outputting the contents of read-only memory (hereinafter referred to as ROM) in synchronization with a clock signal of a constant cycle.
This is described in Japanese Patent Application Laid-open No. 51-142237 and Japanese Patent Application Laid-open No. 149933/1983. However, this method requires a large capacity ROM with a number of words corresponding to the number of clock signals included in the sequence of timing pulse signals to be generated. Furthermore, it has been difficult to generate a complex timing pulse signal in which pulse signals having different phase widths are repeated one after another an arbitrary number of times.

SUMMARY OF THE INVENTION An object of the present invention is to provide a timing pulse generator that easily overcomes the above-mentioned conventional drawbacks.

In the present invention, first storage means stores the states of a plurality of pulse signals and the durations of the states in a corresponding manner;
The timing pulse signal is generated based on the contents of the second storage means that stores information for selecting the number of repetitions of the pulse pattern and the type of pulse pattern in correspondence with each other.

That is, the present invention provides a first OR gate that receives a start signal and a first carry signal, and an output signal of the first OR gate, the contents of which are set in synchronization with a clock signal, and the set value is set. a first counting means that starts counting the clock signal from and generates the first carry signal when the content reaches a specific value; and the start signal sets the content to an initial value in synchronization with the clock signal. is,
It has a second counting means for counting the number of first carry signals, a first storage section and a second storage section, the contents of the second counting means are used as a lower address input, and the read output from the first storage section is used as the first storage section. a first storage means for supplying a content setting input of a first counting means, the read output from the second storage forming a plurality of timing pulse signals; and inputs the start signal and the third carry signal. The content is set in synchronization with the second carry signal from the second counting means by the output signal of the second OR gate and the second OR gate, and the count of the second carry signal is calculated from the set value. a third counting means for generating the third carry signal when the content reaches a specific value; and a fourth counting means for counting the number of the third carry signals when the content is set to an initial value by the start signal. means, a third storage section and a fourth storage section, the content of the fourth counting means is taken as an address input, and the read output from the third storage section is supplied to the content setting input of the third counting means; a second memory whose read output from the fourth memory specifies an upper address of the first memory means;
and storage means. Note that the lower address and upper address used here mean a part of the address of the first storage means and the remainder.

The present invention will be explained in more detail below using the drawings.

FIG. 1 is an embodiment of a timing pulse generator according to the present invention. This timing pulse generator basically consists of a first pulse generator 100 and a twenty-second pulse generator 150, which are surrounded by the dashed line in FIG. The first pulse generator 100 generates a repetitive timing pulse signal 112, and the second pulse generator 150 in turn controls the selection and number of repetitions of the pulse pattern generated by the first pulse generator 100.

The data stored in the first ROM 114 as a first storage means in the first pulse generator 100 is
It is divided into a duration section 109 corresponding to the storage section and a state section 111 corresponding to the second storage section. Status section 11
1 stores the state of the pulse signal as a logical value, and the duration field 109 stores the duration of the same state of the pulse signal as the number of clock signals corresponding to the same address as the state field 111.

The first counter 102 counts the clock signal 101 up to the value specified by the contents of the duration section 109, and keeps the timing pulse signal 112 outputted from the state section 111 via the output register 113 at the same rate until the counting is completed. Let the state continue. The first carry signal 1 of the first counter 102 is output when the clock signal 101 is counted up to the specified value.
03 increments the contents of the second counter 105. As a result, the lower address of the first ROM 114 is moved to the next one, and the timing pulse signal 11
The next state of 2 is output. Repeat this and the second
A pulse sequence of the timing pulse signal 112 is formed at the time the second carry signal 151 of the counter 105 is generated. By repeating the above operations, the timing pulse signal 112 can be generated continuously. If the sequence of multiple timing pulse signals generated simultaneously from the register 113 is expressed as a pulse pattern, then
1ROM 114 stores data regarding a plurality of pulse patterns.

The data stored in the second ROM 164 as a second storage means in the second pulse generator 150 is
It consists of a repetition number section 159 corresponding to a storage section and a pattern selection section 161 corresponding to a fourth storage section. The pattern selection section 161 includes a first pulse generator 100.
Data for selecting the type of pulse pattern generated by the first pulse generator 100 is stored in the repetition number section 159, and the number of repetitions of each pulse pattern generated by the first pulse generator 100 corresponds to the same address as the pattern selection section 161. is stored. The third counter 152 counts the second carry signal 151 from the second counter 105 up to the value specified by the contents of the repetition number section 159, and transmits the read output 160 of the pattern selection section 161 to the output register 163 until the counting is completed. Output via. The output 162 of this output register 163 specifies the upper address of the first ROM 114 and selects the type of timing pulse signal generated from the first pulse generator 100. The third carry signal 153 from the third counter 152, which is output when the second carry signal 151 is counted up to the specified value, is sent to the fourth counter 15.
Increment the contents of 5. This allows the
2The address of ROM 164 moves to the next address. Further, the contents of the next address of the repetition number section 159 and the pattern selection section 161 are supplied to the third counter 152 and the output register 163, respectively. Output register 1
The second pulse generator 15 outputs via 63
The zero output 162 specifies the upper address of the first ROM 114 within the first pulse generator 100 .

By specifying the upper address of the first ROM 114, the pulse pattern generated by the first pulse generator 100 is selected. On the contrary,
The repetition number section 159 indicates the period during which the upper address of the first ROM 114 is kept constant.

That is, at each end of the pulse sequence produced by the first pulse generator, the second counter 10
The second carry signal 151 output from the third
It is input to counter 152 as a clock. Third
The counter 152 counts this second carry signal 151 up to a value specified by the contents of the repetition number section 159. The upper address of the first ROM 114 selected from the pattern selection section 161 via the output register 163 is kept constant until counting is completed.
When the second carry signal 151 output from the second counter 105 has been counted up to the specified value,
The third carry signal 153 output from the third counter 152 is input to the fourth counter 155, and its contents are incremented. This allows the
2 The address of the ROM 164 is moved, and the type of pulse pattern to be generated next (change of the upper address) and the number of repetitions of that pulse pattern are determined. Note that the OR gates 106 and 156 are used to initialize the first counter 102 and the third counter 152 using the start signal 104.

As mentioned above, Figure 1 has a simple structure consisting of only four counters, two ROMs, two output registers, and two OR gates, but the pulse pattern formed by this has a simple structure. The degree of freedom is expanding without limit. This will be explained below.

Generally, the configuration of the first ROM 114 and the second ROM 164, and the configuration of the first counter 102 and the second counter 10
5. Third counter 152, fourth counter 155
Then, the number of bits in the output registers 113 and 163 depends on the number of bits of the timing pulse signal to be generated (number of output terminals), the pulse width, the number of repetitions of the pulse pattern, the number of state changes in each pattern, and the number of pulses. Although it is determined depending on the type of pattern, here, as an example, the first ROM 114 (the second ROM 1
61) is 256 words/8 bits as shown in FIG.
(pattern selection section 161), and the remaining 4 bits are used for the duration section 111 (repetition number section 159). At this time, the first counter 102, second counter 105, third counter 152, fourth counter 155, and output registers 113 and 163 each have 4 bits. In other words, 16 pulse patterns with a resolution of 2 ⁴ = 16 clocks can appear from each of the four output terminals, the maximum number of repetitions for each pattern is 16, and the transitions between the 16 types of pulse patterns are 256 times. I'll forgive you. This is a traditional single
This corresponds to a system using ROM with a storage capacity of 256K bits, but if used in Figure 1, only two 2K bit ROMs would be needed. Next, we will explain how each ROM works, focusing on the operation of the first pulse generator section.

FIG. 3 shows signal waveforms of each part of the first pulse generator 100 when the contents 211, 209 of the first ROM 114 shown in FIG. 2 are used. signal 3
04 indicates a start signal, signal 301 indicates a clock signal, signal 303 indicates the first carry signal of the first counter 102, signal 332 indicates the contents of the first counter 102 in hexadecimal code, and signal 33 indicates the content of the first counter 102 in hexadecimal code.
7 indicates the contents of the second counter 105 in hexadecimal code. Four signals 312 are output register 11
3 output is shown. Note that the high level of the timing pulse signal 112 corresponds to "1" in the state section 111 of the first ROM 114, and the low level corresponds to "0".

Next, the operation of the first pulse generator will be explained in detail using FIGS. 1, 2, and 3.

First, when the start signal 304 becomes low level,
The contents of the second counter 105 are initialized to zero, and at the same time, the contents of the first counter 102 are set to the first ROM1.
The contents of the 0th word of the duration field 109 of 14 (FIG. 2), ie, hexadecimal number D' (1101), are set (hereinafter, hexadecimal representations will be distinguished by '). Next, when the clock signal 301 is input, the contents of the 0th word of the state section 111 of the first ROM 114, ie, 0', are set in the output register 113, while the contents of the first counter 102 are incremented by 1, and E '. Continue clock signal 301
is input and the first carry signal 303 is generated from the first counter 102 at the time when the content of the first counter 102 reaches F'. First carry signal 303
Due to the occurrence of , the contents of the second counter 105 are incremented by 1 at the falling edge of the clock signal 301 at that time. This means that the address of the first ROM 114 is 0.
This corresponds to moving from one word to another. As a result, when the clock signal 301 falls after the first carry signal 303 is generated, the first counter 102
The content E' of the first word of the duration field 109 of the first ROM 114 is set. Furthermore, the contents of the first word of the state section 111 are newly set in the output register 113.

By repeating the above operations, the output register 113 sequentially outputs the contents of the state section 111 of the first ROM 114 every time the first carry signal 103 is generated, and as shown in FIG.
A sequence of independent timing pulse signals 312 is generated. After the content of the second counter 105 reaches F', the initial operation is resumed and the sequence of timing pulse signals 312 is repeated.

In this way, by storing the duration of the state of the timing pulse signal as the number of periods of the clock signal in each address of the first ROM 114, and storing the state of the timing pulse signal as a logical value, the desired timing pulse signal can be generated. It can occur.

The operating waveform of the first pulse generator 100 shown in FIG. 3 shows one pulse pattern when the upper address of the first ROM 114 is constant.
More pulse patterns are stored in the first ROM 114, and the second pulse generator 15
0 output 162 selects these pulse patterns.

The second pulse generator 150 has a similar configuration to the first pulse generator 100 and operates similarly. The difference between the two is that the first pulse generator 100
has the clock signal 101 as its input, whereas the second pulse generator 150 has as its input the second carry signal 151 generated by the second counter 105 in the first pulse generator 100.

Here, the operation of the second pulse generator 150 will be explained in detail again using FIGS. 2 and 3. FIG. 2 shows the contents of the second ROM 164, and the signal 304 in FIG. 3 is the start signal 104 and the signal 3.
01 is the second carry signal 151 supplied from the second counter 105, and signal 303 is the third carry signal 151 supplied from the second counter 105.
The third carry signal 153 generated from 52, the signal 332 is the content of the third counter 152, and the signal 337
Assume that the contents of the fourth counter 155 are respectively shown.
The contents 332 of the third counter 152 and the contents 337 of the fourth counter 155 have 4 bits as one character.
Shown in hexadecimal code. Signal 312 also represents the output 162 of second pulse generator 150 .

First, when the start signal 304 becomes low level,
The contents of the fourth counter 155 are initialized to zero, and at the same time, the contents of the third counter 152 are set to the second ROM1.
The contents of the 0th word (FIG. 2) of the repetition number section 159 of 64, ie, hexadecimal number D' (1101), are set.

The contents of the output register 163 are set by the second carry signal 151 generated from the second counter 105. The contents of the output register 163 are undefined from the time the power is turned on until the second carry signal 151 is generated. Therefore, after the power is turned on, the upper address of the first ROM 114 is not determined from when the start signal 304 becomes low level until the second carry signal 151 is generated, and the timing pulse signal 11
2 becomes temporarily indeterminate. However, clock signal 1
Assuming that the period of 01 is 50 ns and the length of the first counter 102 and second counter 105 is 4 bits, the period during which the timing pulse signal 112 is unstable is a maximum of 12.8 μs after the power is turned on. It's not a problem.

When the second carry signal 151 is input, the contents of the 0th word of the pattern selection section 161 of the second ROM 164, ie, 0', are set in the output register 163. On the other hand, the content of the third counter 152 increases by 1 and becomes E'. Subsequently, the second carry signal 151 is input, and when the content of the third counter 152 reaches F', the third carry signal 151 is inputted from the third counter 152.
A carry signal 303 is generated. Due to the generation of the third carry signal 303, the contents of the fourth counter 155 are incremented by 1 at the falling edge of the second carry signal 301 at that time. This corresponds to moving the address of the second ROM 164 from word 0 to word 1. As a result, when the second carry signal 301 falls after the generation of the third carry signal 303, the third counter 152 stores the contents E' of the first word of the repetition number section 159 (209 in FIG. 2) of the second ROM 164. is set. Furthermore, output register 1
63 is a pattern selection section 161 (21 in FIG.
The contents of the first word in 1) are newly set.

By repeating the above operations, the output register 163 outputs the pattern selector 1 of the second ROM 164 every time the third carry signal 303 is generated.
61 (211 in FIG. 2) are sequentially output, and a 4-bit pattern selection signal 312 is generated as shown in FIG. After the content of the fourth counter 155 reaches F', the process returns to the initial operation and continues to generate the pattern selection signal 312 repeatedly.

In this way, the second pulse generator 150
Similarly to the pulse generator 100, the second ROM 164
By determining the contents of , a desired pattern selection signal 312 can be generated. This pattern selection signal 312 is the first signal in the first pulse generator 100.
1 Specify the upper address of ROM114. This upper address selects one of a plurality of pulse patterns stored in the first ROM 114. That is, the second pulse generator 150 dynamically selects the type of timing pulse 112 output from the first pulse generator 100.

FIG. 4 is an example of a timing pulse signal generated by a timing pulse generator according to the present invention. In this example, the first pulse generator 100
In the first ROM 114, information on the state of the pulse signal and its duration as shown in FIG. 2 is stored for each of the pulse patterns P ₁ to Pm. Second ROM1 in second pulse generator 150
The repetition number section 159 of 64 contains the pulse pattern.
The number of repetitions of each of P ₁ to Pm is stored, and the pattern selection section 161 stores pulse pattern selection information. That is, the first pulse generator 100 repeats the pulse pattern specified by the second pulse generator 150 by the number of repetitions section 159.
Occurs repeatedly as many times as indicated by the content of.

The state of a normal timing pulse signal does not constantly change, but includes many sections in which the same state continues for a certain period of time, as shown in FIG. In the timing pulse generator described in JP-A-51-142237 cited above, the state of the timing pulse signal is expressed by one bit of the ROM for one period of the clock signal, so It required a large amount of ROM. however,
Since the timing pulse generator according to the present invention stores the state pattern of the timing pulse signal and its duration separately in the first and second ROMs, the ROM is not accessed until a change in the state pattern occurs. You can get away with it. Therefore, the timing pulse generator according to the present invention can significantly reduce the ROM capacity compared to the conventional timing pulse generator.

In _addition , complex timing pulses such as pulse patterns Pi, _{P 2} . can occur.

As described above, according to the present invention, the deficiencies of conventional timing pulse generators can be easily solved. In particular, the present invention is highly effective as a controller for magnetic bubble memories.
In this case, when considering LSI, the savings in ROM capacity directly makes it possible to reduce the chip size, which improves yield and reliability, resulting in a significant reduction in price.

In the above explanation, a normal up counter is used as a counter, but a down counter can also be used. In addition, in the explanation of the above embodiments, ROM was used as a storage means, but it is also possible to use rewritable memory (hereinafter referred to as ROM) or RAM.
It is also possible to use a combination of ROMs.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing an embodiment of the present invention, FIG. 2 is a pattern diagram showing an example of the contents of a ROM, and FIG. 3 is a diagram showing various signals of the first pulse generator 100 shown in FIG. 1. FIG. 4 is a diagram illustrating a pattern illustrating an example of a timing pulse generated by the present invention. 102...First counter, 105...Second counter, 106, 156...OR gate, 114...
...First ROM, 109... Duration section, 111...
...Status section, 113, 163...Output register, 1
52...Third counter, 155...Fourth counter, 164...Second ROM, 159...Repetition number section, 161...Pattern selection section, 209...No.
During the duration of 1ROM or the number of repetitions part of the second ROM, 211...The state part of the first ROM or the number of repetitions part of the second ROM.
2ROM pattern selection section, 101 and 301...
Clock signal, 103 and 303...carry signal of first counter, 104 and 304...start signal, 112 and 312...timing pulse signal, 332...content of first counter, 337...
Contents of the second counter.

Claims (1)

[Claims] 1. A first OR gate receives the start signal and the first carry signal as inputs, and the output signal of this first OR gate sets the contents in synchronization with the clock signal, and the clock signal is changed from the set value. a first counting means that starts counting and generates the first carry signal when the content reaches a specific value; It has a second counting means for counting the number of carry signals, a first storage section and a second storage section, the contents of the second counting means are used as a lower address input, and the read output from the first storage section is used as the first counting means. a first storage means for supplying a content setting input of the means, the read output from the second storage forming a plurality of timing pulse signals; and a second logical sum having as inputs the start signal and the third carry signal. The content is set in synchronization with the second carry signal from the second counting means by the output signal of the gate and the second OR gate, and the count of the second carry signal is started from the set value, and the content is set in synchronization with the second carry signal from the second counting means. a third counting means for generating the third carry signal when the number of carries reaches a specific value; a fourth counting means for counting the number of third carry signals whose content is set to an initial value by the start signal; 3 storage section and a fourth storage section, the contents of the fourth counting means are used as address input, and the read output from the third storage section is used as the third storage section.
a second memory means for supplying a content setting input of a counting means, the read output from said fourth memory specifying an upper address of said first memory means.