JPH01303056A - Dc/dc converter - Google Patents

Dc/dc converter

Info

Publication number
JPH01303056A
JPH01303056A JP13192088A JP13192088A JPH01303056A JP H01303056 A JPH01303056 A JP H01303056A JP 13192088 A JP13192088 A JP 13192088A JP 13192088 A JP13192088 A JP 13192088A JP H01303056 A JPH01303056 A JP H01303056A
Authority
JP
Japan
Prior art keywords
transformer
voltage
winding
secondary winding
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13192088A
Other languages
Japanese (ja)
Inventor
Tomiyasu Sagane
富保 砂金
Tamio Shimizu
民夫 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13192088A priority Critical patent/JPH01303056A/en
Publication of JPH01303056A publication Critical patent/JPH01303056A/en
Pending legal-status Critical Current

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  • Dc-Dc Converters (AREA)

Abstract

PURPOSE:To prevent the breakdown of parts and the like, by adding a circuit for suppressing a surge voltage generated in a circuit, when the transistor of the circuit is turned OFF. CONSTITUTION:A DC/DC converter is composed of a transformer 10, a transistor(Tr) 20, and a control circuit 30 to supply a load 40 with power. Then, the secondary winding n2 of a saturable magnetic core SR is connected through a resistance R1 and a diode D2 with a tertiary winding N3 provided in said transformer 10 so that a voltage-surge suppressor circuit 50 is added to the converter. Thus, because electric current flows through the secondary winding N2 of the transformer 10 and the primary winding n1 of SR and a voltage generated in the tertiary winding N3 of the transformer 10 is hindered by the diode D2 when the Tr20 is turned OFF, electric current does not flow through the voltage-surge suppressor circuit 50. Then, because electric current If flows through the secondary winding n2 of SR by the voltage generated in the tertiary winding N3 of the transformer 10 and the SR is saturated and the Tr20 is turned OFF in the state when the Tr20 is switched from OFF to ON, no surge voltage is not generated in the converter.

Description

【発明の詳細な説明】 〔概 要〕 通信装置等に使用されるD C/D Cコンハークに関
し、 上記回路のトランジスタ(以下Trと称する)のオフ時
に発生ずるサージ電圧を抑える回路を付加したD C/
D Cコンバータを提供することを目的とし、 1次巻線N1の一端、及びスイッチ手段を介して1次巻
線の他端が直流電源に接続され、1次S綿の電圧を変圧
して2次巻線N2に出力する1〜ランスと、トランスの
1次巻線の一端と直流電源の間に挿入され、制御信号に
よりオン/オフ動作を行うスイッチ手段と、トランスの
2次巻線の一端に接続され、ナーシ電圧の発生を阻止す
る可飽和磁心(以下SRと称する)と、St?の他端に
接続され、人力信号を整流して平滑化する直流平滑化手
段と、直流平滑化手段とトランスの2次巻線の他端に接
続した負荷の電圧状態により、スイッチ手段を所定のB
i’1間オン/オフ制御する制御信号を出力する制御手
段とを有するDC/DCコンバータにおいて、トランス
にイづ加される3次巻線N、と、SRに付加される2次
巻線n2の一端が接続され、3次巻線N、と2次巻線n
2の他端の間をダイオ−1” D 2と所定の抵抗値を
有する抵抗器R,とて直列接続して形成されるサージ電
圧抑制回路を付加して構成する。
[Detailed Description of the Invention] [Summary] Regarding the DC/DC converter used in communication devices, etc., the DC/DC converter is equipped with a circuit that suppresses the surge voltage generated when the transistor (hereinafter referred to as Tr) in the above circuit is turned off. C/
In order to provide a DC converter, one end of the primary winding N1 and the other end of the primary winding are connected to a DC power source through a switch means, and the voltage of the primary S cotton is transformed to 2 A lance that outputs to the next winding N2, a switch means that is inserted between one end of the primary winding of the transformer and the DC power supply and performs on/off operation according to a control signal, and one end of the secondary winding of the transformer. A saturable magnetic core (hereinafter referred to as SR) connected to St? A DC smoothing means connected to the other end rectifies and smoothes the human input signal, and a voltage state of a load connected to the DC smoothing means and the other end of the secondary winding of the transformer is used to control the switching means at a predetermined level. B
In a DC/DC converter having a control means for outputting a control signal for on/off control during i'1, a tertiary winding N added to the transformer and a secondary winding n2 added to the SR. one end of which is connected, the tertiary winding N, and the secondary winding n
A surge voltage suppression circuit formed by connecting a diode 1"D2 and a resistor R having a predetermined resistance value in series is added between the other ends of the surge voltage suppressing circuit.

〔産業上の利用分野〕[Industrial application field]

本発明は、jm信装置等に使用されるD C/D Cコ
ンハークの改良に関するものである。
TECHNICAL FIELD The present invention relates to an improvement of a DC/DC conharc used in a JM communication device or the like.

この際、」二記回路のTrのオフ時に発生するサージ電
圧を抑える回路を付加したD C/D Cコンバータが
要望されている。
At this time, there is a demand for a DC/DC converter that is equipped with a circuit that suppresses the surge voltage that occurs when the Tr in the circuit 2 is turned off.

〔従来の技術〕[Conventional technology]

第4図は従来例のD C/D Cコンバータの回路図で
ある。
FIG. 4 is a circuit diagram of a conventional DC/DC converter.

第4図において、負荷4の両端の電圧をEoどすると、
負荷4に並列に接続した抵抗の中点fの電圧ばEo/2
となる。この電圧を制御回路3内の公知の演算増幅器(
以下オペアンプと称する)3−2の人力の一方に加えろ
。他方の人力には今の場合、1”l荷に出力したい電圧
値の172に設定した基r1(電圧Vrc!fを加え、
EO/2と基準電圧’Jrefとの差の電圧を求める。
In Fig. 4, if the voltage across the load 4 is Eo, then
The voltage at the midpoint f of the resistor connected in parallel to load 4 is Eo/2
becomes. This voltage is applied to a known operational amplifier (
(Hereinafter referred to as operational amplifier) Add it to one side of 3-2. In this case, to the other human power, add base r1 (voltage Vrc!f) set to 172, which is the voltage value you want to output to 1"l load,
Find the voltage difference between EO/2 and the reference voltage 'Jref.

これを電圧/周波数変換回路(以下V/[と称する)3
〜1に力11え、差の電圧に対応した操り返し周波数の
パルス(パルス幅は一定)を出力する。この出力をTr
  2に加えることにより、′Pr 2のスイッチング
周期を変化さゼることて負荷電圧を一定に制御する。
This is a voltage/frequency conversion circuit (hereinafter referred to as V/[) 3
-1 and outputs a pulse (pulse width is constant) with a frequency corresponding to the difference in voltage. Tr this output
2, the switching period of 'Pr 2 is changed and the load voltage is controlled to be constant.

今、Tr 2がオンの時、トランス1の1次側の巻線N
1に電流が流れるが、トランス1の2次側の巻線N2が
1次側の巻線と逆方向のためダイオ−In、により阻止
されて、2次側の巻線には電流が流れない。
Now, when Tr 2 is on, the primary winding N of transformer 1
Current flows through transformer 1, but since the secondary winding N2 of transformer 1 is in the opposite direction to the primary winding, it is blocked by diode In, and no current flows through the secondary winding. .

次にTr2がオフの時、上述のTr 2がオン時に2次
側巻線に蓄えられたエネルギーが放出され、2次側巻線
C1ニダイオードD1の順方向に電流が流れる。
Next, when Tr2 is off, the energy stored in the secondary winding when Tr2 is on is released, and a current flows in the forward direction of the secondary winding C1 diode D1.

次に、Tr 2がオンになった時、ダイオードD+に流
れる電流は瞬間には0にならず、D、内の蓄積電荷によ
り逆方向に第4図に点線で示す電流Isがパルス状に流
れる。この時回路内の布線等によるインダクタンスLs
(図示しない)によってダイオF’ D Iの両◇:;
;に過大な→ノージ電圧が発生ずる。このサージ電圧は
、ダイオードD1の破壊又は出力端に大きなノイズの発
生を招く。
Next, when Tr 2 is turned on, the current flowing through diode D+ does not instantaneously become 0, but due to the accumulated charge in D, a current Is flows in the opposite direction in a pulsed manner as shown by the dotted line in Figure 4. . At this time, inductance Ls due to wiring in the circuit, etc.
(not shown) both of the diode F' DI ◇:;
Excessive →noge voltage is generated. This surge voltage causes destruction of the diode D1 or generation of large noise at the output terminal.

この1ナージ電圧の発生を抑える方法として、す′−ジ
電圧発生の原因である逆方向電流Isを阻止するためダ
イオード1]1に直列に、第4図に示すSRを挿入する
ことが行われている。即ち、SRの高インダクタンスに
より逆方向電流Isを阻止する。
As a method of suppressing the generation of this 1-nerge voltage, an SR shown in Fig. 4 is inserted in series with the diode 1]1 to block the reverse current Is that is the cause of the 1-nerge voltage. ing. That is, the high inductance of SR blocks the reverse current Is.

このようにしてTrオン時にダイオードの両端に発生す
るサージ電圧を阻止していた。
In this way, the surge voltage generated across the diode when the Tr is turned on is prevented.

〔発明が解決しよう点する課題〕[Problem to be solved by the invention]

しかしながら」−述の回路においては、Sl’lの高・
インダクタンスのためTrがオフになった時流れる順方
向の電流も阻止され、SRの両◇:!1の電圧が人きく
なりトランスの2次側の巻線N2に発生ずる電圧も大き
くなる。したかってトランプの巻数比で決まる1次側の
巻線N1に発生ずる電圧も大きくなって、Tr2&こ過
大なサージ電圧が印加されTr 2の破壊を招くという
問題点があった。
However, in the circuit described above,
Due to the inductance, the forward current flowing when the Tr is turned off is also blocked, and both of the SR ◇:! 1 voltage increases, and the voltage generated in the secondary winding N2 of the transformer also increases. Therefore, the voltage generated in the primary winding N1, which is determined by the turn ratio of the tramp, also increases, causing the problem that an excessive surge voltage is applied to Tr2, resulting in destruction of Tr2.

したがって本発明の目的は、−に記回路のTrのオフ時
にTrに発生ずるサージ電圧を抑える回路を付加したD
 C/D Cコンバータを掃供することにある。
Therefore, an object of the present invention is to provide a D
The purpose is to clean the C/DC converter.

〔課題を解決するための手段〕[Means to solve the problem]

」二記問題点は第1図に示す回路構成によって解決され
る。
The second problem can be solved by the circuit configuration shown in FIG.

即ち第1図において、1次巻線11+の一端、及びスイ
ッチ手段200を介して1次巻線の他θ:!;が直流電
源に接続され、1次巻線の電圧を変圧して2次8線N2
に出力する1−ランス100 と、トランスの1次巻線
の一端と直流電源の間に挿入され、制御信号によりオン
/オフ動作を行うスイッチ手段200と、トランスの2
次巻線の一端に接続され、リーージ電圧の発生を阻什す
る可飽和磁心Sitと、可飽和磁心の他端に接続され、
入力信号を整流して平滑化する直流平滑化手段600と
、直流平滑化手段とトランスの2次S線の他端に接続し
た負荷の電圧状態により、スイッチ手段を所定の時間オ
ン/オフ制御する制御信号を出力する制御手段300と
を有するDC/Dcコンハークにおいて、500はトラ
ンスに(’J加される3次巻線N、と、可飽和磁心に付
加される2次巻線n2の一端が接続され、3次巻線N3
と2次巻線r12の他端の間をダイオード”D2と所定
の抵抗値を有する抵抗器R1とで直列接続して形成され
るサージ電圧抑制回路である。
That is, in FIG. 1, one end of the primary winding 11+ and the other end of the primary winding θ:! through the switch means 200. ; is connected to the DC power supply, transforms the voltage of the primary winding, and connects the secondary 8 wire N2
1-lance 100 that outputs to
A saturable magnetic core Sit is connected to one end of the next winding and prevents the generation of leege voltage, and a saturable magnetic core Sit is connected to the other end of the saturable magnetic core,
A DC smoothing means 600 rectifies and smoothes an input signal, and a switching means is controlled to be turned on and off for a predetermined time depending on the voltage state of a load connected to the DC smoothing means and the other end of the secondary S line of the transformer. In the DC/DC converter circuit 500, a tertiary winding N, which is added to the transformer, and one end of the secondary winding n2, which is added to the saturable magnetic core, are connected to the transformer. connected, tertiary winding N3
This surge voltage suppression circuit is formed by connecting in series a diode "D2" and a resistor R1 having a predetermined resistance value between the other end of the secondary winding r12 and the other end of the secondary winding r12.

〔作 用〕[For production]

第1図において、スイッチ手段200がオフからオンに
スイッチングした時、トランス100の3次巻線NJに
発生ずる電圧によってダイオードD2、抵抗器R1を通
して可飽和磁心SRの2次巻線n2に電流が流れ、可飽
和磁心SRは飽和状態となる。
In FIG. 1, when the switch means 200 is switched from OFF to ON, a voltage generated in the tertiary winding NJ of the transformer 100 causes a current to flow through the diode D2 and the resistor R1 to the secondary winding n2 of the saturable magnetic core SR. As a result, the saturable magnetic core SR becomes saturated.

この結果、可飽和磁心SRが飽和状態即し低インダクタ
ンスの状態でスイッチ手段200がオフするため、トラ
ンス]00の1次巻線N1にはり゛−ジ電圧が発生しな
くなる。
As a result, the switch means 200 is turned off when the saturable magnetic core SR is in a saturated state, i.e., in a low inductance state, so that no excessive voltage is generated in the primary winding N1 of the transformer ]00.

〔実施例〕〔Example〕

第2同は本発明の実施例のサージ電圧抑制回路を付加し
たD C/D Cコンバータの回路図である。
The second figure is a circuit diagram of a DC/DC converter to which a surge voltage suppression circuit is added according to an embodiment of the present invention.

第3図は実施例の動作を説明する図である。FIG. 3 is a diagram illustrating the operation of the embodiment.

全図を通して同一符号は同一対象物を示す。The same reference numerals indicate the same objects throughout the figures.

第2図においてトランス10に設+3られた3次巻線N
Jは、抵抗R1とダイ;t−FD2を1ffi シテ5
II(02次巻線n2に接続されている。
In Fig. 2, the tertiary winding N installed in the transformer 10
J is resistor R1 and die; t-FD2 is 1ffi
II (connected to secondary winding n2).

T r20のオフ時は、トランス10の2次8線N2及
びSRの1次巻線nlを通して電流が流れる。又、トラ
ンス10の3次巻線N3に発生する電圧はダイオードl
′12によって阻止されるので、サージ電圧抑制回路5
0に電流は流れない。
When Tr20 is off, current flows through the secondary 8 wire N2 of the transformer 10 and the primary winding nl of the SR. Also, the voltage generated in the tertiary winding N3 of the transformer 10 is connected to the diode l.
'12, the surge voltage suppression circuit 5
No current flows at 0.

次に、Tr20がオフからオンにスイッチングした時、
第3図に示すようにトランス10の3次巻線N3に発生
ずる電圧によって、抵抗R1、ダイオ−1−”D2を通
してSllの2次S線n2に電流I[が流れる。この時
、SRは電流■rによって飽和状態となる。
Next, when Tr20 switches from off to on,
As shown in FIG. 3, due to the voltage generated in the tertiary winding N3 of the transformer 10, a current I flows through the resistor R1 and the diode 1-"D2 to the secondary S line n2 of the Sll. At this time, SR is The current ■r brings it into a saturated state.

この結果、St?が飽和状fル(即ち低インダクタンス
値)でTr20がオフするため、す°−ジ電圧の発生を
防くことができる。
As a result, St? Since the Tr 20 is turned off when the inductance is saturated (that is, the inductance value is low), it is possible to prevent the generation of a sudden voltage.

〔発明の効果〕〔Effect of the invention〕

以上説明のように本発明によれば、Trのオフ時に発生
するサージ電圧を抑えることができ、サージ電圧の発生
による部品破壊又は出力ノイズによるfl、荷への影響
をなくすることがてきる。
As described above, according to the present invention, it is possible to suppress the surge voltage that occurs when the transistor is turned off, and it is possible to eliminate the damage to parts due to the generation of the surge voltage or the influence on the fl and load due to output noise.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の原理圓、 第2図は本発明の実施例のサージ電圧抑制回路を付加し
たD C/D Cコンバータの回路図、 第3図は実施例の動作を説明する図、 第4図は従来例のD C/D Cコンバータの回路図で
ある。 図において 100はトランス、 200はスイッチ手段、 300は制御手段、 500はナージ電圧抑制回路、 600は直流平滑化手段 を示ず。
Fig. 1 shows the principle of the present invention, Fig. 2 is a circuit diagram of a DC/DC converter added with a surge voltage suppression circuit according to an embodiment of the present invention, and Fig. 3 is a diagram explaining the operation of the embodiment. FIG. 4 is a circuit diagram of a conventional DC/DC converter. In the figure, 100 is a transformer, 200 is a switch means, 300 is a control means, 500 is a nudge voltage suppression circuit, and 600 is a DC smoothing means.

Claims (1)

【特許請求の範囲】[Claims] 1次巻線(N_1)の一端、及びスイッチ手段(200
)を介して1次巻線の他端が直流電源に接続され、該1
次巻線の電圧を変圧して2次巻線(N_2)に出力する
トランス(100)と、該トランスの1次巻線の一端と
直流電源の間に挿入され、制御信号によりオン/オフ動
作を行うスイッチ手段(200)と、該トランスの2次
巻線の一端に接続され、サージ電圧の発生を阻止する可
飽和磁心(SR)と、該可飽和磁心の他端に接続され、
入力信号を整流して平滑化する直流平滑化手段(600
)と、該直流平滑化手段と該トランスの2次巻線の他端
に接続した負荷の電圧状態により、該スイッチ手段を所
定の時間オン/オフ制御する制御信号を出力する制御手
段(300)とを有するDC/DCコンバータにおいて
、該トランスに付加される3次巻線(N_3)と、該可
飽和磁心に付加される2次巻線(n_2)の一端が接続
され、該3次巻線(N_3)と該2次巻線(n_2)の
他端の間をダイオード(D_2)と所定の抵抗値を有す
る抵抗器(R_1)とで直列接続して形成されるサージ
電圧抑制回路(500)を付加したことを特徴とするD
C/DCコンバータ。
One end of the primary winding (N_1) and the switch means (200
), the other end of the primary winding is connected to a DC power supply, and the
A transformer (100) transforms the voltage of the secondary winding and outputs it to the secondary winding (N_2), and is inserted between one end of the primary winding of the transformer and the DC power supply, and is turned on/off by a control signal. a saturable magnetic core (SR) connected to one end of the secondary winding of the transformer to prevent the generation of surge voltage; a switch means (200) connected to the other end of the saturable magnetic core;
DC smoothing means (600
), and control means (300) for outputting a control signal for controlling on/off of the switching means for a predetermined time depending on the voltage state of the load connected to the DC smoothing means and the other end of the secondary winding of the transformer. In the DC/DC converter, one end of a tertiary winding (N_3) added to the transformer and a secondary winding (n_2) added to the saturable magnetic core are connected, and the tertiary winding A surge voltage suppression circuit (500) formed by connecting a diode (D_2) and a resistor (R_1) having a predetermined resistance value in series between the other end of the secondary winding (N_3) and the secondary winding (n_2). D characterized by adding
C/DC converter.
JP13192088A 1988-05-30 1988-05-30 Dc/dc converter Pending JPH01303056A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13192088A JPH01303056A (en) 1988-05-30 1988-05-30 Dc/dc converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13192088A JPH01303056A (en) 1988-05-30 1988-05-30 Dc/dc converter

Publications (1)

Publication Number Publication Date
JPH01303056A true JPH01303056A (en) 1989-12-06

Family

ID=15069286

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13192088A Pending JPH01303056A (en) 1988-05-30 1988-05-30 Dc/dc converter

Country Status (1)

Country Link
JP (1) JPH01303056A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0274156A (en) * 1988-09-08 1990-03-14 Nippon Denso Co Ltd Flyback-type dc-dc converter
WO2013012301A2 (en) * 2011-07-21 2013-01-24 Lg Innotek Co., Ltd. Apparatus for controlling surge voltage
KR101360498B1 (en) * 2011-07-21 2014-02-07 엘지이노텍 주식회사 Apparatus for controlling surge voltage

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0274156A (en) * 1988-09-08 1990-03-14 Nippon Denso Co Ltd Flyback-type dc-dc converter
WO2013012301A2 (en) * 2011-07-21 2013-01-24 Lg Innotek Co., Ltd. Apparatus for controlling surge voltage
WO2013012301A3 (en) * 2011-07-21 2013-04-25 Lg Innotek Co., Ltd. Apparatus for controlling surge voltage
KR101360498B1 (en) * 2011-07-21 2014-02-07 엘지이노텍 주식회사 Apparatus for controlling surge voltage
US9667150B2 (en) 2011-07-21 2017-05-30 Lg Innotek Co., Ltd. Apparatus for controlling surge voltage in DC-DC converter including snubber circuit

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