JPH01302919A - Error interpolation circuit - Google Patents

Abstract

PURPOSE:To prevent a word in which an error is not included from being unpreparedly interpolated by detecting in which word in a clock the error is included when there is the error which is more than the correction capacity of an error correction part in input data. CONSTITUTION:A digital sound signal string supplied to an input terminal 2 is rearranged by a prescribed regularity and the continuous error occurred on transmission is dispersed. One block in the data string is constituted by eight words of sound data and an error correction code. The error correction code is detected at the error correction part 4. When the error in one block is one, the bit in the position is inverted, whereby the error is corrected. When the errors are more than two and correction is impossible, an error detection flag F is set to the block. Rearrangement is executed in a word de interleave part 5 at every word, and interpolation in an interpolation part 6 is improved. The error correction code where the flag F is set, is processed in an interpolation part 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an error interpolation circuit suitable for application to audio equipment that digitally processes audio data.

[Prior Art] Digitization of audio signals has been actively carried out, and is often used in compact discs (CDs), satellite broadcasting, and the like.

When audio signals are digitized and transmitted, incorrect data may be included. In order to correct this error, an error interpolation circuit 10 as shown in FIG. 2 has been conventionally provided.

As shown in FIG.
e 1interleave ) 3, permutation is performed bit by bit, and continuous errors occurring in transmission are dispersed.

The output data of the bit deinterleaving unit 3 is an error correction code and a predetermined number of words are output as one block.

The error correction unit 4 has error correction capabilities that vary depending on the circuit, but when a bit error in one block is within the range of the correction capability, the data is corrected to correct data by inverting the erroneous bits.

On the other hand, if there are errors in one block that exceed the range of correction capability, the errors cannot be corrected and no correction is performed.

If there are errors in the number exceeding the correction capability, an error detection flag F is set, which indicates that an error exists in a word within the block.

This error detection flag F is transmitted separately from data. Therefore, in the figure, the transmission path of this error detection flag F is shown by a broken line for convenience.

The data that has passed through the error correction unit 4 is rearranged word by word by a word deinterleaving unit 5.

This is because when an error exists in a word, the words in the block are distributed so that error interpolation is performed using the preceding and succeeding words.

The interleaving unit 20 uses the error detection flag F to determine whether or not the word is included in a block whose error cannot be corrected by the error correction unit 4 in the word de-interleaved audio word string.

Words for which the detection flag F is not set are processed by the word delay unit 61.
．． 62 and output selection switch 21 as is.

This output selection switch 21 switches between the output block from the word delay section 62 and the output block from the average value calculation section 64 based on the state of the error detection flag F.
It is output to the output terminal 7.

On the other hand, the word for which the detection flag F is set is included in a block whose error cannot be corrected by the error correction unit 4, so there is a possibility that the word is erroneous.

However, since the audio signal is a highly continuous signal, even if an incorrect word is found, replacing it with the average value of the preceding and succeeding correct words will not cause any audible problems. Utilizing the continuity of such music signals, the calculation unit 64 uses the output words of the word delay unit 61 and the word delay unit 63.
The average value is determined at and replaced with that value.

That is, average value interpolation processing is performed.

The error interpolation circuit having such a configuration corrects and interpolates errors that occur during transmission, thereby reducing the influence of errors.

[Problem to be solved by the invention] By the way, when encoding an audio signal into a digital signal,
Error correction codes are added in units of multiple words to form one block.

As mentioned above, if the error correction unit cannot correct the error, the error detection flag F is set for all words included in the block.
stands up.

As a result, the interpolation section 20 performs interpolation on all the words.

For example, if some of the words in one block contain an error that exceeds the error correction capability, other correct words with no errors will also be interpolated and replaced with the average value of the preceding and succeeding words, resulting in the true There is a problem that the word is no longer correct.

Accordingly, the present invention proposes an error interpolation circuit that solves these conventional problems with a simple structure and interpolates only words containing errors.

[Means for solving the problem] An error correction unit that corrects errors in digital audio data, a word delay unit that delays data word by word, and an arithmetic unit that calculates an average value from words before and after a desired word. , a comparison unit that compares the average value obtained in the calculation unit and a desired word bit by bit, and the word averaged in word units and the desired word are selected. That is.

[Function] In such a configuration, as shown in FIG. 1, in the error interpolation circuit 1 according to the present invention, the digital audio data string supplied from the input terminal 2 has continuous errors occurring during transmission dispersed. The error correction unit 4 uses a predetermined word as one block.
is supplied to

The error correction unit 4 performs error correction for each block, and if there are errors in the number exceeding the correction capability, an error detection flag F indicating that errors exist in the block is set.
can be erected.

The blocks in which the error detection flag F has been set are supplied word by word to word delay units 61, 62, and 63.

The average value of the output words of the word delay sections 61 and 63 is determined in the calculation section 64, and the output words from the word delay section 62 and the calculation section 64 are compared bit by bit in the comparison section 65.

In this invention, based on the continuity of the audio signal, whether or not a word is correct is determined based on the average value of the words before and after the word.

Based on this comparison result, it can be determined whether or not to perform interpolation.
Words determined not to contain errors are output without being interpolated.

As a result, the interpolation circuit of the present invention utilizes the characteristics of the audio signal to distinguish between words that contain errors and correct words that do not contain errors among the words of the block that cannot be corrected in the error correction unit. Correct digital audio data can be output without interpolation as much as possible.

[Embodiment] Next, an example of an error interpolation circuit according to the present invention will be explained in detail with reference to FIG.

FIG. 1 is a block diagram showing the configuration of an error interpolation circuit according to the present invention.

The error interleaving circuit 1 includes a bit de-interleaving section 3, an error correction section 4, a word de-interleaving section 5,
It is composed of an interpolation section 6.

The interpolation unit 6 includes a word delay unit 61 . which delays each word.
62, 63, an average value calculation section 64, a bit comparison section 65, and an output selection switch 66.

In the error interpolation circuit 1 having such a configuration, the input terminal 2
The digital audio data stream supplied to
The signals are supplied to the interleaving unit 3 and rearranged with a predetermined regularity, and continuous errors occurring during transmission are dispersed, thereby increasing the effect of error correction.

One block of this rearranged data string is composed of, for example, eight words of audio data and an error correction code.

An error correction code has the ability to correct errors if there is one error in one block, and has the ability to detect errors if there are two or more errors.

The error correction section 4 performs error correction for each block. For example, if there is one error in one block, the error is corrected by inverting the bit at that position.

In addition, if the errors in one block exceed the range of correction capability, for example, if there are two or more errors, error correction becomes impossible and the error detection flag F indicates that errors exist in the block.
is erected.

In the word de-interleaving unit 5, in order to enhance the interpolation effect, rearrangement is performed for each word, and words containing errors are distributed and arranged so that they are not consecutive.

Here, a block in which error correction is impossible and the error detection flag F is set will be explained.

The error detection flag F is detected in the word of the block in which the error detection flag F is set at the time of output from the word delay unit 62, and it can be determined whether the word is a word that may contain an error.

The output words of the word delay section 61 and the word delay section 63 are calculated in the average value calculation section 64.

The output word of the word delay unit 62 and the operation result (output word) from the average value calculation unit 64 are compared bit by bit in a bit comparison unit 65 by extracting all bits or a suitable number of bits.

If all compared bits are equal, it is determined that this word is equal to the average value of the words before and after the word.

As a result, even if the error detection flag F is set in the error correction unit 4, the word delay unit 62 does not perform interpolation.
The output word is outputted to the output terminal 7 via the output selection switch 66.

This output selection switch 66 switches between the output word from the word delay section 62 and the output word from the average value calculation section 64 based on the comparison result from the bit comparison section 65, and outputs the output word to the output terminal 7 according to the comparison result. The words that were written can be output.

If the compared results are not equal, it is determined that the word contains an error, and the output of the average value calculation section 64 is outputted to the output terminal 7 via the output selection switch 66.

As a result, the error correction unit 4 can discriminate between words containing errors and words containing no errors among the words whose errors cannot be corrected on a block-by-block basis.

Therefore, in the interpolation unit 6, correct words are output as they are, and only incorrect words are interpolated using the preceding and succeeding words.

On the other hand, in the error correction section 4, when the error detection flag F is not set, that is, when the error in the word in the block has been corrected or there is no error, the output from the word delay section 62 is directly sent to the output selection switch 66. output via

[Effects of the Invention] As explained above, the error interpolation circuit according to the present invention includes an error correction section that corrects errors in digital audio data, a word delay section that delays data word by word, and a word delay section that delays data before and after a desired word. a computation section that computes an average value from words of This feature is characterized in that a word can be selected.

In this way, if there are more errors in the input data than the error correction unit can correct, it detects which word in the block contains the error and selects a word that does not contain an error. This is to prevent careless interpolation.

As a result, the distortion rate of the audio signal reproduced using audio data can be significantly improved.

Therefore, the error interpolation circuit according to the present invention is extremely suitable for application to audio equipment and the like.

[Brief explanation of the drawing]

FIG. 1 is a system diagram showing an embodiment of an error interpolation circuit according to the present invention, and FIG. 2 is a system diagram showing a conventional error interpolation circuit. 1...Error interpolation circuit 4...Error correction section 6...Interpolation section 61,62,63...Word delay section 64...Arithmetic section 65...Comparison section 66...Output selection switch

Claims (1)

[Claims] (1) An error correction unit that corrects errors in digital audio data; a word delay unit that delays data word by word; and an arithmetic unit that calculates an average value from words before and after a desired word; an error interpolation circuit, comprising: a comparison unit that compares the average value obtained by the calculation and a desired word in bit units; and the error interpolation circuit selects the averaged word and the desired word in units of words. .