JPH01298806A - Demodulation circuit - Google Patents

Abstract

PURPOSE:To attain excellent demodulation by applying A/D conversion at an odd number of sampling points in one cycle of a signal to be modulated and extracting a demodulated output of the signal to be modulated based on an integration value of the A/D conversion value. CONSTITUTION:An A/D converter 4 applying A/D conversion at plural and an odd number of sampling points in one cycle of a signal to be modulated and an integration means 11 to obtain an integration value of an output data of the A/D converter 4 are provided to the circuit, which extract a demodulation output of the signal to be demodulated based on an output data of the integration means 11. Thus, the demodulation with excellent noise immunity is applied. since number of sampling pints in one cycle is an odd number, the demodulation with less error is attained with a few sampling number.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a demodulation circuit that demodulates a modulated signal subjected to AM modulation or PM modulation.

(Summary of the Invention) The present invention performs A/D conversion at a number of sampling points within one cycle of a modulated signal, and extracts the demodulated output of the modulated signal based on the integrated value of the Al1)* conversion value. This allows for good demodulation.

[Conventional technology]

Image communication is used in amateur radio, personal computer communication, and the like.

On the transmitting side, one field of a standard video signal captured by a video camera is converted (Al1) and written into memory.

ii. The image data in the memory is read out at a slow speed and converted into an audio band AM signal, FM signal, or the like.

iii. Send this AM signal or T'M signal to the receiving side.

On the receiving side, iv, the original image data is demodulated from the received AM signal or FM signal, AID converted, and written into memory.

■While repeatedly reading out the image data in memory,
D/A conversion is performed to obtain a standard synchronous frequency video signal.

vi, feed this video signal to the CR'r display to play the still image.

That is what it is.

In this case, regarding the signal formant of the AM signal or FM signal transmitted and received in sections iii and iv,
Although various methods can be considered, for example, a signal Sd as shown in FIG. 6 can be considered.

In other words, when the sending side instructs to send an image,
The level reference signal RHFS is sent out as the signal Sd over a period 1'11, for example, T1-1 seconds. This signal R
The HFS is a signal for correcting the received signal Sd to a reference level on the receiving side. Therefore, the frequency f1 of the signal RHFS is, for example, f 1 = f c /1784 h 3.58 MHz / 1784 W 200611z fcz A signal S1 having a color subcarrier frequency and a predetermined constant level (amplitude).

Then, a period T2 following the period 1'1, for example 'l'2-
〇, the signal Sd is in a no-signal period for 2 seconds.

Further, the start signal 5TRT is transmitted as the signal Sd over a period T3 following the period T2, for example, 1.3=160 cycle period of the signal S1−0.08 seconds.

This signal 5TRT is a synchronization signal or a marker signal indicating that image data is transmitted following this signal 5TRT, and this signal 5TRT is, for example, a signal S1 of a constant level.

Then, the image data is transmitted in a period T4 following the period ]'3. In this case, the transmission of this image data is the signal S1
This is realized by performing AM modulation on image data and transmitting the AM signal Sa.

Further, at this time, the gradation (luminance) of one pixel in the ii image data is expressed using, for example, 4 bits. Then, as shown in FIG. 7, the signal 5a (Sx)
One cycle of is assigned to one pixel of image data (4 bits), and the amplitude of one cycle is AM-modulated according to an analog value (gradation) indicated by one pixel of image data.

However, at this time, the amplitude of the AM signal Sa is modulated so that it becomes the minimum when the image data is "0000" (-white level), and so that the amplitude of the signal Sa does not become 0 even at this minimum amplitude. is limited.

Therefore, even at the minimum amplitude, the signal Sa is not interrupted, and the signal S1 exists as a carrier signal.

Also, when the amplitude of the AM signal Sa is as large as the eel, this is the signal R
It is made equal to the amplitude of BFS.

In this way, during the period 'l'', the AM signal Sa is transmitted over the number of cycles corresponding to the number of pixels to be transmitted, for example, 160 pixels x
If there are 100 pixels, the signal is transmitted for 16,000 cycles, and the signal Sd ends at this point.

If the signal formant is like this, the signal S
d is an audio band, which can be used when transmitting and receiving image data by amateur radio or personal computer communication, or when transmitting and receiving video signals taken with an electronic still camera through a telephone line, etc. It is also possible to create an image file using an audio tape recorder.

[Problem to be solved by the invention]

By the way, when demodulating an AM signal, an envelope detection circuit or a synchronous detection circuit is generally used, but both detection circuits are equipped with a low-pass filter at the subsequent stage to detect the level of the peak point of each cycle of the AM signal. Detect this and use it as ffi
The control output is output and taken out.

Therefore, also when demodulating image data from the above-mentioned AM signal Sa, the demodulated output (image data) passes through a low-pass filter.

However, in this case, if the time constant of the low-pass filter is large, the peak value of each cycle of the signal Sa will be held in the next cycle, making it impossible to correctly extract the peak value of each cycle. At this time, one cycle of the signal Sa indicates the gradation of one pixel.

Therefore, when the time constant of the low-pass filter is large, image data cannot be extracted correctly, and the gradation of a pixel is affected by the gradation of adjacent pixels.

Conversely, when the time constant of the low-pass filter is small, such problems will be reduced, but if the AM signal Sa contains noise, most of that noise will pass through the low-pass filter as is, making it difficult to withstand. The noise level decreases, resulting in a received image of poor quality.

The present invention takes these points into consideration and aims to enable good demodulation.

[Means to solve the problem]

The present invention is a demodulation circuit that demodulates a modulated signal subjected to AM modulation or PM modulation, and includes an A/D converter (4) that performs A/D conversion at a plurality of odd sampling points within one cycle of the modulated signal. G, it has an integrating means (11) for obtaining an integral value of the output data of this A/D converter (4), and extracts the fi1M output of the modulated signal based on the output data of the integrating means (11). .

[Effect]

In the above configuration, A/D conversion is performed at multiple sampling points within one cycle of the modulated signal, and the A/D*
Since the demodulated output is extracted based on the converted value of the converted value, demodulation with excellent noise resistance is performed. Furthermore, since the sampling points within one cycle are set to an odd number, demodulation with fewer errors is possible with a smaller number of samplings.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

In the same figure, (1) indicates a receiving means for receiving the signal Sd from the other party, and this is used in the case of amateur radio, a tuner circuit including from a high frequency circuit to an audio detection circuit, and in the case of personal computer communication. For example, acoustic cabras.

Then, the signal Sd is extracted by this means (1),
This signal Sd is supplied to an A/D converter (4) through a gain control amplifier (3) after unnecessary signal components are removed by a bandpass filter (2).

This converter (4) performs A/D conversion of the signal Sd at a frequency that is several bits larger than the number of bits indicated by the signal Sa and is sufficiently higher than the frequency f1 of the signal Sa. is 6 bits.

The sampling frequency is f2-ftXm (m is a plural number and an odd number).

Also, (10) will block the microcomputer, and (11)
) is the CPU, and (12) is R in which the routine (20) of the flowchart shown in FIG. 2 is written, for example.
OM, (13) is RAM for work area, (14
) is display memory (so-called V-RAM), (15
) is the CRT controller, (16) is the input port, (1
7) and (1B) are output ports, and these circuits (1B) are output ports.
2) to (18) are connected to the CPU via the system bus (19).
(11).

For example, an 8-bit IM signal Sg is supplied from the boat (1B) to the amplifier (3) as a control signal for its gain. Also, from baud 1-(17) to AID converter (4
) is supplied with a pulse Pc as a clock for its sampling and A/D conversion, and its Al1) output Pd is supplied to the input capo (16). Note that, as is clear from the above, the frequency of the pulse P c + P d is f2. The number of bits of pulse Pd is 6 bits.

The controller (15) is also connected to the memory (14), and the controller (15) is connected to the memory (14).
) is repeatedly read out at a speed that corresponds to a standard television broadcast brightness signal, for example, and this image data is converted into an analog brightness signal by a 4-bit D/A converter (5) and then displayed on a CRT display (6). supplied to Note that the memory (14) has, for example, addresses for the number of pixels sent by the signal Sd, and
One address has a size of 4 bits.

Then, the image data is demodulated from the signal Sa by executing the routine (20) by the CPU (11).

That is, when this routine (20) is executed, in step (21), a signal Sg is output from the port (1B), and the gain of the amplifier (3) is set to the standard value (default value) by this signal Sg. Ru.

Next, in step (22), the output Pd of the converter (4) is taken into the CPU (11) through the port (16), and reception of the signal uttps in the signal Sd is checked. In this case, the check for reception of signal RHFS is based on this signal R? This is done by utilizing the fact that 4FS has a predetermined frequency f1 and a constant level, and the signal) 1
h) If 'S is not received, step (22) is repeated.

Then, when the signal ■FS is received, the process proceeds to step (
22) to step (23), and this step (2
In 3), the data Pd which is the AID conversion output of the signal RH)'S is taken in through the baud 1-(16), and the integral value Er of the data Pd during one cycle period of the signal RIEFS is determined. In other words, signal 1? Since the frequency f2 of the clock Pc is m times the frequency f1 of the HFs, for example, as shown in FIG.
m pieces of data Pd are obtained for one EFS cycle period, and if their absolute values are IEI~IE■1, then these values IE1! ~lEml is added to give the value Er Er −IEt l +lE2 14”・+ 1)!
:III l is determined. In addition, the calculation of this value Er is performed for several cycle periods of the signal FS, and the average value for one cycle period is obtained. be made into

Then, the process proceeds to step (24), in which it is checked whether the value Er is a specified value, and if it deviates from the specified value, the process proceeds to step (25) to check the signal. Amplifier by Sg (3)
The gain of is changed, and then the process returns to step (23). In this case, the change in the gain of the amplifier (3) in step (25) is performed in the direction in which the value Er matches the specified value, and therefore, by repeating steps (23) to (25), the gain of the amplifier (3) is changed. Er gradually converges to the specified value.

When the value Er falls within a predetermined tolerance with respect to the specified value, the process proceeds from step (24) to step (31), and the integral value Er of the signal REFS at this time is stored in the RAM (
13).

At this time, since the integral value Er of the data Pd, which is the A/D conversion output of the signal REFS, is the specified value, the level of the signal REFS supplied to the converter (4) is also the reference value (the specified value). ) is controlled by
Therefore, signal! ? This means that the level of the signal Sd is corrected to the reference value by EFS.

Subsequently, the process proceeds to step (32), and for example, by counting the number of cycles of the signal 5TRT based on the data Pd, the period T2. A time wait for T3 is performed, and then in step (33), the integral value Ea of the data Pd during one cycle period of the signal Sa is determined. In this case, this value Ea is also the same as the value Er, for example, the third
As shown in the figure, m in one cycle period of the signal Sa
(It is obtained by adding the absolute values IE11 to lEw+l of the data Pd of W.

Next, in step (34), the value Ea obtained in step (33) is changed to the value Er stored in step (31).
The value En=Ea/Er is obtained. In this case, the values Er, Ea are the signals RE
This is the integral value of each cycle of FS and S a, but this integral value is the signal Rt! Since FS and Sa are proportional to the levels of a, the value En indicates the level ratio of the signal REFS and the signal Sa. Also, at this time, the level of the signal REFS is the maximum level (black level) that the signal Sa can take.
be equivalent to. Therefore, the value En is a value obtained by normalizing the value Ea, that is, image data in which the gradation of a certain pixel is normalized with respect to the black level.

Subsequently, in step (35), step (34)
The value En obtained in step (14) is written to the corresponding address in the display memory (14), and then in step (36), steps (33) to () are performed for all call cycles of the signal Sa.
It is checked whether or not the process in step 35) has been performed, and if it has not been performed, the process returns to step (33) and performs steps (33) to 35 for the next cycle of the signal Sa.
When the process (35) is performed for all cycles of the signal Sa, this routine (20) is ended.

The value En written in the memory (14), that is, the image data, is read out by the controller (15), D/A converted by the converter (5), and then supplied to the display (6). (6
) will display the image sent by the other party.

According to this example, image data is demodulated from the AM decoding Sa, but for one cycle of the AM signal Sa,
A/D conversion is performed at multiple sampling points, and the A/D conversion is performed at multiple sampling points.
Since the integrated value Ea of the D-converted value is determined and image data is obtained based on this, an image can be accurately obtained every cycle without being affected by adjacent pixels.

Further, even if the AM signal Sa contains noise, only the pixels in the cycle containing the noise are affected, and the pixels in other cycles are not affected.

In addition, since A/D conversion is performed at multiple sampling points and image data is obtained based on the integrated value Ea of the A/D converted values, the number of bits in the A/D converter (4) can be reduced, and the gain Even if the gain cent in the control amplifier (3) is somewhat rough, it can be demodulated with sufficient accuracy. This also allows the amplifier (3) to be made simple.

In addition, if the number of sampling points in one cycle is sufficiently increased, the error can be reduced, but due to the processing speed of the microcomputer (10), it is not possible to make the number of sampling points longer. , the sampling points within the l cycle are odd numbers, so fj[ with less error can be performed with a small number of samplings. That is, Fig. 4 shows the variation of the integral value Ea (maximum value of Ea - minimum value of Ea) and the average value of the integral value Ea when the number of sampling points in one cycle is between 5 and 20. The ratio [%] of

As is clear from FIG. 4, by setting the number of sampling points within one cycle to an odd number, the error in the detection level can be reduced.

Note that, for example, as shown in FIG. 5, when the signal Sd has a DC component, the value IE for the first 172 cycle period
I I~lE*I and the value I of the second half 1/2 cycle period
The integral with E 11~lEml is Wa − (IEt l+lE21+−-・・+lH11
)−(lEn◆t l+lE1+z l +...
...+ IE steel 1) may be used. In this case, as shown by the broken line, when the phase of the signal Sa is reversed, this can also be detected. Furthermore, even if the signal Sd contains noise such as hum and the DC level of the signal Sd fluctuates, the noise is canceled by subtraction when calculating the value Ea, so it is not affected by the noise. .

Also, when checking the reception of the signal RH1'S in step (22), this is the signal R1! Since we are using the fact that FS is a predetermined frequency and a constant level, in order to know that it is at a constant level, we will perform the same integration as in step (23).
Therefore, step (23) can be included in step (22).

Furthermore, in the above description, the converter (4) operates using the pulse Pc formed by the CPLI (11) as a clock, but the converter (4) operates by forming the pulse Pc externally.
) as a clock, and its pulse Pc
can also be supplied to the CPU (11) as a signal indicating the timing of A/D conversion in the converter (4). Further, in the above description, one cycle of the AM signal Sa corresponds to one data, but a plurality of cycles may correspond to one data.

〔Effect of the invention〕

According to the present invention described above, A/D conversion is performed at a plurality of sampling points within one cycle of a modulated signal, and the A/D conversion is performed at a plurality of sampling points within one cycle of a modulated signal.
/l) Since the demodulated output is extracted based on the integral value of the converted value, demodulation with excellent noise resistance can be achieved. Furthermore, since the sampling points within one cycle are odd numbers, demodulation with less error can be achieved with a smaller number of samplings.

[Brief explanation of the drawing]

Figure g4yS1 is a configuration diagram showing one embodiment of the present invention, and Figures 2 to 7 are diagrams for explaining the same. (3) is a gain control amplifier, (4) is an A/D converter,
(10) is a microcomputer.

Claims (1)

[Claims] A demodulation circuit that demodulates an AM modulated or PM modulated signal, comprising: an A/D converter that performs A/D conversion at a plurality of odd sampling points within one cycle of the modulated signal;
A demodulating circuit comprising: an integrating means for obtaining an integral value of the output data of the A/D converter, and extracting a demodulated output of the modulated signal based on the output data of the integrating means.