JPH01296490A - Device and method for driving sense amplifier for semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent a voltage noise from being generated in a power source line and a grounding line at the time of sense operation by controlling the sense operation, which is executed through coupling capacity, through first and second opening and closing means. CONSTITUTION:Respective nodal points 27 and 28 in the both sides of coupling capacity 29 are caused to be in a floating condition through P and N type FET24 and 28 in a second opening and closing means 70 and held to a power source potential Vcc and a grounding potential GND. In such a condition, when the amplifying operation of a sense amplifier 50 is started and P and N type FET22 and 25 in a first opening and closing means 60 are turned on, the charge of parasitic capacity 21 in a low potential bit line 7 is moved through an N type FET19, a second signal line 17, the FET25, the capacity 29, a node 27 and the FET22 to a second signal line 14 and accumulated through a P type FET15 to the parasitic capacity of a high potential bit line 2. Then, the potential of the bit line 2 rises up and the potential of the bit line 7 falls down. By this amplifying operation, charging and discharging currents do not flow to the power source line and grounding line, and the noise is prevented from being generated in the power source line and grounding line. Then, the sense amplifier can be obtained not to generate mulfunction in the other circuit.

Description

Detailed Description of the Invention [Field of Application in Industry-42] The present invention relates to an improvement in a driving device and a driving method for a sense amplifier circuit used in a semiconductor memory, and particularly relates to improvements in the charging and driving of a power supply and grounding circuit during sensing operation. This relates to a device designed to reduce electrical discharge current.

[Prior Art] FIG. 3 does not show the overall schematic structure of a reading section of an dynamic random access memory that has been used conventionally and to which the present invention is applied.
8B is an address sofa, which receives an external address given from the outside and generates an internal address.

80X is an X decoder, which decodes the internal address signal from the address sofa AB and selects the corresponding row of the memory cell array MA. ADY is a Y decoder, which decodes the internal address from the address buffer AII and selects the corresponding column of the memory cell array MA.

Sl is (sense amplifier + T10), which detects and amplifies information possessed by the following memory cells selected in the memory cell array MA, and transmits it to the following output buffer in response to a signal from the Y decoder ADY. )-ru.

OB is an output buffer, and ST (sense amplifier +■1
In response to the read take transmitted from 0), output data D
Output out.

CG is a peripheral circuit for control signal generation, and is a dynamic
Control signals (Vll, RN) that control the timing of various operations of the random access memory.

φ, φ2. φ8...φR) is issued.

FIG. 4 is a diagram schematically showing the configuration of the memory cell array section shown in FIG. 3. In the figure, Wl, 1. Wll
,, ,-・-・-W L. is word line, BLo, BL
o, Bl+ +'lN71゜・・・・・・B L,,
, BL, , are bit lines.

One row of the following memory cells is connected to each of the word lines WL, . . . Wl-n. Bit line BLo,・
...BLm constitutes a folded bit line, and two bit lines constitute a bit line pair.

That is, the bit line BLo ends constitutes a pair of bit lines, the bit lines BL, . Configure a wire pair. (1) is a memory cell for storing information, and each bit line BL. , . . ., memory cells (1) are connected to the intersections with every other word line. That is,
In each bit line pair, a memory cell (1) is placed at the intersection of one word line and one of the bit lines of one pair.
is connected.

(+50) is a precharge/equalize circuit, which is provided for each bit line pair in order to equalize the potential of each bit line pair and precharge to a predetermined potential VB. (14) is the first signal line, (17) is the second signal line,
(50) is a sense amplifier, and sense amplifier (50)
is provided for each bit line pair, and the first and second signal lines (
14), the first and second signals φ6. which drive the sense amplifier (50) are transmitted via (17). It is activated in response to φ8, detects the potential difference between the connected human line pair, and differentially amplifies it. Ilo, Ilo is the data output bus, 1゛. .

To',...T1. , , T, , ,' are transfer gates, and each hit line old 4°, . , 'ro'...
・Selectively output data bus Il by T□, T,′
o, connected to Ilo. That is, bit lines BLo, B
L, respectively, are transfer gates T. , To' are connected to the data output path Ilo, 1. Similarly, the human lines B1.1°BL, are connected to the data output bus through transfer gates T, ,T,', respectively.
Ilo, connected to Ilo, bit line B L-, B
L- are transfer gates T, , , T, respectively. ′
Data output bus T10. – is connected to.

Each transfer gate T. , 1゛. ',...T
An address decoder signal from the Y decoder ADY is transmitted to the gates of □ and T-', thereby connecting each pair of bit lines to the data output buses Ilo and Ilo.

FIG. 5 shows a conventional embodiment connected to one of the bit line pairs shown in FIG.
FIG. 2 is a circuit diagram of a sense amplifier driving device for a random access memory.

In the figure, (2) and (7) are pitch 1- lines, (3)
is a word line, (4) is a storage node of memory cell (1),
(5) is a selection transistor of memory cell (1),
n-channel insulated gate field effect transistor (n
-FET), whose gate is a word line (3
), its source is connected to the bit line (2).

(6) is the memory capacity in which the information of the memory cell (1) is stored, one of which is connected to the drain of the selection transistor (5) via the storage node (4), and the other to the ground line shown below. . (8) is a power supply line for the bit lines (2) and (7), to which a constant voltage of about half the power supply voltage is supplied. (9) and (10) are n-FETs, (
11) is a signal line to which signals controlling the operation timing of n-FETs (9) and (10) are manually input, and (12) is an n-FIi provided between bit lines (2> and (7)).
The memory cell (1) operates at the beginning of the standby state to balance the potentials of the bit lines (2) and (7). (
13) is the signal line where the signal to control the mink is input manually, (1,5), (16)
) are p-channel insulated gates 1 to field effect transistors (hereinafter referred to as p-FETs) constituting the sense amplifier (50), (18) and (19) are n-FliTs constituting the sense amplifier (50), The sense amplifier (50) has its gate electrode and one electrode cross-connected to the bit line (
2) A pair of p-FEs connected to (7), respectively
T(15), (1B), and a pair of n-FETs (18), (1B) whose one electrode and gate electrode are cross-connected and connected to bit lines (2), (7), respectively.
19). Then p-FET
The other electrodes (15) and (16) are both connected to the first signal line (14) and receive the activation signal φ9. Also,
The other electrode of n-FET (18), (19) is the second
It is connected to the signal line (17) of and receives the activation signal φ1. (20) and (21) are bit lines (2>
, (7) parasitic capacitance, (22) is the first signal line (1
4) is a p-FET that transmits the power supply voltage, (23) is a p-FET that transmits the power supply voltage to
An input terminal for a signal that controls the operation of FIiT (22), (
24) is a power supply terminal that supplies the power supply voltage to the first signal line (14), (25) is an n-FET that conducts between the second signal line 07) and the ground line, and (2[i) is n-FET (
25), VCC is the power supply voltage, and v8 is the voltage of the power supply line of the bit lines (2) and (7), which is maintained at 1/2·VCC.

φ1 is a signal that controls the operation timing of n-FIETs (9) and (10), φ9 is an equalize signal that controls the timing to equalize the potentials of a predetermined bit line pair,
Rn is a predetermined word line drive signal that controls the timing of selecting a memory cell, positive, and φ3 is p-NE, respectively.
T (22), the first and second signals that control the operation timing of n-FET (25), GND is the ground line, v
'rp is the threshold voltage of p-FET (1,5), (16), V Tn is n-FET (18), (1
9) is the threshold voltage.

FIG. 6 is a timing chart for explaining the operation of the circuit configuration shown in FIG. 5. In FIG. 6, information of logic "1" is stored in memory cell (1); The operation when reading stored information "1" is shown.

Between time to and 11, bit line (2),
(7) are n-FETs (9) and (1,0), respectively.
is connected to the power supply line (8), and its potential is V, = V
, C/2, and the potentials between the two human lines (2) and (7) are balanced by the n-FliT (12). At this time, the potentials of the first and second signal lines (+4) and (17) for driving the sense amplifier are Vcr, /2 + IV7pl, and Vcc/, respectively.
2-VTN.

At time t2, control signal φ2. After φ becomes a low level and n-FET (9) and (IO) are turned off, when the word line drive signal Rn is inputted at time 3, n-FET (5) turns on and off. Memories notes (4)
The charges stored in the bit line (2) move to the bit line (2), and the potential of the bit line (2) increases slightly (ΔV). This increase value is the capacitance value C6 of the memory capacitor (6), the capacitance value C20 of the parasitic capacitance (20) of the bit line (2), and the capacitance value C20 of the storage node (4).
Depends on the storage voltage ■4, usually 100 to 200 m
The value is approximately V.

Next, at time t4, control signal φ3 rises and φ8 falls, p-FET (22), n-FET (25) h)O
When the potential of the first signal line (14) rises, the potential of the second signal line (17) starts to fall. Then, due to the rise and fall of the potentials of the first and second (line 8 (14), (17)), the p-FET (15),
(]Ii) and n-FET (18).

The flip-flop circuit consisting of (19) starts sensing operation, and the minute potential difference △ between bit lines (2) and (7)
Amplify V.

In this case, when the n-FET (+9) is turned on because the potential of the bit line (2) increases by △V, the parasitic capacitance of the bit line (7) increases as the potential of the second signal line (17) decreases. The charge stored in (21) is transferred to n-FET (19)
The voltage is discharged to 0V at time t5.

On the other hand, due to the potential drop of the bit line (7), the p-FET (1
5) is ON, and the potential of the bit line (2) is ■. The memory note (4) has been raised to the C level and is again at a high level (Vc
c VTN) and the logic level is reproduced.

The above is the operation of reading, amplifying, and reproducing information from the memory cell (1). When these series of operations are completed, the machine goes into a standby state in preparation for the next operation.

First, at time t8, the word line drive signal [(11) starts to fall, and at time t9, either n-FET (5) or LI
F + . Then, the memory cell (1) enters the standby state.

Next, at time L+o, the control signal φ3. ■, it's raining,
The voltage starts to rise, and at times 1 and 11 the level becomes low and then high, and the p-FET (22) and n-FfiT (25) are turned off.

Next, at time t12, the control signal φ is activated. When the n-FET (12) starts to rise, the bit line (2),
(7) is connected to the bit line (2) with a high potential level.
The charge moves from there to the bit line (7) having a lower potential level, and at about time t13, both bit lines (2) and (7) have the same potential V, -Vcc/2. At the same time, the first and second signal lines (+4) and (+7), which are in a high impedance state due to the old 7F of the p-11T (22) and n-FET (25), and the bit line ( 2)
, (7), and both signal lines (
Each potential level of 1, 4) and (17) is V. c.
/2 +l VTP l, VCC/2 VTN.

Next, at time t14, the control signal φ starts to rise.
- When FETs (9) and (10) are turned on, the power line (
8) and the bit lines (2) and (7) are coupled to form the bit line (2).

The potential level of (7) is stabilized to prepare for the next read operation.

[Problems to be Solved by the Invention] As explained above, in the read operation, one of the pair of bit lines is connected to the VCC level from the Vcc/2+△V level.
level and the other is V. It is discharged from C/2 level to O level. In order to increase the reading speed of information stored in the memory cell, this operation must be performed relatively quickly, and normally, this charging and discharging is performed within a short time of about +5 ns. Therefore, relatively large charging/discharging currents flow through the power supply line and the grounding line.

Then, let this charging/discharging current be j. It is expressed by the following (formula 1).

△t Here, C: Capacitance value of the bit line △V: Voltage change of the bit line △t: Time required for charging and discharging the bit line.・
Considering random access memory, the capacity per bit line is 0.5 Pl'', and 4096 human lines operate in one operation, so C = 0.5PF x 4096. = 2048PF Also, since the bit line is charged to 1/2 VoC,
■If cc-5V, △V = 5/2 = 2.5V If △t is 15ns, it will be 5ns, and since this relatively large current flows through the power supply line and grounding line, voltage noise due to parasitic resistance in each of these lines , which may affect the operation of other circuits commonly connected to these lines. Therefore, in the worst case, there is a problem that these other circuits may malfunction. This invention was made in order to solve the above-mentioned problems, and it does not generate voltage noise on the power supply line and ground line during sensing operation, and does not generate 'dynamic random noise' on the power supply line and ground line.
An object of the present invention is to obtain a sense amplifier driving device for an access memory and a driving method thereof.

[Means for Solving the Problem] A sense amplifier driving device for a semiconductor memory according to the present invention activates the sense amplifier by charging and discharging first and second signal lines that transmit activation signals of the sense amplifier. a first switching element provided between the first potential terminal and the coupling capacitance; a second switching element provided between the second potential terminal and the coupling capacitance; a first switching means having a first control signal generating means for generating a signal for controlling the operation of the first and second switching elements; a third switching element provided between the first signal line, a fourth switching element provided between the second switching element side of the coupling capacitance and the second signal line; and a second opening/closing means having a second control signal generating means for generating a signal for controlling the operation of the switching element No. 4, and the driving method thereof is as follows: After precharging the coupling capacitance by setting the opening/closing means in an OFF state and the first switching means in an ON state, setting the first switching means in an OFF state and bringing the coupling capacitance into a floating state;
The bit line pair and the first and second signal lines are precharged, the memory cell is selected, and its storage and signal are -
After transmitting the signal to the bit line, the second switching means is turned on to connect the precharged coupling capacitance between the first and second signal lines.

[Example 1] FIG. 1 is a circuit diagram of a sense amplifier driving device for a dynamic random access memory showing an embodiment of the present invention, and the same reference numerals as those in FIG. It is equivalent to that.

In the figure, (27) and (28) are respectively nodes, and the node (27) has an n-FET (22) and a p-FET.
- Source electrode of FET (30), node (28) has n
- Source electrode of FET (25) and n-FIET (32)
) are connected to each other. (29)
is the coupling capacitance provided between nodes (27) and (28), and (30) is the voltage ■ applied to the power supply terminal (24).

The p-FET that inputs C into the node (27), (31) is the signal that controls the operation timing of the p-FET (30).
6p input terminal, (32) is an n-FET that discharges the potential of the note (28) to the ground line GND level, (33)
, (34) are respectively notes (27) and (2
8) parasitic capacitance, (35) is a p-FET that supplies the power supply voltage VCc to the first signal line (14), (36) is a p-F
The input terminal (37) of the signal that controls the operation timing of the ET (35) connects the potential of the second signal line (17) to the ground line G.
The n-FET discharged to the level of ND, (38) is n
- Input terminal for signals that control NET (37), (60)
is the first opening/closing means, and is a p-FET (22).

n-FET (25), input terminal (23), (26
) and control signal φ8. It consists of a control signal generation system CG of φ8. (70) is the second opening/closing means, and p-FET (3
0), n-FET (32), input terminal (II), (2
4), (31,) and control signal φ2. It consists of a control signal generation system CG of φ2. φSD+φsn are each p-FE
T (35) is a signal that controls the operation timing of n-FET (37).

FIG. 2 is a timing chart for explaining the operation of the circuit configuration shown in FIG. 1, and as in the conventional example shown in FIG.
The operation when reading is shown below.

The operation will be explained below based on FIG. In addition, it takes time. ~
Since the operations up to 1 and 4 are the same as those in the conventional example, the explanation will be omitted, but in this case, up to time t1, the impedance is low and the note (27) is at the power supply voltage V. C, the node (28) is connected to the ground line GND, and the node (27) after time t2.

(28) High impedance (floating state)
The voltage is maintained at the previous potential level. Then, the amplification operation starts at time t4, and the signal φs + '<
” s is manually converted to p-FliT (22), n-FE
When T(25) starts to turn ON, the charge of the parasitic capacitance ffl(21) is reduced by the function of the sense amplifier (50).
(19), second signal line (17), n-FET (25
), coupling capacitance (29), node (27), p-FET
(22) to the first signal line (14), and further,
It will be accumulated in the parasitic capacitance (20) via the p-FET (15), and the division of this accumulated charge will be
The potential of line 2) increases, and conversely, the potential of line (7) decreases in response to the released charge. However, in reality, the presence of parasitic capacitances (33) and (34) causes losses, and the total charge of the parasitic capacitance (21) is reduced by the parasitic capacitance (
20). Therefore, the bit line (
2) The potentials in (7) are at the final level (vcc, ov)
However, a slight difference (△vH9△■1.) occurs.

Therefore, by manually inputting the delayed signals 73D and φsn of the signals T and φ3 from the input terminals (36) and (38) at time t7 to turn on the p-FET (35) and n-FET (37), the above-mentioned Bit line with compensation for loss (2)
, (7) are set to the final level vCo, OV. However, in this case, △v, 1. △
v1. The charging/discharging current corresponding to the current flowing through the power supply line or the ground line is much smaller than that in the conventional device, and does not cause malfunction of other circuits.

At this time, due to the change in potential of the second signal-return wire (17) at time t7 (△V from high to low, by the same amount), the note (28
), coupling capacity (2g), notebook (27), p-FET (
22).

In order to prevent the potential of the human wire (2) from decreasing through (15), the p
-FET (22) and n-FET (25) must be turned off, and therefore, at time t6, the signal φ8. φ8 is raised or lowered.

In addition, in accordance with the above example, F1mir (22),
(30).

(35) excludes that of p-NET, but this is not limited to each signal φ8. φ13. φ, 0
Reverse the polarity of and convert its high level to Vcc+VTN(
A deviation of more than n-1'E' (threshold voltage) is n-F
It may also be configured using ET.

Similarly, n-FET (25), (32), (:
] Regarding 7), the signal φ3φ2 that is manually applied to the gate electrode
．． By selecting the polarity and voltage value of φsn, p-FET
You can configure it using .

[Effects of the Invention] As described above, the present invention connects the precharged first and second signal lines of the sense amplifier with the precharged capacitance during the sense operation, so that the lower of the bit line pair Since the charge accumulated on the level side is transferred to the high level side, almost no charging/discharging current flows through the power supply line and ground line during sensing operation, and therefore voltage noise on these lines is reduced. Since the occurrence can be eliminated, it is possible to obtain a sense amplifier driving device for a semiconductor memory and a driving method thereof that do not cause other circuits to malfunction.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a sense amplifier driving device according to an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation shown in FIG.・A diagram showing the overall general configuration of the memory readout section, FIG. 4 is a diagram showing the outline of the configuration of the memory cell array section shown in FIG. 3, and FIG. 5 is a diagram showing the general configuration of the memory cell array section shown in FIG. The circuit diagram shown in FIG. 6 is a timing chart for explaining the operation of the circuit shown in FIG. 5. In the figure, (1) is a memory cell, (2), (7)
is the bit line, (3) is the word line, (14) is the first signal line, (17) is the second signal line, (22), (30)
is a p-type field effect transistor (p-FET), (25
), (32) are n-type field effect transistors (n-F
ET), (24) is the power supply terminal, (29) is the coupling capacitance, (
50) is a sense amplifier, (60) is a first switching means, (
70) is the second opening/closing means, and (150) is the precharge/closing means.
In the equalization circuit, GND is a ground terminal, and CG is a control signal generation peripheral circuit. In each figure, the same reference numerals indicate the same or equivalent parts.

Claims (2)

[Claims] (1) Semiconductor memory that is provided for each of a plurality of bit line pairs to which memory cells are connected, and differentially amplifies read signals of the memory cells in response to activation signals from first and second signal lines. A sense amplifier driving device comprising: a coupling capacitor for activating the sense amplifier by charging and discharging the first and second signal lines; and a coupling capacitor provided between a first potential terminal and the coupling capacitor. a first switching element provided between the second potential terminal and the coupling capacitor; and the first and second switching elements.
a first switching means having a first control signal generating means for generating a signal for controlling the operation of the switching element; and a first switching means provided between the first switching element side of the coupling capacitor and the first signal line. a third switching element, which connects the coupling capacitance to the second switching element side and the second switching element side;
and a second switching means having a fourth switching element provided between the signal lines and a second control signal generating means for generating a signal for controlling the operation of the third and fourth switching elements. A semiconductor memory sense amplifier driving device characterized by: (2) In the semiconductor memory sense amplifier driving device according to item 1, the second opening/closing means is in an OFF state, and the first opening/closing means is in an OFF state.
After precharging the coupling capacitance by turning on the switching means of the switch, turning the first switching means off to put the coupling capacitance in a floating state, and controlling the bit line pair and the first and second signals. After precharging the line, selecting the memory cell, and transmitting its storage signal to the bit line, the second opening/closing means is turned on, and the precharged coupling capacitance is connected to the first and second
A method for driving a sense amplifier of a semiconductor memory, the method comprising: connecting between signal lines of a semiconductor memory.