JPH01295530A - Ad conversion system - Google Patents

Ad conversion system

Info

Publication number
JPH01295530A
JPH01295530A JP12670788A JP12670788A JPH01295530A JP H01295530 A JPH01295530 A JP H01295530A JP 12670788 A JP12670788 A JP 12670788A JP 12670788 A JP12670788 A JP 12670788A JP H01295530 A JPH01295530 A JP H01295530A
Authority
JP
Japan
Prior art keywords
offset
conversion
converter
digital signal
signal processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12670788A
Other languages
Japanese (ja)
Inventor
Kimiharu Kataoka
公治 片岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP12670788A priority Critical patent/JPH01295530A/en
Publication of JPH01295530A publication Critical patent/JPH01295530A/en
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To attain AD conversion without offset by using a digital signal processing section so as to detect the offset and to correct it based on an input signal during a period of no input to the AD converter and an output signal of the AD converter of the period. CONSTITUTION:The AD converter applies the 1st conversion at a time t=1, and an analog signal V1 is converted into a digital signal C1 in this case. Then the 2nd conversion is applied at a time t=2 and an analog signal V2 in converted into a digital signal C2. The cycle above is repeated at t=m, that is, at the end of offset detecting period. When the offset detection period is finished at t=m, an offset is calculated and detected in a digital signal processing section. Then offset correction AD conversion is started based on the detected offset and the processing is continued till the signal processing system reaches the state of the end of AD conversion. Thus, the AD conversion independently of the offset of the AD converter is attained.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は、AD変換器とデジタル信号処理部とを含む信
号処理系に於けるAD変換方式に関するものである。
DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to an AD conversion method in a signal processing system including an AD converter and a digital signal processing section.

〈従来の技術〉 AD変換器及びデジタル信号処理部を有する信号処理系
の構成の一例を第4図に示す。アナログ入力信号404
はAD変換器401によってデジタル信号405に変換
され、デジタル信号405はデジタル信号処理部402
で処理された後、出力部403に送られる。出力部40
3では、デジタル信号若しくはアナログ信号の何れか、
又は両方が、この信号処理系の目的に応じて出力される
<Prior Art> FIG. 4 shows an example of the configuration of a signal processing system including an AD converter and a digital signal processing section. Analog input signal 404
is converted into a digital signal 405 by the AD converter 401, and the digital signal 405 is converted into a digital signal 405 by the digital signal processing unit 402.
After being processed, it is sent to the output unit 403. Output section 40
In 3, either a digital signal or an analog signal,
Or both are output depending on the purpose of this signal processing system.

さて、AD変換器401の入出力対応の一例を表1に示
す。
Now, Table 1 shows an example of input/output correspondence of the AD converter 401.

表1 表1の例では、o、oov〜5.OOVのアナログ信号
を000・・・o o (J2)〜111・・・+ I
 +(2)のnビット2 段階にデジタル化するAD変
換となっており、理論上は、o、oovはOOO−00
0(2)に、500vは111・・・I I 1(2)
に変換する。ここで、(2)は、この数字が2進数であ
ることを示す。しかし、表1に示すように、実際のAD
変換器は、その構成素子(コンデンサ、抵抗等)の精度
等の問題から、理論値に対して若干のズレ(オフセット
)を持った値を出力する。表1の例ではオフセットが+
2の例を示している。
Table 1 In the example of Table 1, o, oov to 5. OOV analog signal 000...o o (J2) ~ 111...+I
+(2) is an AD conversion that digitizes n bits in 2 steps, and theoretically, o and oov are OOO-00.
0(2), 500v is 111...I I 1(2)
Convert to Here, (2) indicates that this number is a binary number. However, as shown in Table 1, the actual AD
A converter outputs a value with a slight deviation (offset) from the theoretical value due to problems such as the accuracy of its constituent elements (capacitors, resistors, etc.). In the example in Table 1, the offset is +
Example 2 is shown.

オフセットはAD変換器の性能を示す項目の1つであり
、理想的には0である事が要求される為、いかにこのオ
フセットを少なくするかがAD変換器設計のポイントの
一つとなっており、従来多くの努力がなされてきた。
Offset is one of the items that indicate the performance of an AD converter, and ideally it is required to be 0, so how to reduce this offset is one of the points in AD converter design. , many efforts have been made in the past.

〈発明が解決しようとする課題〉 AD変換器及びデジタル信号処理部を有する信号処理系
に於いて、AD変換器のオフセットを無くした変換を行
うことは従来技術では非常に困難であるという問題点が
あった。
<Problems to be Solved by the Invention> In a signal processing system having an AD converter and a digital signal processing unit, it is extremely difficult to perform conversion without offset of the AD converter using conventional technology. was there.

〈課題氷解法するための手段及び作用〉前記問題点に対
し、本発明では、信号処理系が対象としている入力信号
がAD変換器に入力されていない期間の入力信号、及び
この期間のAD変換器の出力信号を基に、デジタル信号
処理部に於いてオフセットを検出し、対象入力信号に対
するAD変換器の出力信号についてオフセットを補正し
て、デジタル信号処理部へ取り込む構成とする事により
、オフセットの無いAD変換を可能とする。
<Means and operations for solving the problem> In order to solve the above-mentioned problems, in the present invention, the input signal of the period when the input signal targeted by the signal processing system is not input to the AD converter, and the AD conversion of this period. The offset is detected in the digital signal processing section based on the output signal of the device, and the offset is corrected for the output signal of the AD converter for the target input signal, and the offset is taken into the digital signal processing section. This enables AD conversion without

〈実施例〉 本発明の一実施例を第1図〜第3図を基に説明する。尚
、AD変換器は、便宜上、表1の対応に従う変換を行う
ものとする。
<Example> An example of the present invention will be described based on FIGS. 1 to 3. It is assumed that the AD converter performs conversion according to the correspondence shown in Table 1 for convenience.

@1図は本実施例のフローチャートである。Figure @1 is a flowchart of this embodiment.

AD変換器は実際にこの信号処理系が対象とする入力信
号が入って来る前にオフセット検出の為にAD変換を開
始する。オフセット検出は一定の期間に行うが、このオ
フセット検出のための期間は、入力信号に重畳してくる
ノイズの周波数を考慮し、また実際の信号処理装置の使
用上問題とならない程度の時間を設定すればよい。フロ
ーチャートでは、mがこの検出期間に対応するもので、
m=オフセット検出期間÷AD変換周期の関係を満たし
ている。
The AD converter starts AD conversion for offset detection before the input signal targeted by the signal processing system actually comes in. Offset detection is performed during a fixed period of time, but the period for offset detection should be set in consideration of the frequency of noise superimposed on the input signal, and should be set to a length that does not cause problems in actual use of the signal processing device. do it. In the flowchart, m corresponds to this detection period,
The relationship m=offset detection period/AD conversion period is satisfied.

AD変換器は時間1=1で1回目の変換を行い、このと
き、第2図及び第3図に示すように、アナログ信号値V
(1)がデジタル信号値C(1+に変換される。ここで
、注意すべき事は、表1に示すように、理論上はVf1
+= 2.5 Vに対応すべきC(1+は100・・・
000(2)であるが、実際は、このAD変換器の持つ
オフセット (=+2)を加えた100・・・OI 0
(2)がCmとして出力される。次に、時間t=2で2
回目の変換が行われ、アナログ信号値v(2)がデジタ
ル信号値C(2)に変換される。このサイクルは、t=
m即ちオフセット検出期間終了まで繰り返される。
The AD converter performs the first conversion at time 1=1, and at this time, as shown in FIGS. 2 and 3, the analog signal value V
(1) is converted to the digital signal value C(1+. Here, it should be noted that as shown in Table 1, theoretically Vf1
+= C that should correspond to 2.5 V (1+ is 100...
000(2), but in reality it is 100 plus the offset (=+2) of this AD converter...OI 0
(2) is output as Cm. Next, at time t=2, 2
A second conversion is performed, and the analog signal value v(2) is converted into a digital signal value C(2). This cycle is t=
This is repeated until m, that is, the end of the offset detection period.

オフセット検出期間ではAD変換器に対するオフセット
補正は行われない為、第2図及び第3図に示したように
、AD変換結果は、あたかも入力レベルが少し高い電圧
値であるかの様な変換結果となる。
During the offset detection period, offset correction is not performed on the AD converter, so as shown in Figures 2 and 3, the AD conversion results are as if the input level were a slightly higher voltage value. becomes.

さて、t=mに於いてオフセット検出期間が終了すると
、デジタル信号処理部に於いて15式によって、オフセ
ットが計算、検出される。オフセットの計算の方法はい
ろいろなものが考えられるが、本例では、t=mとt=
’m+Iとの間で上式に従って行うものとした。
Now, when the offset detection period ends at t=m, the offset is calculated and detected by Equation 15 in the digital signal processing section. There are many ways to calculate the offset, but in this example, t=m and t=
'm+I according to the above formula.

次に、この検出されたオフセットをもとにオフセット補
正AD変換が開始される。時間t =m+1に於いて、
v(m+1は、C(m+1)−オフセット=100・・
・OI 0(2)−2= + 00・・・OO0(2)
のようにして、オフセットを補正されて変換され、同様
にして、t=m+2 、・・・とAD変換が継続され、
信号処理系がAD変換終了の状態になるまで続けられる
Next, offset correction AD conversion is started based on this detected offset. At time t = m+1,
v(m+1 is C(m+1)-offset=100...
・OI 0(2)-2= + 00...OO0(2)
The offset is corrected and converted as follows, and AD conversion is continued in the same manner as t=m+2,...
This continues until the signal processing system reaches the state where AD conversion is completed.

〈発明の効果〉 以上詳細に説明したように、本発明により、AD変換器
のオフセットに関係しないAD変換が可能となり、オフ
セットが問題となる信号処理系に於いて大きな効果が得
られる。
<Effects of the Invention> As described above in detail, the present invention enables AD conversion that is not related to the offset of the AD converter, and provides a significant effect in signal processing systems where offset is a problem.

【図面の簡単な説明】 第1図は本発明の一実施例のフローチャート、第2図は
同実施例説明の為のアナログ信号例図、第3図は同実施
例説明のためのAD変換後のデジタル信号例図、第4図
はAD変換器、デジタル信号処理部を有する信号処理系
の構成例を示す図である。 符号の説明 401:AD変換器、402:デジタル信号処理部、4
03:出力部、404:アナログ信号、405:デジタ
ル信号。 代理人 弁理士 杉 山 毅 至(他1名)纂I図
[Brief Description of the Drawings] Fig. 1 is a flowchart of an embodiment of the present invention, Fig. 2 is an analog signal example diagram for explaining the embodiment, and Fig. 3 is a diagram after AD conversion for explaining the embodiment. FIG. 4 is a diagram showing an example of the configuration of a signal processing system having an AD converter and a digital signal processing section. Explanation of symbols 401: AD converter, 402: Digital signal processing unit, 4
03: Output section, 404: Analog signal, 405: Digital signal. Agent Patent Attorney Takeshi Sugiyama (and 1 other person) Compilation I

Claims (1)

【特許請求の範囲】[Claims] 1、AD変換器及びデジタル信号を処理するデジタル信
号処理部を有するシステムに於いて、上記AD変換器の
入力であるアナログ信号値に対して理論的に対応づけら
れるデジタル信号値と実際にAD変換器から出力される
デジタル信号値との差(AD変換器のオフセット)を上
記デジタル信号処理部で検出し、これを補正しつつAD
変換を行うことを特徴とするAD変換方式。
1. In a system that includes an AD converter and a digital signal processing unit that processes digital signals, the digital signal value that is theoretically associated with the analog signal value that is input to the AD converter and the actual AD conversion The digital signal processing section detects the difference with the digital signal value output from the device (AD converter offset), and corrects it while performing the AD converter offset.
An AD conversion method characterized by performing conversion.
JP12670788A 1988-05-23 1988-05-23 Ad conversion system Pending JPH01295530A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12670788A JPH01295530A (en) 1988-05-23 1988-05-23 Ad conversion system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12670788A JPH01295530A (en) 1988-05-23 1988-05-23 Ad conversion system

Publications (1)

Publication Number Publication Date
JPH01295530A true JPH01295530A (en) 1989-11-29

Family

ID=14941867

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12670788A Pending JPH01295530A (en) 1988-05-23 1988-05-23 Ad conversion system

Country Status (1)

Country Link
JP (1) JPH01295530A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04505090A (en) * 1990-08-31 1992-09-03 ゼネラル・エレクトリック・カンパニイ Improved auto-nulling device and auto-nulling method for computed tomography data acquisition systems

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04505090A (en) * 1990-08-31 1992-09-03 ゼネラル・エレクトリック・カンパニイ Improved auto-nulling device and auto-nulling method for computed tomography data acquisition systems

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