JPH01293503A - Semiconductor porcelain having positive temperature coefficient of resistance - Google Patents
Semiconductor porcelain having positive temperature coefficient of resistanceInfo
- Publication number
- JPH01293503A JPH01293503A JP12459088A JP12459088A JPH01293503A JP H01293503 A JPH01293503 A JP H01293503A JP 12459088 A JP12459088 A JP 12459088A JP 12459088 A JP12459088 A JP 12459088A JP H01293503 A JPH01293503 A JP H01293503A
- Authority
- JP
- Japan
- Prior art keywords
- internal electrodes
- electrodes
- exposed
- insulating layer
- laminate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 24
- 229910052573 porcelain Inorganic materials 0.000 title claims description 14
- 239000000919 ceramic Substances 0.000 claims abstract description 22
- 239000012212 insulator Substances 0.000 claims description 4
- 238000007747 plating Methods 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 2
- 238000009713 electroplating Methods 0.000 abstract description 18
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 6
- 229910002113 barium titanate Inorganic materials 0.000 abstract description 2
- WMWLMWRWZQELOS-UHFFFAOYSA-N bismuth(iii) oxide Chemical compound O=[Bi]O[Bi]=O WMWLMWRWZQELOS-UHFFFAOYSA-N 0.000 abstract 2
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 239000007800 oxidant agent Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000010953 base metal Substances 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 239000000843 powder Substances 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 229910010293 ceramic material Inorganic materials 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000001089 mineralizing effect Effects 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Thermistors And Varistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、セラミクス層と内部電極とを交互に積層して
なり、正の抵抗温度特性を有する半導体磁器に関し、特
に大量生産を可能にして、生産性を向上できるようにし
た半導体磁器の構造に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor porcelain, which is made up of alternately laminated ceramic layers and internal electrodes and has positive resistance-temperature characteristics, and is particularly applicable to mass production. , relates to a structure of semiconductor porcelain that can improve productivity.
（従来の技術〕
一般に、正特性サーミスタとして採用される半導体磁器
は、ある所定の温度で導体から絶縁体へ移行する特性を
有している。このような半導体磁器として、従来、第５
図に示すような構造のものがある（特開昭６１−１５３
０２号公報参照）、この半導体磁器２０は、セラミクス
層２１と内部電極２２とを交互に積層して、一体焼結さ
れた焼結体２３の両側面２３ａ、２３ｂに外部電極２４
を形成して構成されている。また、上記各内部電極２２
の図示左、右端面は、上記焼結体２３の左側面２３ａと
右側面２３ｂとに交互に導出されて上記外部電極２４に
接続されている。(Prior Art) Generally, semiconductor porcelain used as a positive temperature coefficient thermistor has the property of transitioning from a conductor to an insulator at a certain predetermined temperature.
There is a structure as shown in the figure (Japanese Unexamined Patent Publication No. 61-153
This semiconductor ceramic 20 has ceramic layers 21 and internal electrodes 22 alternately laminated, and external electrodes 24 are formed on both sides 23a and 23b of a sintered body 23 that is integrally sintered.
It is composed of the following. In addition, each of the internal electrodes 22
The left and right end faces of the sintered body 23 are alternately led out to the left side 23a and the right side 23b of the sintered body 23 and connected to the external electrode 24.
ところで、上記焼結体２３に外部電極２４を形成する場
合は、従来、導電性ペーストを塗布した後、焼付けて、
たとえばオーミック性の銀電極を形成するようにしてい
る。By the way, when forming the external electrode 24 on the sintered body 23, conventionally, a conductive paste is applied and then baked.
For example, an ohmic silver electrode is formed.
しかしながら、上記従来の外部電極の形成方法では、焼
結体の両側面に導電性ペーストを塗布する工程を含むこ
とから、生産性が低いという問題点がある。However, the above-mentioned conventional method for forming external electrodes involves a step of applying conductive paste to both sides of the sintered body, so there is a problem in that productivity is low.
本発明の目的は、上記外部ｔｉを容易に形成でき、生産
性を向上できる半導体磁器を提供することにある。An object of the present invention is to provide a semiconductor ceramic in which the above-mentioned external Ti can be easily formed and productivity can be improved.
本件発明者らは、上記従来の問題点を解決するために半
導体磁器の、特に外部電極の構造について検討したとこ
ろ、電解メッキにより上記外部電極を形成することに着
目した。この電解メッキによれば、設備が簡単で、しか
も−度に大量の処理ができることから、従来の導電性ペ
ーストを塗布する場合に比べて生産性の向上が期待でき
る。ところが、上記焼結体に電解メッキを施すと、上記
焼結体はユニット全体が半導体であることから、該ユニ
ット全体に金属が析出してしまうという問題が生じ、こ
のままでは電解メッキが採用できないことが判明した。In order to solve the above-mentioned conventional problems, the present inventors studied the structure of semiconductor ceramics, especially the external electrodes, and focused on forming the external electrodes by electrolytic plating. According to this electrolytic plating, the equipment is simple and a large amount can be processed at one time, so it can be expected to improve productivity compared to the case of applying a conventional conductive paste. However, when electrolytic plating is applied to the sintered body, since the entire unit of the sintered body is a semiconductor, a problem arises in that metal is deposited on the entire unit, and electrolytic plating cannot be used as it is. There was found.
そこで、上記焼結体の外表面の、金属析出の不要部分に
絶縁層を形成してやれば、不要部分における電解メッキ
による金属の折中を防止できることに想到し、本発明を
成したものである。Therefore, we have come up with the idea that if an insulating layer is formed on the outer surface of the sintered body in areas where metal deposition is unnecessary, it is possible to prevent the metal from breaking due to electrolytic plating in the unnecessary areas, and the present invention has been completed.
そこで本発明は、正の抵抗温度特性を有する半導体磁器
において、セラミクス層と内部電極とを交互に積層して
なる積層体の側面に上記内部電極の端面を露出させ、こ
の積層体の内部電極の露出部を除く外表面部分に絶縁層
を形成し、上記各内部電極の露出部を覆うように電解メ
ッキによって外部電極を形成したことを特徴としている
。Therefore, in a semiconductor ceramic having positive resistance-temperature characteristics, the end face of the internal electrode is exposed on the side surface of a laminate formed by alternately laminating ceramic layers and internal electrodes. The present invention is characterized in that an insulating layer is formed on the outer surface portion excluding exposed portions, and external electrodes are formed by electrolytic plating so as to cover the exposed portions of each of the internal electrodes.
ここで、上記ｍ縁層は、例えば、内部ｔｔｉの形成工程
の途中において、積層体内に内部電極用空隙層が形成さ
れた後、これを磁性容器内にＢｂｆ）ｓ等の酸化剤と共
に充填して加熱することにより、該酸化剤を熱拡散させ
て形成することができる。Here, the m-edge layer is formed by, for example, forming an internal electrode gap layer in the laminate during the process of forming the internal tti, and then filling this into a magnetic container together with an oxidizing agent such as Bbf)s. The oxidizing agent can be thermally diffused by heating the oxidizing agent.
本発明に係る正の抵抗温度特性を有する半導体磁器によ
れば、外表面の、内部電極の露出部以外の部分に絶縁層
を形成したので、電解メッキにより外部電極を形成でき
る。即ち、上記積層体をメッキ溶液中に浸漬して電解メ
ッキを施すことにより、上記内部電極の露出部のみに外
部電極としての金属が析出し、これが成長して積層体の
側面に、各内部電極の露出部を覆うように外部電極が形
成されることとなる。また、この場合の絶縁層は、例え
ば多数の積層体を磁器容器内に投入し、これに酸化剤を
添加し、該酸化剤の熱拡散により容易に形成でき、しか
も上記電解メッキ処理も一度に大量処理できるから、従
来のペーストを塗布する作業に比べて、生産性を大幅に
向上できる。According to the semiconductor porcelain having positive resistance-temperature characteristics according to the present invention, since the insulating layer is formed on the outer surface at a portion other than the exposed portion of the internal electrode, the external electrode can be formed by electrolytic plating. That is, by immersing the above-mentioned laminate in a plating solution and performing electrolytic plating, metal as the external electrode is deposited only on the exposed portions of the above-mentioned internal electrodes, and this metal grows to form the respective internal electrodes on the sides of the laminate. An external electrode is formed to cover the exposed portion. In addition, the insulating layer in this case can be easily formed by placing a large number of laminates in a ceramic container, adding an oxidizing agent thereto, and thermally diffusing the oxidizing agent, and the electrolytic plating process described above can be performed at once. Since it can be processed in large quantities, productivity can be greatly improved compared to conventional paste application work.
以下、本発明の実施例を図について説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
第１図ないし第４図は本発明の一実施例による半導体磁
器を説明するための図である。1 to 4 are diagrams for explaining semiconductor ceramics according to an embodiment of the present invention.
第１図において、ｌは本実施例の半導体磁器であり、こ
れの外形は、長さ１０ｍ、幅５ｆｌ、厚さ２日程度の直
方体状のものである。上記半導体磁器１は、チタン酸バ
リウム系セラミクス層２と卑金属、例えば錫からなる内
部電極３とを交互に積層して積層体４を形成し、該積層
体４の左、右側面４ａ、４ｂに上記内部電極３の左、右
端面を交互に露出させるとともに、該露出部３ａを除く
上記積層体４の外表面部分にＢｌ、Ｑ、からなる絶縁層
５を形成して構成されている。また、上記積層体４の両
側面４ａ、４ｂにはＮ１からなる第１外部電極６が形成
されており、この第１外部１！掻６は上記内部［橿３の
露出部３ａに接続されている。In FIG. 1, 1 is the semiconductor porcelain of this example, and its external shape is a rectangular parallelepiped with a length of 10 m, a width of 5 fl, and a thickness of about 2 days. The semiconductor ceramic 1 has a laminate 4 formed by alternately laminating barium titanate ceramic layers 2 and internal electrodes 3 made of a base metal such as tin, and has left and right side surfaces 4a and 4b of the laminate 4. The left and right end faces of the internal electrodes 3 are exposed alternately, and an insulating layer 5 made of Bl and Q is formed on the outer surface of the laminate 4 except for the exposed portions 3a. Further, first external electrodes 6 made of N1 are formed on both side surfaces 4a and 4b of the laminate 4, and the first external electrodes 6 are made of N1. The paddle 6 is connected to the exposed portion 3a of the rod 3 inside.
さらに、上記第１外部電極６の外表面には、低融点金属
の錫からなる第２外部電極７が形成されている。Further, on the outer surface of the first external electrode 6, a second external electrode 7 made of tin, a low melting point metal, is formed.
次に本実施例の半導体磁器１の製造方法を第２図ないし
第４図について説明する。Next, a method for manufacturing the semiconductor ceramic 1 of this embodiment will be explained with reference to FIGS. 2 to 4.
■ まず、主成分としての３ａＴｉＯｔに、半導体化剤
としてＹｘＯｓ、鉱化剤としてＳｉＯオ及びＡｌｔｏｓ
、特性改善剤としてＭ ｎ Ｏｔを添加して混合粉砕し
、これにアクリル系有機バインダーを混合してスラリー
状のセラミクス材料を生成する。そして、このセラミク
ス材料を所定の均一厚さのグリーンシートに成形する。■ First, 3aTiOt as the main component, YxOs as a semiconducting agent, SiO and Altos as a mineralizing agent.
, MnOt is added as a property improving agent, mixed and pulverized, and an acrylic organic binder is mixed thereto to produce a slurry-like ceramic material. Then, this ceramic material is formed into a green sheet with a predetermined uniform thickness.
■ 一方、ＢａＴｉＯｓ焼結粉末にカーボンとフェスと
を混合してペーストを作成する。そしてこのペーストを
上記グリーンシートの上面に内部を極のパターンに応じ
た形状に印刷し、これを矩形状にカッティングする。こ
れにより上記ペースト８の一辺部分８ａのみがグリーン
シート９の外縁まで延び、他の辺部分８ｂは内方に位置
することとなる０次に、第２図に示すように、上記各ペ
ースト８の一辺部分８ａが交互に外方に露出するように
各グリーンシート９をＭＭ’ｌ、さらにこの積層された
シート９の上、下にダミーとしてのセラミクスシート１
０を重ねて積層体を形成し、この積層体をプレスにより
積層方向に圧着する。(2) On the other hand, a paste is prepared by mixing BaTiOs sintered powder with carbon and Fes. Then, this paste is printed on the top surface of the green sheet in a shape corresponding to the polar pattern inside, and this is cut into a rectangular shape. As a result, only one side portion 8a of the paste 8 extends to the outer edge of the green sheet 9, and the other side portion 8b is located inward.Next, as shown in FIG. Each green sheet 9 is MM'l so that one side portion 8a is exposed to the outside alternately, and ceramic sheets 1 as a dummy are placed above and below the laminated sheets 9.
0 are piled up to form a laminate, and this laminate is pressed in the lamination direction using a press.
■ 上記積層体を、空気中にて約１３００℃に加熱し焼
成する。すると、上記ペースト８内のカーボンが焼失し
、該ペースト８部分にポーラス層１）が形成された焼結
体４が得られる（第３図（ａｌ参照）。(2) The above-mentioned laminate is heated to about 1300° C. in air and fired. Then, the carbon in the paste 8 is burned out, and a sintered body 4 in which a porous layer 1) is formed in the paste 8 portion is obtained (see FIG. 3 (al)).
■ 次に、第４図に示すような筒状の磁器ボット１２内
に上記焼結体４を投入するとともに、酸化剤としてのＢ
ｉ□０．粉末を添加し、上記ポット１２を回転させなが
ら、１０００℃に加熱する。すると、上記３ｉ、○、粉
末が焼結体４の外表面に熱拡散して該表面部分を絶縁体
化し、これにより絶縁層５が形成される（第３図〜）参
照）、ここで、上記ポーラス層１）の開口部分は、上述
の熱拡散によっても絶縁体化されることはなく、従って
上記絶縁層５は、上記焼結体４の外表面の、ポーラス層
１）の開口を除く部分に形成されることとなる。■ Next, the sintered body 4 is placed in a cylindrical porcelain pot 12 as shown in FIG.
i□0. Add the powder and heat to 1000° C. while rotating the pot 12. Then, the powder 3i, ○, thermally diffuses to the outer surface of the sintered body 4 and turns the surface portion into an insulator, thereby forming the insulating layer 5 (see FIG. 3~), where: The opening portion of the porous layer 1) is not made into an insulator even by the above-mentioned thermal diffusion, and therefore the insulation layer 5 is formed on the outer surface of the sintered body 4 excluding the opening of the porous layer 1). It will be formed in parts.
■ 次に、上記絶縁層５が形成された焼結体４を低融点
の重金］Ｉ４（錫、鉛等又はこれらの合金）、例えばｗ
Ａ溶液中に浸漬し、上記ポーラスＮｌｌ内に錫を加圧注
入する。これにより、上記ポーラスＪｉ１）部分は内部
電極３となり、該電極３の端面３ａは上記焼結体４の側
面４ａ、４ｂに露出することになる（第３図（Ｃ１参照
）。■ Next, the sintered body 4 on which the insulating layer 5 has been formed is heated with a low melting point heavy metal I4 (tin, lead, etc. or an alloy thereof), for example w
It is immersed in solution A, and tin is injected into the porous Nll under pressure. As a result, the porous Ji1) portion becomes the internal electrode 3, and the end surface 3a of the electrode 3 is exposed to the side surfaces 4a and 4b of the sintered body 4 (see FIG. 3 (C1)).
■ 上記内部電極３が形成された焼結体４をＮｉメッキ
液中に浸漬し、これを除権として直流電流を流して電解
メッキ処理を施す、すると、Ｎｉが上記内部電極３の露
出部３ａのみに析出し、これが側面４ｂ上を拡がりなが
ら成長し、これにより側面４ｂ部分に第１外部電極６が
形成されることになる。さらに、上記第１外部電極６の
表面に半田付は性を向上させるために、電解メッキ又は
スパフタリングにより錫からなる第２外部電極７を形成
する（第３図（Ｃ１参照）、これにより、本実施例の半
導体磁器１が製造されることとなる。(2) The sintered body 4 on which the internal electrodes 3 have been formed is immersed in a Ni plating solution, and electrolytic plating is performed by passing a direct current through the Ni plating solution. This precipitates only on the side surface 4b, and grows while spreading on the side surface 4b, thereby forming the first external electrode 6 on the side surface 4b. Furthermore, in order to improve soldering properties on the surface of the first external electrode 6, a second external electrode 7 made of tin is formed by electrolytic plating or sputtering (see FIG. 3 (C1)). , the semiconductor ceramic 1 of this example will be manufactured.
次に本実施例の作用効果について説明する。Next, the effects of this embodiment will be explained.
本実施例の半導体磁器１によれば、焼結体４の内部ｔｉ
３の露出部３ａを除く外表面に絶縁Ｍ５を形成したので
、外部電極６，７の形成に際して電解メッキの採用が可
能となり、生産性を向上でき、それだけ部品コストを低
減できる。According to the semiconductor ceramic 1 of this embodiment, the internal ti of the sintered body 4
Since the insulation M5 is formed on the outer surface except for the exposed portion 3a of 3, electrolytic plating can be used when forming the external electrodes 6 and 7, productivity can be improved, and component costs can be reduced accordingly.
なお、上記実施例では、焼結体４の外表面に絶縁Ｎ５を
形成し、次に卑金属を加圧注入し、電解メッキを施すこ
とによって外部電極６を形成したが、本発明では次の手
順で外部電極を形成してもよい０例えば、上記絶縁層５
を形成した後、まずポーラスの外部電極層を形成し、こ
のポーラス外部電極層及び上記ポーラス層１）の両方に
卑金属を加圧注入し、しかる後電解メッキを施してもよ
い。このようにした場合は電解メッキに要する処理時間
が大幅に短縮される。In the above embodiment, the external electrode 6 was formed by forming the insulation N5 on the outer surface of the sintered body 4, then injecting the base metal under pressure, and performing electrolytic plating, but in the present invention, the following procedure was performed. For example, the insulating layer 5 may form an external electrode.
After forming, a porous external electrode layer may be formed first, a base metal may be injected under pressure into both this porous external electrode layer and the porous layer 1), and then electrolytic plating may be performed. In this case, the processing time required for electrolytic plating is significantly shortened.
（発明の効果〕
以上のように本発明に係る正の抵抗温度特性を有する半
導体磁器によれば、積層体の内部電極の露出部を除く外
表面に絶縁層を形成したので、外部電極の形成に、大量
生産に遺した電解メッキ処理が採用でき、生産性を大幅
に向上できる効果がある。(Effects of the Invention) As described above, according to the semiconductor porcelain having positive resistance-temperature characteristics according to the present invention, since an insulating layer is formed on the outer surface of the laminate except for the exposed portion of the internal electrode, the formation of the external electrode In addition, the electrolytic plating process left behind in mass production can be used, which has the effect of greatly improving productivity.
第１図ないし第４図は本発明の一実施例による半導体磁
器を説明するための図であり、第１図（δ）はその斜視
図、第１図Ｃｂ１はその断面図、第２図ないし第４図は
その製造方法を説明するための図であり、第２図はその
分解斜視図、第３図（ａｌないし第３図ｆｅ）はそれぞ
れ断面図、第４図はその半導体磁器の表面に絶縁層を形
成する際に採用される磁器ポットを示す正面図、第５図
は従来の半導体磁器を示す断面図である。
図において、■は半導体磁器、２はセラミクス層、３は
内部電極、３ａは内部電極の露出部、４は焼結体（積層
体）、４ａ、４ｂは焼結体の側面、５は絶縁層、６は外
部電極である。
特許出願人 株式会社 村田製作所
代理人 弁理士 下 市 努
第１図
第２図1 to 4 are diagrams for explaining a semiconductor ceramic according to an embodiment of the present invention, in which FIG. 1 (δ) is a perspective view thereof, FIG. 1 Cb1 is a sectional view thereof, and FIGS. Fig. 4 is a diagram for explaining the manufacturing method, Fig. 2 is an exploded perspective view thereof, Fig. 3 (al to Fig. 3 fe) is a cross-sectional view, and Fig. 4 is a surface of the semiconductor porcelain. FIG. 5 is a front view showing a porcelain pot used for forming an insulating layer on a semiconductor porcelain pot, and FIG. 5 is a sectional view showing a conventional semiconductor porcelain pot. In the figure, ■ is semiconductor porcelain, 2 is a ceramic layer, 3 is an internal electrode, 3a is an exposed part of the internal electrode, 4 is a sintered body (laminate), 4a and 4b are the side surfaces of the sintered body, and 5 is an insulating layer. , 6 are external electrodes. Patent applicant Murata Manufacturing Co., Ltd. Representative Patent attorney Tsutomu Shimoichi Figure 1 Figure 2
Claims (1)
特性を有する半導体磁器において、セラミクス層と内部
電極とを交互に積層して積層体を形成し、該積層体の左
，右側面に上記内部電極の左，右端面を交互に露出させ
るとともに、該内部電極の露出部を除く上記積層体の外
表面部分に絶縁層を形成し、上記各内部電極の露出部を
覆うように電解メッキによって外部電極を形成したこと
を特徴とする正の抵抗温度特性を有する半導体磁器。(1) In semiconductor ceramics that have positive resistance characteristics that transform from a conductor to an insulator at a predetermined temperature, ceramic layers and internal electrodes are alternately laminated to form a laminate, and the left and right sides of the laminate are The left and right end faces of the internal electrodes are alternately exposed, and an insulating layer is formed on the outer surface of the laminate excluding the exposed parts of the internal electrodes, and electrolyzed so as to cover the exposed parts of each internal electrode. A semiconductor porcelain having positive resistance-temperature characteristics characterized by having an external electrode formed by plating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63124590A JP2531019B2 (en) | 1988-05-20 | 1988-05-20 | Semiconductor porcelain with positive resistance temperature characteristic |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63124590A JP2531019B2 (en) | 1988-05-20 | 1988-05-20 | Semiconductor porcelain with positive resistance temperature characteristic |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01293503A true JPH01293503A (en) | 1989-11-27 |
| JP2531019B2 JP2531019B2 (en) | 1996-09-04 |
Family
ID=14889225
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63124590A Expired - Lifetime JP2531019B2 (en) | 1988-05-20 | 1988-05-20 | Semiconductor porcelain with positive resistance temperature characteristic |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2531019B2 (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0644101U (en) * | 1992-11-09 | 1994-06-10 | 株式会社村田製作所 | Chip type positive temperature coefficient thermistor element |
| JP2004040085A (en) * | 2002-04-15 | 2004-02-05 | Avx Corp | Component formation by plating technique |
| JP2004040084A (en) * | 2002-04-15 | 2004-02-05 | Avx Corp | Plated terminal |
| JP2004312023A (en) * | 2003-04-08 | 2004-11-04 | Avx Corp | Plated termination |
| JP2009224802A (en) * | 2003-04-08 | 2009-10-01 | Avx Corp | Method for forming electroless plating termination |
| JP2010141073A (en) * | 2008-12-11 | 2010-06-24 | Mitsubishi Materials Corp | Method of manufacturing thermistor element, and thermistor element |
| WO2010081312A1 (en) * | 2009-01-16 | 2010-07-22 | 上海科特高分子材料有限公司 | Laminated surface mounting type thermistor and manufacturing method thereof |
| JP4573956B2 (en) * | 2000-06-30 | 2010-11-04 | 京セラ株式会社 | Multilayer electronic component and manufacturing method thereof |
| JP2014072516A (en) * | 2012-09-27 | 2014-04-21 | Samsung Electro-Mechanics Co Ltd | Multilayer ceramic electronic component |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62122104A (en) * | 1985-11-20 | 1987-06-03 | 松下電器産業株式会社 | Electrode treatment of laminated chip varistor |
| JPS6399519A (en) * | 1986-10-15 | 1988-04-30 | 株式会社村田製作所 | Manufacture of ceramic electronic component |
-
1988
- 1988-05-20 JP JP63124590A patent/JP2531019B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62122104A (en) * | 1985-11-20 | 1987-06-03 | 松下電器産業株式会社 | Electrode treatment of laminated chip varistor |
| JPS6399519A (en) * | 1986-10-15 | 1988-04-30 | 株式会社村田製作所 | Manufacture of ceramic electronic component |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0644101U (en) * | 1992-11-09 | 1994-06-10 | 株式会社村田製作所 | Chip type positive temperature coefficient thermistor element |
| JP4573956B2 (en) * | 2000-06-30 | 2010-11-04 | 京セラ株式会社 | Multilayer electronic component and manufacturing method thereof |
| US9666366B2 (en) | 2002-04-15 | 2017-05-30 | Avx Corporation | Method of making multi-layer electronic components with plated terminations |
| JP2004040085A (en) * | 2002-04-15 | 2004-02-05 | Avx Corp | Component formation by plating technique |
| JP2004040084A (en) * | 2002-04-15 | 2004-02-05 | Avx Corp | Plated terminal |
| US11195659B2 (en) | 2002-04-15 | 2021-12-07 | Avx Corporation | Plated terminations |
| US10366835B2 (en) | 2002-04-15 | 2019-07-30 | Avx Corporation | Plated terminations |
| US10020116B2 (en) | 2002-04-15 | 2018-07-10 | Avx Corporation | Plated terminations |
| JP2004312023A (en) * | 2003-04-08 | 2004-11-04 | Avx Corp | Plated termination |
| JP2004327983A (en) * | 2003-04-08 | 2004-11-18 | Avx Corp | Plated termination |
| JP2009224802A (en) * | 2003-04-08 | 2009-10-01 | Avx Corp | Method for forming electroless plating termination |
| JP2010141073A (en) * | 2008-12-11 | 2010-06-24 | Mitsubishi Materials Corp | Method of manufacturing thermistor element, and thermistor element |
| US8451084B2 (en) | 2009-01-16 | 2013-05-28 | Shanghai Keter Polymer Material Co., Ltd. | Laminated surface mounting type thermistor and manufacturing method thereof |
| WO2010081312A1 (en) * | 2009-01-16 | 2010-07-22 | 上海科特高分子材料有限公司 | Laminated surface mounting type thermistor and manufacturing method thereof |
| JP2014072516A (en) * | 2012-09-27 | 2014-04-21 | Samsung Electro-Mechanics Co Ltd | Multilayer ceramic electronic component |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2531019B2 (en) | 1996-09-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3555563B2 (en) | Manufacturing method of multilayer chip varistor and multilayer chip varistor | |
| CN107403678A (en) | Multilayer coil component | |
| JP2007242995A (en) | Laminated ceramic electronic component and its manufacturing method | |
| JPH0661708A (en) | Irreversible circuit element for microwave | |
| CN214099309U (en) | Coil component | |
| JPH01293503A (en) | Semiconductor porcelain having positive temperature coefficient of resistance | |
| JP2006253322A (en) | Electronic component | |
| JPH02135702A (en) | Lamination type varistor | |
| TWI295472B (en) | ||
| JP3735756B2 (en) | Chip-shaped electronic component and manufacturing method thereof | |
| JP2727789B2 (en) | Positive characteristic thermistor and manufacturing method thereof | |
| JPH02189903A (en) | Laminated varistor | |
| JP2004128221A (en) | Method of manufacturing chip ceramic electronic component | |
| JP3622853B2 (en) | Thermistor | |
| JP2689756B2 (en) | Sudden change thermistor and manufacturing method thereof | |
| JP2001291604A (en) | Chip-type laminated thermistor and its manufacturing method | |
| JP2001093745A (en) | Laminated chip component | |
| JP4109348B2 (en) | Electronic parts and manufacturing method thereof | |
| JPH0534122Y2 (en) | ||
| JPH0547508A (en) | Laminated semiconductor porcelain and manufacture thereof | |
| JPH04317303A (en) | Method of manufacturing positive temperature coefficient thermistor | |
| KR101333259B1 (en) | Variable resistor element and fabrication methods thereof | |
| JPH02220407A (en) | Laminated varistor | |
| KR101333258B1 (en) | Variable Resistor Element And Fabrication Methods Thereof | |
| JPH01186601A (en) | V2o3 ceramics resistor element |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |