JPH01293503A - Semiconductor porcelain having positive temperature coefficient of resistance - Google Patents

Semiconductor porcelain having positive temperature coefficient of resistance

Info

Publication number
JPH01293503A
JPH01293503A JP12459088A JP12459088A JPH01293503A JP H01293503 A JPH01293503 A JP H01293503A JP 12459088 A JP12459088 A JP 12459088A JP 12459088 A JP12459088 A JP 12459088A JP H01293503 A JPH01293503 A JP H01293503A
Authority
JP
Japan
Prior art keywords
internal electrodes
electrodes
exposed
insulating layer
laminate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12459088A
Other languages
Japanese (ja)
Other versions
JP2531019B2 (en
Inventor
Yukio Sakabe
行雄 坂部
Yutaka Shimabara
豊 島原
Yasunobu Yoneda
康信 米田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP63124590A priority Critical patent/JP2531019B2/en
Publication of JPH01293503A publication Critical patent/JPH01293503A/en
Application granted granted Critical
Publication of JP2531019B2 publication Critical patent/JP2531019B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To form external electrodes easily and improve the productivity by a method wherein ceramics layers and internal electrodes are alternately laminated to form a laminated unit, the terminals of the internal electrodes are exposed on both the sides of the laminated unit, an insulating layer is formed over the surface of the laminated unit except the exposed parts of the internal electrodes and external electrodes are formed by electrolytic plating so as to cover the exposed parts of the respective internal electrodes. CONSTITUTION:Ceramics layers 2 and internal electrodes 3 are alternately laminated to form a laminated unit 4. The left and right terminals of the internal electrodes 3 are alternately exposed on both the left and right sides 4a and 4b of the laminated unit 4 respectively. An insulating layer 5 is formed over the surface of the laminated unit 4 except the exposed parts 3a of the internal electrodes 3 and then external electrodes 6 are formed by electrolytic plating so as to cover the exposed parts 3a of the respective internal electrodes 3. For instance, the BaTiO3 ceramics layers 2 and the internal electrodes 3 made of tin are alternately laminated to form the laminated unit 4 and the insulating layer 5 made of Bi2O3 is formed over the surface of the laminated unit 4 except the exposed parts 3a of the internal electrodes 3. Then the first external electrodes 6 made of Ni are formed on both the sides 4a and 4b and, further, second external electrodes 7 made of tin are formed on the surfaces of the first extarnal electrodes 6.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、セラミクス層と内部電極とを交互に積層して
なり、正の抵抗温度特性を有する半導体磁器に関し、特
に大量生産を可能にして、生産性を向上できるようにし
た半導体磁器の構造に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor porcelain, which is made up of alternately laminated ceramic layers and internal electrodes and has positive resistance-temperature characteristics, and is particularly applicable to mass production. , relates to a structure of semiconductor porcelain that can improve productivity.

(従来の技術〕 一般に、正特性サーミスタとして採用される半導体磁器
は、ある所定の温度で導体から絶縁体へ移行する特性を
有している。このような半導体磁器として、従来、第5
図に示すような構造のものがある(特開昭61−153
02号公報参照)、この半導体磁器20は、セラミクス
層21と内部電極22とを交互に積層して、一体焼結さ
れた焼結体23の両側面23a、23bに外部電極24
を形成して構成されている。また、上記各内部電極22
の図示左、右端面は、上記焼結体23の左側面23aと
右側面23bとに交互に導出されて上記外部電極24に
接続されている。
(Prior Art) Generally, semiconductor porcelain used as a positive temperature coefficient thermistor has the property of transitioning from a conductor to an insulator at a certain predetermined temperature.
There is a structure as shown in the figure (Japanese Unexamined Patent Publication No. 61-153
This semiconductor ceramic 20 has ceramic layers 21 and internal electrodes 22 alternately laminated, and external electrodes 24 are formed on both sides 23a and 23b of a sintered body 23 that is integrally sintered.
It is composed of the following. In addition, each of the internal electrodes 22
The left and right end faces of the sintered body 23 are alternately led out to the left side 23a and the right side 23b of the sintered body 23 and connected to the external electrode 24.

ところで、上記焼結体23に外部電極24を形成する場
合は、従来、導電性ペーストを塗布した後、焼付けて、
たとえばオーミック性の銀電極を形成するようにしてい
る。
By the way, when forming the external electrode 24 on the sintered body 23, conventionally, a conductive paste is applied and then baked.
For example, an ohmic silver electrode is formed.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかしながら、上記従来の外部電極の形成方法では、焼
結体の両側面に導電性ペーストを塗布する工程を含むこ
とから、生産性が低いという問題点がある。
However, the above-mentioned conventional method for forming external electrodes involves a step of applying conductive paste to both sides of the sintered body, so there is a problem in that productivity is low.

本発明の目的は、上記外部tiを容易に形成でき、生産
性を向上できる半導体磁器を提供することにある。
An object of the present invention is to provide a semiconductor ceramic in which the above-mentioned external Ti can be easily formed and productivity can be improved.

〔問題点を解決するための手段〕[Means for solving problems]

本件発明者らは、上記従来の問題点を解決するために半
導体磁器の、特に外部電極の構造について検討したとこ
ろ、電解メッキにより上記外部電極を形成することに着
目した。この電解メッキによれば、設備が簡単で、しか
も−度に大量の処理ができることから、従来の導電性ペ
ーストを塗布する場合に比べて生産性の向上が期待でき
る。ところが、上記焼結体に電解メッキを施すと、上記
焼結体はユニット全体が半導体であることから、該ユニ
ット全体に金属が析出してしまうという問題が生じ、こ
のままでは電解メッキが採用できないことが判明した。
In order to solve the above-mentioned conventional problems, the present inventors studied the structure of semiconductor ceramics, especially the external electrodes, and focused on forming the external electrodes by electrolytic plating. According to this electrolytic plating, the equipment is simple and a large amount can be processed at one time, so it can be expected to improve productivity compared to the case of applying a conventional conductive paste. However, when electrolytic plating is applied to the sintered body, since the entire unit of the sintered body is a semiconductor, a problem arises in that metal is deposited on the entire unit, and electrolytic plating cannot be used as it is. There was found.

そこで、上記焼結体の外表面の、金属析出の不要部分に
絶縁層を形成してやれば、不要部分における電解メッキ
による金属の折中を防止できることに想到し、本発明を
成したものである。
Therefore, we have come up with the idea that if an insulating layer is formed on the outer surface of the sintered body in areas where metal deposition is unnecessary, it is possible to prevent the metal from breaking due to electrolytic plating in the unnecessary areas, and the present invention has been completed.

そこで本発明は、正の抵抗温度特性を有する半導体磁器
において、セラミクス層と内部電極とを交互に積層して
なる積層体の側面に上記内部電極の端面を露出させ、こ
の積層体の内部電極の露出部を除く外表面部分に絶縁層
を形成し、上記各内部電極の露出部を覆うように電解メ
ッキによって外部電極を形成したことを特徴としている
Therefore, in a semiconductor ceramic having positive resistance-temperature characteristics, the end face of the internal electrode is exposed on the side surface of a laminate formed by alternately laminating ceramic layers and internal electrodes. The present invention is characterized in that an insulating layer is formed on the outer surface portion excluding exposed portions, and external electrodes are formed by electrolytic plating so as to cover the exposed portions of each of the internal electrodes.

ここで、上記m縁層は、例えば、内部ttiの形成工程
の途中において、積層体内に内部電極用空隙層が形成さ
れた後、これを磁性容器内にBbf)s等の酸化剤と共
に充填して加熱することにより、該酸化剤を熱拡散させ
て形成することができる。
Here, the m-edge layer is formed by, for example, forming an internal electrode gap layer in the laminate during the process of forming the internal tti, and then filling this into a magnetic container together with an oxidizing agent such as Bbf)s. The oxidizing agent can be thermally diffused by heating the oxidizing agent.

〔作用〕[Effect]

本発明に係る正の抵抗温度特性を有する半導体磁器によ
れば、外表面の、内部電極の露出部以外の部分に絶縁層
を形成したので、電解メッキにより外部電極を形成でき
る。即ち、上記積層体をメッキ溶液中に浸漬して電解メ
ッキを施すことにより、上記内部電極の露出部のみに外
部電極としての金属が析出し、これが成長して積層体の
側面に、各内部電極の露出部を覆うように外部電極が形
成されることとなる。また、この場合の絶縁層は、例え
ば多数の積層体を磁器容器内に投入し、これに酸化剤を
添加し、該酸化剤の熱拡散により容易に形成でき、しか
も上記電解メッキ処理も一度に大量処理できるから、従
来のペーストを塗布する作業に比べて、生産性を大幅に
向上できる。
According to the semiconductor porcelain having positive resistance-temperature characteristics according to the present invention, since the insulating layer is formed on the outer surface at a portion other than the exposed portion of the internal electrode, the external electrode can be formed by electrolytic plating. That is, by immersing the above-mentioned laminate in a plating solution and performing electrolytic plating, metal as the external electrode is deposited only on the exposed portions of the above-mentioned internal electrodes, and this metal grows to form the respective internal electrodes on the sides of the laminate. An external electrode is formed to cover the exposed portion. In addition, the insulating layer in this case can be easily formed by placing a large number of laminates in a ceramic container, adding an oxidizing agent thereto, and thermally diffusing the oxidizing agent, and the electrolytic plating process described above can be performed at once. Since it can be processed in large quantities, productivity can be greatly improved compared to conventional paste application work.

〔実施例〕〔Example〕

以下、本発明の実施例を図について説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

第1図ないし第4図は本発明の一実施例による半導体磁
器を説明するための図である。
1 to 4 are diagrams for explaining semiconductor ceramics according to an embodiment of the present invention.

第1図において、lは本実施例の半導体磁器であり、こ
れの外形は、長さ10m、幅5fl、厚さ2日程度の直
方体状のものである。上記半導体磁器1は、チタン酸バ
リウム系セラミクス層2と卑金属、例えば錫からなる内
部電極3とを交互に積層して積層体4を形成し、該積層
体4の左、右側面4a、4bに上記内部電極3の左、右
端面を交互に露出させるとともに、該露出部3aを除く
上記積層体4の外表面部分にBl、Q、からなる絶縁層
5を形成して構成されている。また、上記積層体4の両
側面4a、4bにはN1からなる第1外部電極6が形成
されており、この第1外部1!掻6は上記内部[橿3の
露出部3aに接続されている。
In FIG. 1, 1 is the semiconductor porcelain of this example, and its external shape is a rectangular parallelepiped with a length of 10 m, a width of 5 fl, and a thickness of about 2 days. The semiconductor ceramic 1 has a laminate 4 formed by alternately laminating barium titanate ceramic layers 2 and internal electrodes 3 made of a base metal such as tin, and has left and right side surfaces 4a and 4b of the laminate 4. The left and right end faces of the internal electrodes 3 are exposed alternately, and an insulating layer 5 made of Bl and Q is formed on the outer surface of the laminate 4 except for the exposed portions 3a. Further, first external electrodes 6 made of N1 are formed on both side surfaces 4a and 4b of the laminate 4, and the first external electrodes 6 are made of N1. The paddle 6 is connected to the exposed portion 3a of the rod 3 inside.

さらに、上記第1外部電極6の外表面には、低融点金属
の錫からなる第2外部電極7が形成されている。
Further, on the outer surface of the first external electrode 6, a second external electrode 7 made of tin, a low melting point metal, is formed.

次に本実施例の半導体磁器1の製造方法を第2図ないし
第4図について説明する。
Next, a method for manufacturing the semiconductor ceramic 1 of this embodiment will be explained with reference to FIGS. 2 to 4.

■ まず、主成分としての3aTiOtに、半導体化剤
としてYxOs、鉱化剤としてSiOオ及びAltos
、特性改善剤としてM n Otを添加して混合粉砕し
、これにアクリル系有機バインダーを混合してスラリー
状のセラミクス材料を生成する。そして、このセラミク
ス材料を所定の均一厚さのグリーンシートに成形する。
■ First, 3aTiOt as the main component, YxOs as a semiconducting agent, SiO and Altos as a mineralizing agent.
, MnOt is added as a property improving agent, mixed and pulverized, and an acrylic organic binder is mixed thereto to produce a slurry-like ceramic material. Then, this ceramic material is formed into a green sheet with a predetermined uniform thickness.

■ 一方、BaTiOs焼結粉末にカーボンとフェスと
を混合してペーストを作成する。そしてこのペーストを
上記グリーンシートの上面に内部を極のパターンに応じ
た形状に印刷し、これを矩形状にカッティングする。こ
れにより上記ペースト8の一辺部分8aのみがグリーン
シート9の外縁まで延び、他の辺部分8bは内方に位置
することとなる0次に、第2図に示すように、上記各ペ
ースト8の一辺部分8aが交互に外方に露出するように
各グリーンシート9をMM’l、さらにこの積層された
シート9の上、下にダミーとしてのセラミクスシート1
0を重ねて積層体を形成し、この積層体をプレスにより
積層方向に圧着する。
(2) On the other hand, a paste is prepared by mixing BaTiOs sintered powder with carbon and Fes. Then, this paste is printed on the top surface of the green sheet in a shape corresponding to the polar pattern inside, and this is cut into a rectangular shape. As a result, only one side portion 8a of the paste 8 extends to the outer edge of the green sheet 9, and the other side portion 8b is located inward.Next, as shown in FIG. Each green sheet 9 is MM'l so that one side portion 8a is exposed to the outside alternately, and ceramic sheets 1 as a dummy are placed above and below the laminated sheets 9.
0 are piled up to form a laminate, and this laminate is pressed in the lamination direction using a press.

■ 上記積層体を、空気中にて約1300℃に加熱し焼
成する。すると、上記ペースト8内のカーボンが焼失し
、該ペースト8部分にポーラス層1)が形成された焼結
体4が得られる(第3図(al参照)。
(2) The above-mentioned laminate is heated to about 1300° C. in air and fired. Then, the carbon in the paste 8 is burned out, and a sintered body 4 in which a porous layer 1) is formed in the paste 8 portion is obtained (see FIG. 3 (al)).

■ 次に、第4図に示すような筒状の磁器ボット12内
に上記焼結体4を投入するとともに、酸化剤としてのB
i□0.粉末を添加し、上記ポット12を回転させなが
ら、1000℃に加熱する。すると、上記3i、○、粉
末が焼結体4の外表面に熱拡散して該表面部分を絶縁体
化し、これにより絶縁層5が形成される(第3図〜)参
照)、ここで、上記ポーラス層1)の開口部分は、上述
の熱拡散によっても絶縁体化されることはなく、従って
上記絶縁層5は、上記焼結体4の外表面の、ポーラス層
1)の開口を除く部分に形成されることとなる。
■ Next, the sintered body 4 is placed in a cylindrical porcelain pot 12 as shown in FIG.
i□0. Add the powder and heat to 1000° C. while rotating the pot 12. Then, the powder 3i, ○, thermally diffuses to the outer surface of the sintered body 4 and turns the surface portion into an insulator, thereby forming the insulating layer 5 (see FIG. 3~), where: The opening portion of the porous layer 1) is not made into an insulator even by the above-mentioned thermal diffusion, and therefore the insulation layer 5 is formed on the outer surface of the sintered body 4 excluding the opening of the porous layer 1). It will be formed in parts.

■ 次に、上記絶縁層5が形成された焼結体4を低融点
の重金]I4(錫、鉛等又はこれらの合金)、例えばw
A溶液中に浸漬し、上記ポーラスNll内に錫を加圧注
入する。これにより、上記ポーラスJi1)部分は内部
電極3となり、該電極3の端面3aは上記焼結体4の側
面4a、4bに露出することになる(第3図(C1参照
)。
■ Next, the sintered body 4 on which the insulating layer 5 has been formed is heated with a low melting point heavy metal I4 (tin, lead, etc. or an alloy thereof), for example w
It is immersed in solution A, and tin is injected into the porous Nll under pressure. As a result, the porous Ji1) portion becomes the internal electrode 3, and the end surface 3a of the electrode 3 is exposed to the side surfaces 4a and 4b of the sintered body 4 (see FIG. 3 (C1)).

■ 上記内部電極3が形成された焼結体4をNiメッキ
液中に浸漬し、これを除権として直流電流を流して電解
メッキ処理を施す、すると、Niが上記内部電極3の露
出部3aのみに析出し、これが側面4b上を拡がりなが
ら成長し、これにより側面4b部分に第1外部電極6が
形成されることになる。さらに、上記第1外部電極6の
表面に半田付は性を向上させるために、電解メッキ又は
スパフタリングにより錫からなる第2外部電極7を形成
する(第3図(C1参照)、これにより、本実施例の半
導体磁器1が製造されることとなる。
(2) The sintered body 4 on which the internal electrodes 3 have been formed is immersed in a Ni plating solution, and electrolytic plating is performed by passing a direct current through the Ni plating solution. This precipitates only on the side surface 4b, and grows while spreading on the side surface 4b, thereby forming the first external electrode 6 on the side surface 4b. Furthermore, in order to improve soldering properties on the surface of the first external electrode 6, a second external electrode 7 made of tin is formed by electrolytic plating or sputtering (see FIG. 3 (C1)). , the semiconductor ceramic 1 of this example will be manufactured.

次に本実施例の作用効果について説明する。Next, the effects of this embodiment will be explained.

本実施例の半導体磁器1によれば、焼結体4の内部ti
3の露出部3aを除く外表面に絶縁M5を形成したので
、外部電極6,7の形成に際して電解メッキの採用が可
能となり、生産性を向上でき、それだけ部品コストを低
減できる。
According to the semiconductor ceramic 1 of this embodiment, the internal ti of the sintered body 4
Since the insulation M5 is formed on the outer surface except for the exposed portion 3a of 3, electrolytic plating can be used when forming the external electrodes 6 and 7, productivity can be improved, and component costs can be reduced accordingly.

なお、上記実施例では、焼結体4の外表面に絶縁N5を
形成し、次に卑金属を加圧注入し、電解メッキを施すこ
とによって外部電極6を形成したが、本発明では次の手
順で外部電極を形成してもよい0例えば、上記絶縁層5
を形成した後、まずポーラスの外部電極層を形成し、こ
のポーラス外部電極層及び上記ポーラス層1)の両方に
卑金属を加圧注入し、しかる後電解メッキを施してもよ
い。このようにした場合は電解メッキに要する処理時間
が大幅に短縮される。
In the above embodiment, the external electrode 6 was formed by forming the insulation N5 on the outer surface of the sintered body 4, then injecting the base metal under pressure, and performing electrolytic plating, but in the present invention, the following procedure was performed. For example, the insulating layer 5 may form an external electrode.
After forming, a porous external electrode layer may be formed first, a base metal may be injected under pressure into both this porous external electrode layer and the porous layer 1), and then electrolytic plating may be performed. In this case, the processing time required for electrolytic plating is significantly shortened.

(発明の効果〕 以上のように本発明に係る正の抵抗温度特性を有する半
導体磁器によれば、積層体の内部電極の露出部を除く外
表面に絶縁層を形成したので、外部電極の形成に、大量
生産に遺した電解メッキ処理が採用でき、生産性を大幅
に向上できる効果がある。
(Effects of the Invention) As described above, according to the semiconductor porcelain having positive resistance-temperature characteristics according to the present invention, since an insulating layer is formed on the outer surface of the laminate except for the exposed portion of the internal electrode, the formation of the external electrode In addition, the electrolytic plating process left behind in mass production can be used, which has the effect of greatly improving productivity.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図ないし第4図は本発明の一実施例による半導体磁
器を説明するための図であり、第1図(δ)はその斜視
図、第1図Cb1はその断面図、第2図ないし第4図は
その製造方法を説明するための図であり、第2図はその
分解斜視図、第3図(alないし第3図fe)はそれぞ
れ断面図、第4図はその半導体磁器の表面に絶縁層を形
成する際に採用される磁器ポットを示す正面図、第5図
は従来の半導体磁器を示す断面図である。 図において、■は半導体磁器、2はセラミクス層、3は
内部電極、3aは内部電極の露出部、4は焼結体(積層
体)、4a、4bは焼結体の側面、5は絶縁層、6は外
部電極である。 特許出願人  株式会社 村田製作所 代理人    弁理士 下 市  努 第1図 第2図
1 to 4 are diagrams for explaining a semiconductor ceramic according to an embodiment of the present invention, in which FIG. 1 (δ) is a perspective view thereof, FIG. 1 Cb1 is a sectional view thereof, and FIGS. Fig. 4 is a diagram for explaining the manufacturing method, Fig. 2 is an exploded perspective view thereof, Fig. 3 (al to Fig. 3 fe) is a cross-sectional view, and Fig. 4 is a surface of the semiconductor porcelain. FIG. 5 is a front view showing a porcelain pot used for forming an insulating layer on a semiconductor porcelain pot, and FIG. 5 is a sectional view showing a conventional semiconductor porcelain pot. In the figure, ■ is semiconductor porcelain, 2 is a ceramic layer, 3 is an internal electrode, 3a is an exposed part of the internal electrode, 4 is a sintered body (laminate), 4a and 4b are the side surfaces of the sintered body, and 5 is an insulating layer. , 6 are external electrodes. Patent applicant Murata Manufacturing Co., Ltd. Representative Patent attorney Tsutomu Shimoichi Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] (1)所定の温度で導体から絶縁体に転移する正の抵抗
特性を有する半導体磁器において、セラミクス層と内部
電極とを交互に積層して積層体を形成し、該積層体の左
,右側面に上記内部電極の左,右端面を交互に露出させ
るとともに、該内部電極の露出部を除く上記積層体の外
表面部分に絶縁層を形成し、上記各内部電極の露出部を
覆うように電解メッキによって外部電極を形成したこと
を特徴とする正の抵抗温度特性を有する半導体磁器。
(1) In semiconductor ceramics that have positive resistance characteristics that transform from a conductor to an insulator at a predetermined temperature, ceramic layers and internal electrodes are alternately laminated to form a laminate, and the left and right sides of the laminate are The left and right end faces of the internal electrodes are alternately exposed, and an insulating layer is formed on the outer surface of the laminate excluding the exposed parts of the internal electrodes, and electrolyzed so as to cover the exposed parts of each internal electrode. A semiconductor porcelain having positive resistance-temperature characteristics characterized by having an external electrode formed by plating.
JP63124590A 1988-05-20 1988-05-20 Semiconductor porcelain with positive resistance temperature characteristic Expired - Lifetime JP2531019B2 (en)

Priority Applications (1)

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Application Number Priority Date Filing Date Title
JP63124590A JP2531019B2 (en) 1988-05-20 1988-05-20 Semiconductor porcelain with positive resistance temperature characteristic

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JPH01293503A true JPH01293503A (en) 1989-11-27
JP2531019B2 JP2531019B2 (en) 1996-09-04

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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0644101U (en) * 1992-11-09 1994-06-10 株式会社村田製作所 Chip type positive temperature coefficient thermistor element
JP2004040085A (en) * 2002-04-15 2004-02-05 Avx Corp Component formation by plating technique
JP2004040084A (en) * 2002-04-15 2004-02-05 Avx Corp Plated terminal
JP2004312023A (en) * 2003-04-08 2004-11-04 Avx Corp Plated termination
JP2009224802A (en) * 2003-04-08 2009-10-01 Avx Corp Method for forming electroless plating termination
JP2010141073A (en) * 2008-12-11 2010-06-24 Mitsubishi Materials Corp Method of manufacturing thermistor element, and thermistor element
WO2010081312A1 (en) * 2009-01-16 2010-07-22 上海科特高分子材料有限公司 Laminated surface mounting type thermistor and manufacturing method thereof
JP4573956B2 (en) * 2000-06-30 2010-11-04 京セラ株式会社 Multilayer electronic component and manufacturing method thereof
JP2014072516A (en) * 2012-09-27 2014-04-21 Samsung Electro-Mechanics Co Ltd Multilayer ceramic electronic component

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62122104A (en) * 1985-11-20 1987-06-03 松下電器産業株式会社 Electrode treatment of laminated chip varistor
JPS6399519A (en) * 1986-10-15 1988-04-30 株式会社村田製作所 Manufacture of ceramic electronic component

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62122104A (en) * 1985-11-20 1987-06-03 松下電器産業株式会社 Electrode treatment of laminated chip varistor
JPS6399519A (en) * 1986-10-15 1988-04-30 株式会社村田製作所 Manufacture of ceramic electronic component

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0644101U (en) * 1992-11-09 1994-06-10 株式会社村田製作所 Chip type positive temperature coefficient thermistor element
JP4573956B2 (en) * 2000-06-30 2010-11-04 京セラ株式会社 Multilayer electronic component and manufacturing method thereof
US9666366B2 (en) 2002-04-15 2017-05-30 Avx Corporation Method of making multi-layer electronic components with plated terminations
JP2004040085A (en) * 2002-04-15 2004-02-05 Avx Corp Component formation by plating technique
JP2004040084A (en) * 2002-04-15 2004-02-05 Avx Corp Plated terminal
US11195659B2 (en) 2002-04-15 2021-12-07 Avx Corporation Plated terminations
US10366835B2 (en) 2002-04-15 2019-07-30 Avx Corporation Plated terminations
US10020116B2 (en) 2002-04-15 2018-07-10 Avx Corporation Plated terminations
JP2004312023A (en) * 2003-04-08 2004-11-04 Avx Corp Plated termination
JP2004327983A (en) * 2003-04-08 2004-11-18 Avx Corp Plated termination
JP2009224802A (en) * 2003-04-08 2009-10-01 Avx Corp Method for forming electroless plating termination
JP2010141073A (en) * 2008-12-11 2010-06-24 Mitsubishi Materials Corp Method of manufacturing thermistor element, and thermistor element
US8451084B2 (en) 2009-01-16 2013-05-28 Shanghai Keter Polymer Material Co., Ltd. Laminated surface mounting type thermistor and manufacturing method thereof
WO2010081312A1 (en) * 2009-01-16 2010-07-22 上海科特高分子材料有限公司 Laminated surface mounting type thermistor and manufacturing method thereof
JP2014072516A (en) * 2012-09-27 2014-04-21 Samsung Electro-Mechanics Co Ltd Multilayer ceramic electronic component

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