JPH01293002A - Beam forming/zero sensitivity navigation optimum array - Google Patents

Abstract

PURPOSE: To simultaneously execute beam formation and zero-sensitivity steering by providing a first means for supplying a desired signal and an unwanted signal received with the desired signal a second means for coordinating a zero- sensitivity steering means and a beam-forming means. CONSTITUTION: A first means supplies the desired signal and the unwanted signal received with this desired signal and is combined with a zero-sensitivity steering means 100, which erases at least a part of the unwanted signal. A beam-forming means is also combined with the first means to separate the desired signal and the unwanted signal and to reinforce at least a part of the desired signal. A second means coordinates the zero-sensitivity steering means 100 and the beam-forming means 200. Thereby beam formation and zero- sensitivity steering can be simultaneously executed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an optimal signal processing device for boat fishing, and more particularly to an optimal processor including beamforming and zero-sensitivity steering of an array antenna.

Communication signals whose spectrum has been broadened by being phase-encoded are
Acquisition in the presence of interference with the aid of an optimal array antenna under the control of the well-known LMS (least mean square) algorithm that minimizes the power 1. It is possible to synchronize. However, the optimal signal-to-interference (S/I) ratio at the array output for a system using this type of processing is
Although sufficient for acquisition and synchronization, it results in undesirable reporting quality. In the best case, this
This is several decibels below the theoretical maximum obtained when direction of arrival (beam steering) information is available.

In narrowband interference (eg, AM radio) communication systems, the spectral band of the interference source is much wider than the band of the desired signal. In this case, zero-sensitivity steering can be performed by an LMS algorithm in which the control signal of the optimal processor is spectrally adjusted in advance to prevent the formation of zero-sensitivity with respect to the desired signal.

Main object of the present invention is to provide an optimal processor that simultaneously performs beamforming and atmospheric sensitivity steering.

Another object of the invention is to provide optimal processing using a first optimal control loop with an off-epoch sample/hold filter and a second optimal control loop with an on-epoch sample/hold filter. be.

The present invention includes an apparatus for canceling interference to a desired signal caused by a source that is clearly identifiable as the source of the desired signal.

The first means is associated with zero-sensitivity steering means for supplying the desired signal and the unwanted signal received with the desired signal, and for separating the desired signal and the unwanted signal. The zero-sensitivity steering means cancels at least a portion of the unwanted signal. Beam forming means is also associated with the first means to separate desired and unwanted signals and to enhance at least a portion of the desired signal. The second means coordinates the zero sensitivity steering means and the beam forming means. The zero sensitivity steering loop and beamforming loop use on and off epoch processors. The zero-sensitivity steering means reduces the gain of the radiation pattern of the array antenna in the direction of the interference source. The beam forming means increases the gain of the sub-radiation pattern of the array antenna in the direction of the desired signal source.

The present invention will be described in detail below based on the accompanying drawings.

DETAILED DESCRIPTION OF THE INVENTION FIGS. 1-3 are signal line block diagrams used to represent an overview of vector systems involving multiple signals. As used in the following description, the term "line" refers to multiple paths for transmitting one or more signals, and the term "mixer" refers to vector weighted multiplication in mixing multiple signals.

FIG. 1 is a block diagram forming the general features of the invention. The array antenna 300 of this example is illustrated as having four antenna elements 301, 302, 303 and 304 positioned to receive electromagnetic signals. Although the invention is described below with respect to receiving electromagnetic signals, it should be understood that the principles of the invention are equally applicable to acoustic signals. In this case, the elements of the antenna would be transducers that convert sound energy into electrical energy. Four elements 30 of antenna 300
It should be understood that 1-304 are shown as examples and that more elements could be used in practice. Also, overall, depending on the environment in which antenna 300 is deployed, element 30
It should also be understood that 1-304 can be positioned on a straight line or on a curved surface. Positioning the elements of antenna 300 on a curved surface may be the case when the antenna element is placed on an aircraft, where the element is positioned on a curved surface of the fuselage or wing of the aircraft. Good morning.

The optimal processing of the input signals received by elements 301-304 is as follows:
Optimal signal processors 305, 306, 307 and 30 are coupled to these elements 301-304, respectively.
This is carried out by 8. The output signals of the processors 305-308 are applied to the input terminals of the adder circuit 309 and output on line 310 as a mixed signal contributed by all the elements 301-304 of the antenna 300. The output signal on line 310 is also fed back to each processor 305-308 and is used as a reference signal for the generation of weighting factors. These weighting factors are optimally applied to the input signals of the respective elements 301-304 by processors 305-308 according to the invention, as described below.

Note that each processor 305-308 in combination with a respective antenna element 301-304 constitutes a separate signal processing channel, with each channel sharing a summing circuit 309 that provides a common reference signal on line 310. I want to be Each of these channels behaves the same way,
Consists of the same circuit. Accordingly, although circuitry within processor 305 is described below by way of example, it should be understood that this description applies equally to other processors 306-308. The general form of a set of processors sharing a common summing circuit for weighting antenna signals is well known and need not be explained in order to understand the present invention. The present invention utilizes a processor 30 as described below.
It concerns a circuit of a signal processor such as No. 5.

As shown in FIG. 1, the desired signal along with unwanted (ie, interfering) signals is provided by line 10 to mixer 11. As shown in FIG. The desired signal with interference is also provided to the beamforming circuit 200 via line 12 and to the zero sensitivity steering circuit 100 via line 13. The output of the zero-sensitivity steering circuit 100 is supplied via line 14 to a coordinator 15;
It is added to the output of beam shaping circuit 200, which is supplied from line 16. The aligned sum is fed via line 9 to mixer 11 and further mixed with the relevant signals of the other channels by summing circuit 309 so that line 310
The mixed output signals on and 17 consist of the desired signal and the interference mixed with the output of coordinator 15. This mixed signal is sent via line 18 to beamforming circuit 200.
They are also supplied to a zero sensitivity steering circuit 100 via a line 19, respectively. Effectively, the zero-sensitivity steering circuit 100 functions as a first vector loop 1 that cancels at least a portion of the interfering signal. Conversely, the beamforming circuit functions as a second vector loop 2 that enhances at least part of the desired signal. The mixed signal supplied by line 17 therefore has an increased S/I ratio and therefore an increased reporting quality.

The zero-sensitivity steering circuit and beamforming circuit may perform their functions by temporal processing or by spectral processing. Processing of phase-encoded, broadband-spread communication signals can be time-processed using a processor 305, the details of which are shown in FIG.

As shown in FIG. 2, the desired signal and the interfering signal are
An automatic gain control circuit (A
GC) 20. AGC20 output is line 2
1 to the matched filter 22 and encoded with a specific code of the desired signal. The output of the matched filter 22 is fed via line 23 to a first wideband vector weight control loop IWB for zero-sensitivity steering and to a second wideband vector weight control loop 2WB for beamforming. In the first vector loop IWB, line 2
The reference signal supplied from 4 is an off-epoch sample/
In the hold filter circuit 101, the line 2
The feedback signal supplied from 5 is off-epoch.
Processed by sample/hold filter circuit 103. The processed signal is supplied to a correlation circuit 102,
The signal of antenna element 301 is fed through line 106 to summing circuit 28 for weighting the signal of antenna element 301 with the output of correlation circuit 102 . This is determined by the correlation circuit 102 in the loop I
The negative sign in vector loop IWB shown in adder circuit 28 represents the execution of a minimization process, effectively removing the desired signal from the control signals of the modified LMS algorithm performed in WB.

In the second vector loop 2WB, the reference signal provided from line 26 is provided by an on-epoch sample/hold filter circuit 201 and the feedback signal provided from line 27 is provided by an on-epoch sample/hold filter circuit 203. Each is processed. The processed signal is fed to a correlation circuit 202 and is connected to line 2 for weighting with the output of the correlation circuit 102.
06 to the adder circuit 28. 2nd loop 2
WB increases the desired signal-to-interference power ratio of the control signal of the modified LMS algorithm performed by the correlation circuit 202;
The positive sign shown in adder circuit 28 represents the execution of a maximization process.

The correlation circuit 102 of the vector loop IWB includes a mixer 104 that mixes the outputs of the off-epoch circuits 101 and 103.
, and an integrating circuit 105 that integrates the mixed output. The correlation circuit 202 of the vector loop 2WB is a mixer 2 that mixes the outputs of the on-epoch circuits 201 and 203.
04, and an integrating circuit 205 that integrates the mixed output.

Output of correlation circuit 102 of loop IWB (line 106)
is added to the correlation circuit 20 of loop 2WB by the addition circuit 28.
2 (line 206) and this sum is mixed with the input signal on line 23 by mixer 29 to form the mixed output signal on line 17.

Epoch processing circuits 101 and 201 are integrated into a single unit 3
It is advantageous to assemble the epoch processing circuits 103 and 203 as a single unit 312.

Since both units 311 and 312 have the same form, only unit 311 will be described in detail, but it should be understood that this description also applies to unit 312. Unit 311 is used within each processor 305-308 of FIG. Further, the unit 312 includes each processor 305 to
308, or alternatively, one unit 312 may be provided for all antennas and its output signals used for all processors 305-308.

FIG. 3 is a block diagram of the epoch processing circuit included in the unit 311, and the description of FIG. 3 also applies to the epoch processing unit 312. The output signals are applied to mixers 104 and 204 as shown in FIG. The input signal to the epoch processing circuit is from line 23 for unit 311 and from line 1 for unit 312.
It is given from 7.

The unit 311 includes an envelope detection circuit 313, a threshold unit 314, a clock 315, a counter 316, an early gate signal generator 317, and a late gate signal generator 31.
Contains 8. The input signal from line 23 is sent to the detection circuit 313
The detection circuit 313 outputs the amplitude of the signal envelope to the threshold unit 314. counter 316
counts clock pulses supplied from clock 315. Threshold unit 314 outputs a command signal to counter 316 during the time interval during which detection circuit 313 is outputting a signal amplitude higher than the threshold of unit 314 . This command signal energizes and deenergizes the counters 31, 6 to count the duration of the pulses of the input signal. Counter 316 strobes signal generators 317 and 318.

In the case of a repeating input signal, as is usual in radar communications, signal generator 317 is activated by being strobed to output a fast gate signal as shown in waveform 319. This gate signal temporally rises before the input pulse signal and falls at the end of the input signal pulse. Similarly, signal generator 318 is activated by the strobe and outputs a slow gating signal shown in waveform 320. This gate signal temporally rises at the beginning of the input pulse signal and continues until after the input pulse signal ends. These two signals 319 and 320 are superimposed during the next expected input pulse signal time.

Unit 311 has two gates 321 and 322.2
It also includes two low pass filters 323 and 324 and one subtraction circuit 325. The input terminals of both gates 321 and 322 are connected to the detection circuit 313.
Receives the signal output from 3. Gate 321 is activated by early gate signal 319 of signal generator 317;
During the early gate signal period, the signal from the detection circuit 313 is passed to the filter 323. Gate 322 is activated by slow gate signal 320 of signal generator 318 and passes the signal from detection circuit 313 to filter 3 during the slow gate period.
Pass to 24. Filters 323 and 324 average the signals repeatedly applied by gates 321 and 322. The average values output from filters 323 and 324 are subtracted by subtraction circuit 325 to produce an error signal. This error signal represents the error in the placement of gate signals 319 and 320 relative to the input pulse signal. The error signal is applied to clock 315, which advances or retracts the clock pulses as commanded by the error signal, so that game signals 319 and 320
The superimposed region of is aligned with the input pulse signal. The signals output from early gate 321 and late gate 322 are shown stylized in waveforms 326 and 327.

Unit 311 has two gates 328 and 329.1
It also includes one delay unit 330 and one adder circuit 331. The adder circuit 331 performs an AND function between the early gate signal 319 and the late gate signal 320, and has a logic 1 value during the overlap region of both signals 319 and 320, and a logic 0 value otherwise. line 33 with a value of
Occurs on 2. The overlapping region of both signals 319 and 320 is indicated diagrammatically by 333, and the summation circuit 33
The logic 1 signal output from 1 is shown at 334.

Signal 334 indicates the expected time of the next input pulse signal to arrive on line 23 and is applied to gate 329. Gate 329 is thereby activated and line 23
The signal from the mixer 204 is guided to the mixer 204. We term this the on-epoch part of the transmission of the signal received by antenna element 301. Signal 334 is also applied to the terminal of gate 328 via delay unit 33Q. This activates gate 328 and passes the signal from line 23 to mixer 104. The delay provided by delay unit 330 is sufficient to shift the activation period of gate 328 to a time after the end of the on-epoch by gate 329. The activation period of gate 328 is therefore termed the off-epoch portion of the signal received at antenna element 301.

Explain the operation. The epoch processing circuit of unit 311 tracks the substantially periodic occurrence of pulses of the human input signal on line 23 output from matched filter 22 . This tracking of the input signal pulses is used to operate on-epoch gate 329 and off-epoch gate 328 to sample signal energy during times when the desired signal is received and during times when interfering signals may be received. . During the off-epoch period, interference data is provided and this data is used by the loop IWB (FIG. 2) to direct the null sensitivity towards the interfering signal. During the on-epoch period, the energy of the desired signal is supplied, which is loop 2WB (
2) to maximize the gain of antenna 300 in the direction of the source of the desired signal. processor 305
In the operation, the integral operation of the correlation circuits 102 and 202 converts the pulsed signals output from the epoch gates 328 and 329 into continuous signals, and these continuous signals are supplied to the adder circuit 28 to generate continuously existing weighting coefficients. Note also that a coefficient is formed and this coefficient is applied to mixer 29. Thereby, the epoch processing circuit performs optimal control together with the correlation circuit, and a loop with characteristics of a sample-and-hold filter circuit with temporal filtering is achieved by slow gates and fast gate tracking operations.

Figures 4 and 5 show 1 x 6 wavelengths in the azimuth plane and 2 elevation angles.
It is a diagram showing the gain when zero-sensitivity steering and beam forming are simultaneously performed on a randomly arranged antenna array of five elements with a spread of wavelengths, and three waves of interference signals (Jl, J2, J3) are shown. are assumed to be equal in strength and 10 dB higher than the desired signal at each antenna.

Tanukibon Howata A Interfering signal 1 (Jl) 0°C 0.4° Interfering signal 2 (J2) 0°C 22.3" Interfering signal 3 (J3) 0°C 93.8" Desired signal (S) 0°C 62. 2. FIG. 4 is an optimal antenna pattern obtained with only zero sensitivity control over all signal frequency bands for a given loop bias condition, resulting in a single element "on" static weight vector. In this optimal state, the total interference signal is reduced by about 30 dB, and the desired signal (S) is located on the side of zero sensitivity,
The net improvement in S/J (signal to interference) ratio is about 22 dB. FIG. 5 shows the optimal pattern obtained when zero-sensitivity steering and beamforming are performed using the optimal processor according to the present invention under the same assumption.

In this optimal state, the zero sensitivity near the desired signal (S) is buried and the S/J ratio is further improved by 6 dB.

[Brief explanation of the drawing]

1 is a block diagram of an array antenna with an optimal processor according to the present invention, and FIG. 2 is a block diagram of a broadband spread spectrum temporal processor for one of the set of signal channels of FIG. Figure 3 is a block diagram of the epoch processor in Figure 2, Figure 4 is a zero sensitivity steering simulation pattern in the horizontal plane of the array antenna, and Figure 5 is a diagram of the zero sensitivity steering simulation pattern in the horizontal plane of the array antenna. This is a beam forming/zero sensitivity steering simulation pattern. 1...First vector loop, 2...Self...Second
Vector loop, 11... Mixer, 15...
...Coordinator, 20...AGC circuit,
22...Matched filter, 28...Addition circuit, 29...Mixer, 100...Atmospheric sensitivity steering circuit, 101.103... Off-epoch sample/hold filter circuit, 102...
... Correlation circuit, 104 ... Mixer, 105
... Integration circuit, 200 ... Beam forming circuit, 201.203 ... On-epoch sample/hold filter circuit, 202 ... Correlation circuit, 204 ...Mixa, 205...
・Integrator circuit, 300...Antenna, 301,3
02,303.304...Antenna element, 30
5,306,307゜308...optimal signal processor, 309...addition circuit, 311,312
...Epoch processing circuit unit, 313...
... Envelope detection circuit, 314 ... Threshold unit, 315 ... Clock, 316 ...
... Counter, 317, 318 ... Signal generator, 321, 322. 328. 329...
Gate, 323.324...Low pass filter, 325...Subtraction circuit, 330...Delay unit, 331...Addition circuit. FIG, 4 Zero-sensitivity steering only FIG, 5 Zero-sensitivity steering and beam forming procedure amendment (method) 63.8.25 1. Indication of incident Patent application No. 109825 of 1988
No. 2, Title of the Invention: Beam Forming/Zero Sensitivity Steering Optimal Array 3, Relationship with the Amended Person's Case Applicant Name: Hazeltine Corporation 4, Agent Address: 3-3-1 Marunouchi, Chiyoda-ku, Tokyo Telephone: ) 211-8741 6. Subject of amendment All drawings 7. Contents of amendment

Claims (1)

[Claims] 1. An apparatus for canceling an unnecessary signal received together with a desired signal having a wide spectrum, comprising: (a) a first means for supplying a desired signal and an unnecessary signal received together with the desired signal; (b) zero-sensitivity steering means, which is combined with the first means and includes a first temporal processing means for temporally separating a desired signal and an unnecessary signal and canceling at least a portion of the unnecessary signal; ) a beam forming means that is combined with said first means and includes a second temporal processing means for temporally separating a desired signal and an unnecessary signal and enhancing at least a portion of the desired signal; and (d) said beam forming means. Apparatus comprising zero-sensitivity steering means and second means for coordinating said beamforming means. 2. the first temporal processing means comprises a first optimization control loop coupled to the first means, the first loop having a negative correction output for minimizing unwanted signals; the second temporal processing means coupled to the first means;
a second loop having a positive correction output for maximizing the desired signal; second means for summing the negative correction output and the positive correction output; Claim 1 further comprising a mixer for mixing the desired signal and the unnecessary signal with the sum to generate a mixed output.
Apparatus described in section. 3. The summing means has a first input port coupled to the positive correction output, a second input port coupled to the negative correction output,
3. The apparatus of claim 2, wherein the summed output is a summing circuit coupled to an input of a mixer. 4. The first optimal control loop is coupled to the first means to provide the off-epoch unmixed output.
a second off-epoch sample/hold filter circuit coupled to the mixed output to provide an off-epoch mixed output; and a second off-epoch sample/hold filter circuit for correlating the off-epoch unmixed output and the off-epoch mixed output. Claim 2 comprising a correlation circuit that generates a negative correction output.
The device described. 5. Each epoch filter circuit includes means for tracking the desired signal, and the tracking means includes an early gate and a late gate superimposed on each other during the generation time of the desired signal, and an off-epoch gate and an on-epoch gate driven by the tracking means. 5. The apparatus of claim 4, wherein the gate samples the desired signal and the interfering signal. 6. A second optimal control loop is coupled to the first means to provide an on-epoch unmixed output.
a second on-epoch sample/hold filter circuit coupled to the mixed output to provide an on-epoch mixed output; and a second on-epoch sample/hold filter circuit for correlating the on-epoch unmixed output and the on-epoch mixed output. Claim 2 comprising a correlation circuit that generates a positive correction output.
The device described. 7. Each epoch filter circuit includes means for tracking the desired signal, the tracking means including an early gate and a late gate superimposed on each other during the generation time of the desired signal, and an off-epoch gate and an on-epoch gate driven by the tracking means. 7. The apparatus of claim 6, wherein the gate samples the desired signal and the interfering signal.