JPH01292958A - Power source circuit for automatic circuit incoming equipment - Google Patents

Power source circuit for automatic circuit incoming equipment

Info

Publication number
JPH01292958A
JPH01292958A JP12264388A JP12264388A JPH01292958A JP H01292958 A JPH01292958 A JP H01292958A JP 12264388 A JP12264388 A JP 12264388A JP 12264388 A JP12264388 A JP 12264388A JP H01292958 A JPH01292958 A JP H01292958A
Authority
JP
Japan
Prior art keywords
circuit
incoming signal
power source
power supply
microprocessor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12264388A
Other languages
Japanese (ja)
Inventor
Takao Miyanaga
隆雄 宮永
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Frontech Ltd
Original Assignee
Fujitsu Frontech Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Frontech Ltd filed Critical Fujitsu Frontech Ltd
Priority to JP12264388A priority Critical patent/JPH01292958A/en
Publication of JPH01292958A publication Critical patent/JPH01292958A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To reduce the consumption of a battery by turning on a power source of an incoming signal reception circuit and a detecting means at every prescribed time by an output signal of a clock circuit, turning on a main power source in case an incoming signal has been detected and starting a microprocessor. CONSTITUTION:The title circuit is provided with an incoming signal reception circuit 1 to which a supply of a power source VA provided on terminal equipments 11a-11d has been cut off, detecting means 3, 4 to which a supply of the power source VA for detecting an incoming signal from a main computer 8 has been cut off, and a clock circuit 5 to which a power source is supplied by a main power source of a battery in a microprocessor which has cut off a supply of a main power source VBAT. In this state, by an output signal of the clock circuit 5, the power source VA of the incoming signal reception circuit 1 and the detecting means 3, 4 is turned on at every prescribed time, and in case the incoming signal has been detected, the main power source VBAT is turned on so that the microprocessor 2 is started. In such a way, the consumption of the battery can be reduced.

Description

【発明の詳細な説明】 〔概  要〕 データ通信に用いて好適な回線自動着信装置用電源回路
に関し、 バッテリの消費が少ない回線自動着信装置用電源回路を
提供することを目的とし、 主コンピュータから複数の端末機器に供給される着信信
号によって、端末機器と主コンピュータ間にデータの伝
送を行うようにされた回線自動着信装置において、上記
端末機器に設けられた電源の供給が遮断された着信信号
受信回路と、上記主コンピュータからの着信信号を検知
する電源の供給が遮断された検知手段と、主電源の供給
を遮断したマイクロプロセッサ内のバッテリの主電源で
電源供給が成されている時計回路とを具備し、上記時計
回路の出力信号で一定時間毎に上記着信信号受信回路及
び上記検知手段の電源を投入し、着信信号を検知した場
合に、主電源を投入して上記マイクロプロセッサを起動
してなるように構成する。
[Detailed Description of the Invention] [Summary] The purpose of this invention is to provide a power supply circuit for a line automatic call receiving device which is suitable for use in data communications, and which consumes less battery. In an automatic line termination device that transmits data between the terminal equipment and the main computer using incoming signals supplied to multiple terminal equipment, an incoming call signal when the power supply to the terminal equipment is cut off. a receiving circuit, a detection means for detecting an incoming signal from the main computer when the power supply is cut off, and a clock circuit powered by the main power of a battery in the microprocessor whose main power supply is cut off. and turning on the power of the incoming signal receiving circuit and the detecting means at regular intervals using the output signal of the clock circuit, and when an incoming signal is detected, turning on the main power and starting the microprocessor. Configure it so that it does.

〔産業上の利用分野〕[Industrial application field]

本発明はデータ通信に用いて好適な回線自動着信装置用
電源回路に関する。
The present invention relates to a power supply circuit for an automatic line receiving device suitable for use in data communications.

〔従来の技術〕[Conventional technology]

従来からデータ通信として種々のものが提案され、デー
タベースサービス、パソコン通信サービス、パソコン間
通信等が知られている。特にパソコン間通信ではモデム
を用いてパソコンどうしで電話回線を利用して、データ
の授受を行う場合に300ボー又は1200ボ一程度の
伝送速度であり、大量データの送信を行う場合に長時間
を必要とするため伝送待時間が長くなる問題があった。
Various types of data communication have been proposed in the past, including database services, personal computer communication services, and inter-personal computer communication. In particular, when communicating between computers, the transmission speed is about 300 baud or 1200 baud when sending and receiving data using a modem and a telephone line between computers, and it takes a long time when sending large amounts of data. There was a problem in that the transmission waiting time was increased because of the need for the transmission.

そこで例えばホストコンピュータ側に端末機器からデー
タを伝送する場合にはホストコンピュータ側に電話を掛
けて、ホストコンピュータ側がデータを受は入れる態勢
にあるか否かの確認を行った後に約束した時間にデータ
伝送を行うために人が常に端末機器側についている必要
があった。また、昼間は電話線はピーシであり人手を掛
けずに電話線の空いている夜間に自動的に伝送すること
が好ましい。その度に、ホストコンピュータ側から、端
末機器に着信信号を供給し、その着信信号を受信したと
き、端末機器からデータを自動的に送信開始するように
した回線自動着信装置が提案されている。
For example, when transmitting data from a terminal device to a host computer, the host computer must be called over the phone to confirm whether the host computer is ready to accept the data, and then the data will be sent at the agreed time. It was necessary for a person to be present at the terminal device at all times in order to perform the transmission. Also, since the telephone line is busy during the day, it is preferable to automatically transmit the message without manual intervention during the night when the telephone line is free. An automatic line termination device has been proposed in which a host computer supplies an incoming call signal to a terminal device, and when the incoming signal is received, the terminal device automatically starts transmitting data.

このような回線自動着信装置、特にハンディベルトター
ミナル等では第4図に示す如くマイクロプロセッサ2へ
の主電源■ll□は切断されているが、入力端子T、か
ら入力されるモデム等からの着信信号はCiを受信する
受信回路1には常に主電源■1lA7が供給され、電源
投入状態になっていて、着信信号を受信するとマイクロ
プロセッサが動作して、出力端子T3からデータを伝送
する。
In such automatic line receiving devices, especially handy belt terminals, etc., the main power supply to the microprocessor 2 is cut off, as shown in Fig. 4, but incoming calls from a modem, etc. input from the input terminal T, The receiving circuit 1 that receives the signal Ci is always supplied with the main power source 11A7 and is in a power-on state, and when an incoming signal is received, the microprocessor operates and transmits data from the output terminal T3.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上記従来の構成によると、回線自動着信装置がハンディ
ベルトターミナル等の携帯用のものではバッテリで動作
するものが多いために常時、受信回路1を動作状態にし
ていると、特に待時間が長いものでは消費電流が常に一
定値以上流れて、バッテリを消費する問題があった。
According to the above-mentioned conventional configuration, if the line automatic call receiving device is a portable device such as a handy belt terminal and is often operated by a battery, if the receiving circuit 1 is always in operation, the waiting time may be particularly long. However, there was a problem in that the current consumption always exceeded a certain value, consuming the battery.

本発明は上記の欠点に鑑みなされたもので、バフテリの
消費が少ない回線自動着信装置用電源回路を提供するこ
とを目的とする。
The present invention has been made in view of the above-mentioned drawbacks, and an object of the present invention is to provide a power supply circuit for an automatic call receiving device that consumes less buffer power.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の回線自動着信装置用電源回路は第1図及び第2
図に示されるように、主コンピュータ8から複数の端末
機器11a〜lidに供給される着信信号によって端末
機器11a−1idと主コンピュータ8間にデータの伝
送を行うようにされた回線自動着信装置12において、
端末機器11a〜lldに設けられた電源■、の供給が
遮断された着信信号受信回路1と、主コンピュータ8か
らの着信信号を検知する電源VAの供給が遮断された検
知手段3.4と、主電源V IIATの供給を遮断した
マイクロプロセッサ2内のバッテリの主電源で電源供給
が成されている時計回路5を具備し、時計回路5の出力
信号で一定時間毎に着信信号受信回路1及び検知手段3
.4の電源■。を投入し、着信信号を検知した場合に主
電源VIIAアを投入してマイクロプロセッサ2を起動
させるようにしたものである。
The power supply circuit for the automatic line receiving device of the present invention is shown in FIGS. 1 and 2.
As shown in the figure, a line automatic termination device 12 is adapted to transmit data between the terminal devices 11a-1id and the main computer 8 using incoming signals supplied from the main computer 8 to the plurality of terminal devices 11a-lid. In,
The incoming signal receiving circuit 1 provided with the terminal devices 11a to lld is cut off from the power source (1), and the detection means 3.4 is cut off from the power source VA for detecting the incoming signal from the main computer 8. The clock circuit 5 is equipped with a clock circuit 5 which is supplied with power from the main power source of the battery in the microprocessor 2 from which the supply of the main power supply V IIAT has been cut off, and the incoming signal receiving circuit 1 and Detection means 3
.. 4 power supply■. is turned on, and when an incoming signal is detected, the main power supply VIIA is turned on and the microprocessor 2 is activated.

〔作   用〕[For production]

本発明の回線自動着信装置用電源回路ではマイクロプロ
セッサ2にバッテリからの主電源■、アが供給されず切
断されていても、常にバッテリで電源供給′が行われて
いる時計回路5を用いて一定時間毎に着信信号受信回路
1に電源電圧を投入し、着信信号を監視していて、着信
信号が検出されれば、主電源V!IAアを投入してマイ
クロプロセッサを起動するためにデータ伝送を行うこと
が出来て、バッテリの消耗を極めて少なくすることが可
能となる。
The power supply circuit for an automatic call receiving device according to the present invention uses a clock circuit 5 which always supplies power from the battery even if the main power source (1) or (a) from the battery is not supplied to the microprocessor 2 and is disconnected. The power supply voltage is applied to the incoming signal receiving circuit 1 at regular intervals to monitor the incoming signal, and if an incoming signal is detected, the main power supply V! Data transmission can be performed in order to turn on the IA and start up the microprocessor, making it possible to extremely reduce battery consumption.

〔実  施  例〕 以下、本発明の回線自動着信装置用電源回路の一実施例
を第1図乃至第3図について詳細に説明する。
[Embodiment] Hereinafter, an embodiment of the power supply circuit for an automatic call receiving device according to the present invention will be described in detail with reference to FIGS. 1 to 3.

第1図は本発明の系統図を示すものであるが、第2図に
よって本発明のデータ通信方法を説明する。第2図でホ
ストコンピュータ8は例えば会社の本社に置かれたパソ
コンであり、モデム9を介してパソコンから着信信号C
iを公衆電話回線10に送るためにアナログ信号に変換
を行う。端末機器は例えば会社の複数の営業所に置かれ
た/’tンディベルトターミナルlla、llb、ll
c。
Although FIG. 1 shows a system diagram of the present invention, the data communication method of the present invention will be explained with reference to FIG. In FIG. 2, the host computer 8 is a personal computer located at a company's headquarters, for example, and an incoming signal C is sent from the personal computer via a modem 9.
i is converted into an analog signal in order to be sent to the public telephone line 10. Terminal equipment may be located, for example, at several business offices of a company.
c.

lidであり、公衆電話回線lOからの着信信号C4は
ハンディベルトターミナル1la−11d内のモデムで
デジタル信号に変換されて、入力端子T1 (第1図)
に入力される。着信信号Ciは通常の電話機のベルの呼
出音に対応し、この呼出音は所定周波数に変換され、公
衆電話回線10に送信されるもので第3図(a)に示す
ように所定のデュレーション(例えば2秒)で1秒の着
信信号C1を3回連続して受信したときに端末機器11
3〜lidは着信信号C4を受けたとしてホストコンピ
ュータ8側に端末機器11a−1id側のデータ伝送を
開始する。
The incoming signal C4 from the public telephone line IO is converted into a digital signal by the modem in the handy belt terminal 1la-11d, and then sent to the input terminal T1 (Fig. 1).
is input. The incoming call signal Ci corresponds to the ringing tone of a normal telephone bell, and this ringing tone is converted to a predetermined frequency and transmitted to the public telephone line 10, and has a predetermined duration (as shown in FIG. 3(a)). For example, when the terminal device 11 receives an incoming signal C1 of 1 second duration three times in succession
3-lid start data transmission from the terminal device 11a-1id to the host computer 8 upon receiving the incoming signal C4.

ホストコンピュータ8は、受信可能状態になると複数の
端末機器の1つにデータ伝送を行ってもよいとの着信信
号Ciを伝送する。この着信信号Ciが所定の端末機器
11a〜lidの入力端子T1に供給される。例えば端
末機器11aに着信信号Ciを送ったとすると端末機器
11aは第1図に示す回線自動着信装置12の如く構成
され着信信号受信回路1を有し、着信信号受信回路1の
入力は入力端子T1に接続され、電圧源■4が接続され
ると共に、その出力はアンドゲート回路3の一方の入力
端子に接続されている。さらに回線自動着信装置12内
のマイクロプロセッサ2にも接続されている。着信信号
受信回路lに接続されている電圧源VAは着信信号待ち
の間は後述すると略遮断状態になっている。
When the host computer 8 becomes ready for reception, it transmits an incoming signal Ci indicating that data transmission may be performed to one of the plurality of terminal devices. This incoming call signal Ci is supplied to input terminals T1 of predetermined terminal devices 11a-lid. For example, if an incoming signal Ci is sent to the terminal device 11a, the terminal device 11a is configured like the line automatic incoming call device 12 shown in FIG. is connected to the voltage source 4, and its output is connected to one input terminal of the AND gate circuit 3. Furthermore, it is also connected to the microprocessor 2 in the automatic line termination device 12. The voltage source VA connected to the incoming signal receiving circuit 1 is in a substantially cut-off state while waiting for an incoming signal, as will be described later.

回線自動着信装置12の主電源VIlll、即ち、バッ
テリは常時駆動されている時計回路(時計用LSI)5
及びこの時計回路5で駆動される検出パルス形成回路6
に接続され、常時電圧を供給している。検出パルス形成
回路6によって形成される第3図(C)に示すような一
定周期、例えばC5肥周期で、0.5ms幅のパルスC
をアンドゲート回路3とオアゲート回路7の他方の入力
端子に供給する。
The main power supply VIll of the line automatic call receiving device 12, that is, the battery is a clock circuit (clock LSI) 5 that is constantly driven.
and a detection pulse forming circuit 6 driven by this clock circuit 5
It is connected to the power supply and constantly supplies voltage. A pulse C with a width of 0.5 ms is generated by the detection pulse forming circuit 6 at a constant cycle as shown in FIG.
is supplied to the other input terminals of the AND gate circuit 3 and the OR gate circuit 7.

オフゲート回路7も常時バッテリでバックアップされて
いて、主電源VIATからの電圧が供給されている。オ
アゲート回路7の一方の入力端子はフリップフロップ回
路4の出力端子と接続され、その出力は第2のトランジ
スタTrzのベースに接続されている。第2のトランジ
スタTr!のコレクタは生霊Ill!XVIATに接続
されエミッタは電圧源vAとして上述の着信信号受信回
路l、アンドゲート回路3並びにこれから説明を行うフ
リップフロップ回路4に供給される。
The off-gate circuit 7 is also constantly backed up by a battery and supplied with voltage from the main power supply VIAT. One input terminal of the OR gate circuit 7 is connected to the output terminal of the flip-flop circuit 4, and its output is connected to the base of the second transistor Trz. Second transistor Tr! The collector of is Wraith Ill! The emitter connected to XVIAT is supplied as a voltage source vA to the above-mentioned incoming signal receiving circuit 1, AND gate circuit 3, and flip-flop circuit 4 which will be explained from now on.

フリップフロップ回路4のセット端子にはアンドゲート
回路3の出力パルスBが供給されると共に他の入力端子
に1”入力が与えられ、マイクロプロセッサ2からリセ
ットパルスR3Tもリセット端子R3TFに与えられる
。今、第3図(a)の様な着信信号Ciが入力端子T、
に供給されたとすると、着信信号受信回路1は電圧源■
いから電圧が供給されない“オフ”状態であるが、検出
パルス形成回路6の第3図(C1に示すパルスCが“オ
ン”されるたびに電圧源■、が着信信号受信回路1、ア
ンドゲート回路3、フリップフロップ回路4に断続的に
供給される。
The output pulse B of the AND gate circuit 3 is supplied to the set terminal of the flip-flop circuit 4, and 1'' input is given to the other input terminal, and the reset pulse R3T from the microprocessor 2 is also given to the reset terminal R3TF. , the incoming signal Ci as shown in FIG. 3(a) is input to the input terminal T,
If the incoming signal receiving circuit 1 is supplied with voltage source ■
Therefore, the detection pulse forming circuit 6 is in the "off" state where no voltage is supplied, but each time the pulse C shown in FIG. The signal is intermittently supplied to the circuit 3 and the flip-flop circuit 4.

よって、着信信号受信回路1の出力パルスC4は第3図
(b)に示すようにパルスC(第3図(C))と着信信
号Ci(第3図(a))とが共に“ハイ”の状態でアン
ドゲート回路3から第3図+d>に示すパルスBを出力
する。パルスBの立ち上り部でフリップフロップ回路4
をセットしてラッチし第3図(e)に示すパルスAをマ
イクロプロセッサ2に割込み信号iRQとして供給する
と共に第1のトランジスタTr、を“オン“状態とする
ためコレクタに接続されていたバッテリの主電源V!I
A?はマイクロプロセッサ2にエミッタを介して第3図
(glに示すように電圧■8として供給されるのでマイ
クロプロセッサ2は着信信号C1′を割込データとして
受は入れて、マイクロプロセッサ2内のメモリ内に1回
着信信号C1′が入力されたことをレジストしてリセッ
ト端子R3Tcからフリップフロップ回路4のリセット
端子R3TFに第3図(hlに示すリセットパルスRE
Sを供給して電源を落としてしまう (第3図(Q)の
立下り点AD)。この様な着信信号C4のレジスト動作
を3回行うと、マイクロプロセッサ2は第3図(hlに
示すN0R3Tの様にリセットパルスRESをフリップ
フロップ回路4に供給しないために着信信号Ciが供給
されたことをマイクロプロセッサ2は検出し、ホストコ
ンピュータ8側に端末機器11aのデータ伝送を開始す
ることになる。
Therefore, as shown in FIG. 3(b), the output pulse C4 of the incoming signal receiving circuit 1 is "high" in both the pulse C (FIG. 3(C)) and the incoming signal Ci (FIG. 3(a)). In this state, the AND gate circuit 3 outputs a pulse B shown in FIG. At the rising edge of pulse B, flip-flop circuit 4
is set and latched, and the pulse A shown in FIG. 3(e) is supplied to the microprocessor 2 as an interrupt signal iRQ, and the first transistor Tr is turned on in order to Main power supply V! I
A? is supplied to the microprocessor 2 via the emitter as a voltage 8 as shown in FIG. It registers that the incoming signal C1' has been input once within the period of time, and sends a reset pulse RE shown in FIG. 3 (hl) from the reset terminal R3Tc to the reset terminal R3TF of the flip-flop circuit 4.
S is supplied and the power is turned off (falling point AD in Figure 3 (Q)). When such a registration operation for the incoming signal C4 is performed three times, the microprocessor 2 does not supply the reset pulse RES to the flip-flop circuit 4 as shown in FIG. The microprocessor 2 detects this and starts data transmission from the terminal device 11a to the host computer 8 side.

尚、電圧tAvAの電圧は第3図(「)に示すようにオ
アゲート回路7がゲートされた状態で着信信号受信回路
1、アンドゲート回路3、フリップフロップ回路4、等
の電源電圧として供給される。この電圧Vヶは着信信号
C4が着信信号受信回路1に供給されなければ第3図(
C)に示す検出パルス形成回路6からのパルスCが0.
5msの間“オン”するだけであり、着信信号受信回路
1、アンドゲート回路3、フリップフロップ回路4等の
LSIに流れる電流は漏れ電流だけで殆どバッテリを消
費することはなく主電圧源のバッテリの消耗を抑えるこ
との出来る回線着信装置用電源回路が得られる。
The voltage tAvA is supplied as a power supply voltage to the incoming signal receiving circuit 1, the AND gate circuit 3, the flip-flop circuit 4, etc. with the OR gate circuit 7 gated as shown in FIG. If the incoming signal C4 is not supplied to the incoming signal receiving circuit 1, this voltage V is as shown in FIG.
When the pulse C from the detection pulse forming circuit 6 shown in C) is 0.
It is only "on" for 5ms, and the current flowing through the LSIs such as the incoming signal receiving circuit 1, AND gate circuit 3, and flip-flop circuit 4 is only leakage current, and hardly consumes the battery. A power supply circuit for a line receiving device that can suppress consumption of the line is obtained.

〔発明の効果〕〔Effect of the invention〕

本発明は公衆電話回線のすいている時間にデータ通信を
自動的に行うことが出来ると共に、バッテリの消耗を極
力少なくすることの出来る回線着信装置用電源回路が得
られる効果を有する。
The present invention has the effect of providing a power supply circuit for a line receiving device that can automatically perform data communication during times when public telephone lines are idle and can minimize battery consumption.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の回線着信装置用電源回路の一実施例を
示す系統図、 第2図は本発明の回線着信装置が使用される通信系の系
統図、 第3図は第1図の動作波形図、 第4図は従来の回線着信装置用電源回路図であてる。 1・・・着信信号受信回路、 2・・・マイクロプロセッサ、 3・・・アンドゲート回路、 4・・・フリップフロップ回路、 5・・・時計回路、 6・・・検出パルス形成回路。 特許出願人  富士通機電株式会社 ィズri 来 4961 第4図
FIG. 1 is a system diagram showing an embodiment of the power supply circuit for a line terminating device of the present invention, FIG. 2 is a system diagram of a communication system in which the line terminating device of the present invention is used, and FIG. The operating waveform diagram, Figure 4, is a power supply circuit diagram for a conventional line receiving device. DESCRIPTION OF SYMBOLS 1... Incoming signal receiving circuit, 2... Microprocessor, 3... AND gate circuit, 4... Flip-flop circuit, 5... Clock circuit, 6... Detection pulse forming circuit. Patent applicant Fujitsu Kiden Ltd. IZRI 4961 Figure 4

Claims (1)

【特許請求の範囲】 主コンピュータから複数の端末機器に供給される着信信
号によって、端末機器と主コンピュータ間にデータの伝
送を行うようにされた回線自動着信装置において、 上記端末機器に設けられた電源の供給が遮断された着信
信号受信回路と、 上記主コンピュータからの着信信号を検知する電源の供
給が遮断された検知手段と、 主電源の供給を遮断したマイクロプロセッサ内のバッテ
リの主電源で電源供給が成されている時計回路とを具備
し、 上記時計回路の出力信号で一定時間毎に上記着信信号受
信回路及び上記検知手段の電源を投入し、着信信号を検
知した場合に、主電源を投入して上記マイクロプロセッ
サを起動してなることを特徴とする回線自動着信装置用
電源回路。
[Scope of Claims] An automatic line termination device configured to transmit data between a terminal device and a main computer using incoming signals supplied from a main computer to a plurality of terminal devices, comprising: An incoming signal receiving circuit whose power supply has been cut off, a detection means whose power supply has been cut off for detecting an incoming signal from the main computer, and a main power source of a battery in the microprocessor whose main power supply has been cut off. and a clock circuit to which power is supplied, and the incoming signal receiving circuit and the detecting means are powered on at regular intervals using the output signal of the clock circuit, and when an incoming signal is detected, the main power supply is turned on. A power supply circuit for an automatic line receiving device, characterized in that the power supply circuit for an automatic line receiving device is activated by inputting the above microprocessor.
JP12264388A 1988-05-19 1988-05-19 Power source circuit for automatic circuit incoming equipment Pending JPH01292958A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12264388A JPH01292958A (en) 1988-05-19 1988-05-19 Power source circuit for automatic circuit incoming equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12264388A JPH01292958A (en) 1988-05-19 1988-05-19 Power source circuit for automatic circuit incoming equipment

Publications (1)

Publication Number Publication Date
JPH01292958A true JPH01292958A (en) 1989-11-27

Family

ID=14841048

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12264388A Pending JPH01292958A (en) 1988-05-19 1988-05-19 Power source circuit for automatic circuit incoming equipment

Country Status (1)

Country Link
JP (1) JPH01292958A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4929004A (en) * 1972-07-13 1974-03-15
JPS6121668A (en) * 1984-07-09 1986-01-30 Omron Tateisi Electronics Co Data transmitter

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4929004A (en) * 1972-07-13 1974-03-15
JPS6121668A (en) * 1984-07-09 1986-01-30 Omron Tateisi Electronics Co Data transmitter

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